CA1201529A - Superconducting read-only memories or programable logic arrays having the same - Google Patents

Abstract

Abstract:
An A.C. powered type logic array of very high speed operation employs Josephson devices and can program any desired logic. The logic array comprises a first logic array that delivers AND logic signals from input signals, and a second logic array that delivers OR logic signals from desired ones of the AND outputs. Each of the first and second logic arrays comprises a plurality of bit lines that connect a plurality of arrayed Josephson devices in series at respective rows, and each of which has one end connected to a power source and the other end grounded through a resistor. Word lines are arranged in the column direction of the Josephson device array and are selectively coupled to the Josephson devices. Whether or not the word lines are coupled to the respective Josephson devices of the arrays, is determined by the patterns of the word lines or the patterns of the Josephson devices, whereby to program the desired logic. The system is an improvement over the prior art in facilitating rapid and easy changing of the logic.

Description

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Superconducting read-only memories or programable logic arrays having the same The present invention relates to a programable logic array employing superconducting devices, especially Josephson devices, and also to read-only memories or use in such a logic array.
Since a Josephson device is switched at high speed and dissipates low power, it is expected to be applicable to a digital system such as computer. The prior art has proposed an arrangement wherein a Josephson ~SI having complicated logic is constructed by combining individual AND
circuits and OR circuits. This method, however, has the disadvantage that changes of logic required by a design alteration or correction of erroneous design cannot be made quickly. Particularly, a system employing Josephson devices operates only in an environment of extremely low temperature (about 4K), exhibits as small a signal amplitude voltage as

2.5 mV and achieves circuit operations as fast as several ps. It is accordingly difficult to follow up logic operations with a probe or the like. Therefore, it is impossible to repeat a larqe number of small changes, so that logic changes must be achieved by performing a small number of large changes on the scale of the whole LSI. Consequently, a system employing Josephson devices needs to perform the changes quickly on the scale of the whole LSI, but this is equivalent to re-designing the LSI. The LSI in the prior art, in which ,~

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the logic is organized by the combination of AND circuits and OR circuits, involves a high design cost and a long design time, and it therefore introduces the disadvantage that much expense and a long time are necessary for finishing a system.
U.S. Patent 4,360,898 issued November 23, 1982 to Sadeg M. Faris discloses a programable logic array comprising in combination two logic arrays in each of which Josephson devices are disposed at selected ones of the intersection points between a plurality of superconducting loops and a plurality of superconducting wiring leads or loops in a direction in which they intersect the superconducting loops.
This known programable logic array is driven by D.C. power source means. Therefore, after the operations of each cycle have been performed, the Josephson devices for coupling input signals need to be reset by some method. Another dis-advantage is that, since direct currents flow to the loops in succession, the access speed is low.
An object of the present invention is to provide a fast A.C. powered programable logic array in which the logic can easily he changed and in which the period of time for system design and the expenses thereof can be reduced.
Another object is to provide a programable logic array that can realize an enhanced density of integration.
Still another object is to provide a programable logic array that can equalize the inductances and capacitances of a plurality of bit lines constituting the logic array, whereby stable outputs can be delivered from the respective bit lines.
One construction according to an embodiment of the present invention resides in a superconducting memory type logic array comprising a first logic array including first Josephson devices arranged in the form of an array, first bit lines connecting respective rows of said first Josephson devices in series and each of which has one end connected to a power source and the other end grounded through a resistor, and first word lines arranged in respective columns of said t ~3~

first Josephson devices for selectively coupling input signals to the individual Josephson devices; a second logic array including second Josephson devices arranged in the form of an array, second bit lines connecting respective rows of said second Josephson devices in series and each of which has one end connected to a power source and the other end grounded through a resistor, and second word lines arranged in respective columns of said second Josephson devices for selectively coupling signals to the individual Josephson devices; a connection circuit for connecting AND
outputs of the rows of said first logic array to.said second word lines respectively; and an output circuit for deriving OR outputs of the respective rows of said second logic array.
According to such construction, currents flow through the bits of the logic arrays, to produce logic out-puts, so that high-speed read-out is obtained. It is there-fore possible to assemble an A.C.-driven ultrahigh-speed logic system.
In the drawings:
Figure 1 is a block diagram showing the general arrangement of a first embodiment of the present invention;
Figure 2 shows circu.it diagrams of blocks in Figure l;
Figure 3 is a circuit diagram of another block in Figure l;
Figure 4 is a circuit diagram of a further block in Figure l;
Figures 5a and 5b and Figures 6a and 6b show plan and sectional views respectively of elements in another block in Figure l;
Figure 7 is a characteristic diagram of the element shown in Figures 5a and 5b;
Figure 8 is a block diagram showing the general arrangement of a second embodiment of the present invention;
Figure 9 is a circuit diagram of a block in Figure 8;
Figure lQ is a circuit diagram of another block in Figure 8;

Figures lla and llb and Figures 12a and 12b show plan and sectional views respectively of different examples of elements in a block of Figure 1 or Figure 8;
Figures 13 and 14 show plan views of further examples of elements in this block;
Figure 15 is a circuit diagram of this block which employs the elements in ~igure 14;
Fi~ures 16 and 17 show plan views of further examples of elements in this block;
Figures 18a and 18b and Figures l9a and l9b are plan and sectional views respectively of further examples of element in this block;
Figure 20 is a block diagram of another embodiment of another block in Figure l;
Figure 21 is a circuit diagram of a block in Figure 20;
Figure 22 is a circuit diagram of another block in Figure 20; and Figures 23, 2~ and 25 are plan views of elements in a further block in Figure 20.
Referring to Figure 1, the general arrangement of a programable memory type logic array embodying the present invention will be described. The programable memory type logic array (hereinbelow, termed "logic array") is composed of a first logic array 100, a second logic arra~ 120 and timed inverter circuits 110. In the firs~ logic array 100, a plurality of memory type logic cells (hereinbelow, termed "logic cells") 101 are aligned in the vertical and lateral directions. The logic cells 101 have first word lines 105 common in the vertical direction. Magnetic fluxes generated by word currents that flow through the first word lines 105 via terminals 104 and 104', interlink with the corresponding logic cells 101. The logic cells 101 are connected by first bit lines 103 in the lateral direction. One end of each of the first bit lines 103 is grounded, while the other end is connected to a first bit driver circuit 102. The first bit driver circuits 102 are supplied with electric power through a terminal 106. The outputs of the first bit driver circuits `J

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102 are respectively connected to corresponding timed inverter circuits 111 of the timed inverter circuit group 110 through wiring leads 114. The timed inverter circuits 111 are supplied with electric power through a terminal 112.
In addition, the timed inverter circuits 111 are supplied with a trigger pulse from a trigger terminal 113, and, at the timing thereof, pulse signals are fed from the respective timed inverter circuits 111 to the second logic array 120. The second logic array 120 has a plurality of logic cells 101 aligned in the vertical and lateral directions. The logic cells 101 in the second logic array 120 have second woxd lines 122 common in the lateral direction.
One end of each of the second word lines 122 is connected to the corresponding timed inverter circuit 111, while the other end is connected to a corresponding terminating circuit 123. Magnetic fluxes generated by currents that flow through the second bit lines 122 from the respective timed inverter circuits 111, interlink with the logic cells 101 coupled with the second bit lines 122. The logic cells 101 in the second logic array 120 are connected by second bit lines 124 in the vertical direction. One end o each of the second bit lines 124 is connected to a corresponding second bit driver circuit 121, while the terminal end thereof is grounded. The respective second bit driver circuits 121 are supplied with electric power from a terminal 126.
Figure 2 shows examples of the first bit driver circuit 102 and the timed inverter circuit 111. The first bit driver circuit 102 is constructed of a resistor 200 one end of which is connected to the terminal 106 and the o~her end of which is connected to the first bit line 103 and the wiring 114. This timed inverter circuit 111 is described in detail in, for example, IBM Journal of research and development, Vol. 24, No. 2, March 1980. It is constructed of a first magnetic coupling Josephson OR ci~cuit (3Osephson Interference Device) 214, a second magnetic coupling Josephson OR circuit 215, a current injection type Josephson AND circuit 217 (Current Injection Device), a first resistor ~2~ 9 212, a second resistor 218 and a third resistor 213. The wiring 114 passes near the first magnetic coupling Josephson OR circuit 214, and is terminated through a resistor 210. A
magnetic flux generated by current that flows out through the wiring 114 from the first bit circuit 102, interlinks with the first magnetic coupling Josephson OR circuit 214. A
wiring lead 216 is arranged near the second magnetic coupling Josephson OR circuit 215, and a magnetic flux generated by current that is supplied to the wiring 216 from the terminal 113, interlinks with the second magnetic coupling Josephson OR circuit. The output of the current injection type Josephson AND circuit 217 is connected to the second word line 122.
Figure 3 shows an example of the terminating circuit 123. This terminating circuit is constructed of a resistor 302, one end of which is connected to the second word line 122 and the other end of which is grounded.
Figure 4 shows an example of the second bit driver circuit 121. This second bit driver circuit 121 is constructed of a resistor 301, one end of which is connected to the terminal 126 and the other end of which is connected to an output terminal 125 as well as the second bit line 124.
Figures 5a, 5b, 6a and 6b show the structures of the logic cells 101 for use in the first logic array 100 and second logic array 120 shown in Figure 1. Figure 5a is a plan view of the logic cell in a programed state , while Figure 5b is a sectional view thereof taken along line A - A'. Figure 6a is a plan view of the logic cell in an unprogramed state, while Figure 6b is a sectional view thereof taken along line A - A'.
The logic cell shown in Figures 6a and 6b is such that a base electrode 500 and a counter electrode 501 are opposed through an inuslator layer 510 which is as thin as several nm. A part where the base electrode 500 and the counter electrode 501 confront each other through th0 thin insulator layer is a Josephson junction 504. A control wiring lead 502 is arranged over the base electrode 500 and the counter electrode 501. These portions are stacked and formed 3~5~

on a substrate 550 which includes a ground plane of a super-conducting material and an insulator film covering it. The control wiring 502 corresponds to the first word line 105 in the first logic array 100, and to the second word line 122 in the second logic array 120. In the logic cell in the programed state shown in Figures 5a and 5b, a base electrode 500 and a counter electrode 501 are opposed through an insulator layer 503 which is as thick as several hundred nm, and recesses are provided in parts of the thick insulator layer 503, so that the electrodes confront each other in only the recessed parts through insulator layers 510 which are as thin as several nm. In this case, the recessed parts serve as Josephson junctions 504. In the logic cell shown in Figures 5a and 5b, the two Josephson junctions 504, base electrode 500 and counter electrode 501 constitute a super-conducting loop, and a so-called Josephson interferometer is constructed of the two junctions.
Figure 7 illustrates the relationship between the m~xir~lm superconducting current Im that can flow through the logic cell shown in Figure 5a and 5b, and a control current Ic that flows through a control wiring lead 502. Since the logic cell shown in Figures 6a and 6b has a Josephson junction area larger than that of the logic cell shown in Figures 5a and 5b, the m~i m-lm superconducting current that can flow through the former logic cell is greater than in Figure 7. The base electrode 500 and counter electrode 501 are connected to the first bit line 103 in the first logic array 100, and to the second bit line 124 in the second logic array 120.
The operation of the programable logic array shown in Figure 1 will now be described. In the lateral direction (hereinbelow, termed "bit direction") of the first logic array 100, the plurality of memory cells 101 are connected in series through the first bit lines 103. In a case where current is flowing through none of the first word lines 105, all the logic cells 101 are in the superconducting state, and hence currents fed through the terminal 106 and the resistors 200 flow to ground through the serially-connected logic cells 101. The serially-connected lo~ic cells 101 have the programed state illustrated in Figures 5a and 5b, and the unprogramed state illustrated in Figures 6a and 6b. Since, in the logic cell 101 in the unprogramed state shown in Figures 6a and 6b, the maximum supe.rconducting current permitted to flow therethrough is great, this logic cell remains in the superconducting state even when the current is caused to flow through the first word line 105 located therein. As regards the logic cell 101 in the programed state shown in Figures 5a and 5b, the relationship between the current of the first word line 105 and the maximum superconducting current permitted to flow through this logic cell 101 is illustrated in Figure 7~ In a case where no current flows through the word line 105, the logic cell has an operating point A in Figure 7 and is in the superconducting state. In contrast, when current flows through the word line 105, the operat.ing point shifts to a point B in Figure 7, the non-superconducting state is established and the current that had been flowing through the logic cell 101 is cut off. Therefore, the current that had flowed to the serially-connected logic cells 101 through the first bit line 103 flows to the timed inverter circuit 111 through the wiring 114. The logic cells 101 are connected in series in the bit direction, and even when one of them has shifted into the non-superconducting state, the current flows to the timed inverter circuit 111. Accordingly, the serially-connected logic cells 101 and the first bit driver circuit 102 constitute an OR logic circuit for the signal of the wiring 114 and the signals of the first word lines 105 located in the logic cells 101 in the programed state. The timed inverter circuit 111 supplies the inverted signal of the signal of the wiring 114 to the second word line 122 of the second logic array 120 at a timing that is synchroniæed to a trigger signal applied from the trigger terminal 113. An OR
logic signal formed by the first logic array 100 is inverted by the timed inverter circuit and becomes an AND signal.
Similarly to the first logic array 100, the second logic array ~' ~ rs~

120 executes the OR logic operation for the signals o the second word lines 122 and delivers the resultant OR signals to the output signal terminals 125.
In the above embodiment, the desired logic can be programed by selectively programing the logic cells 101 which are arrayed in the logic arrays 100 and 120. That is, the desired AND signals of signals applied across the input terminals 104 and 104' are obtained in the logic array 100, and the desired OR signals of these output signals are obtained in the logic array 120, so that the desired logic signal combining the OR logic and AND logic can be obtained.
Figure 8 shows a second embodiment according to the present invention. The programable logic array shown in Figure 8 is constructed of a first logic array 100', affirmative driver circuit group 600 and a second logic array 120. The second loyic array 120 in Figure 8 has the same arrangement as the second logic array 120 shown in Figure 1.
The first logic array 100' in Figure 8 is constructed of aligned logic cells 101, bit driver circuits 102', first word lines 105 and first bit lines 103. The affirmative driver circuit group 600 is constructed of a plurality of affirmative driver circuits 601. Figure 9 shows an example of the bit driver circuit 102'. The bit driver circuit 102' has an arrangement wherein two resistors 801 and 802 are connected in series and wherein one end of the series connection is grounded, while the other end is connected to a terminal 106. The middle point of the serially-connected resistors is connected to the first word line 103. Figure 10 shows an example of the affirmative driver circuit 601.
This affirmative driver circuit 601 is constructed of a cùrrent injection type Josephson AND circuit 804 and a resistor 803. The first bit line 103 is grounded through the current injection type Josephson AND circuit 804, the out-put of which is connected to the second word line 122. The current injection type Josephson AND circuit is described in detail in, for example, IBM Journal of research and 5~

development, Vol. 2~, No. 2, March 1980.
The operation of theprogra~able logic array shown in Figure 8 will now be described. In a case where no current flows through the first word lines 105 of the first logic array 100', all the logic cells 101 are in the superconducting state, and hence currents flowing through the terminal 10G and the resistors 801 flow through the logic cells via the first bit lines 103. When, even in one of the logic cells 101 connected in series in the bit direction and programed as illustrated in Figures 5a and Sb~ current flows through the first word line 105, the current that had been flowing through the logic cell is cut off, and the current that had been flowing through the first bit line 103 flows to ground through the resistor 802. It is to be understood lS that the current flowing through the irst word line 105 and the current flowing through the first bit line 103 are subjected to a NOR logic operation, namely, an AND logic operation. The si~nal of the first bit line 103 is applied to the second word line 122 by the current injection type AND circuit 804 in synchronism with a trigger signal that is applied from a trigger terminal 113. The operating principle that the OR logic operation is executed by the second logic array 120, is as explained with reference to Figure 1. It is apparent from the foregoing that the programable logic array shown in Figure 8 effects the same operations as those of the programable logic array shown in Figure 1.
The logic arrays used in the first and second embodiments stated above are programed by bringing the individual logic cells 101 into the structure shown in Figures 5a and 5b or Figures 6a and 6b. The structures of the logic cells 101 are not restricted to those illustrated in Figures 5a and 5b and Figures 6a and 6b. As an example of a different structure, all logic cells can have the same configuration in the portions of the Josephson junctions, and the coefficients of magnetic coupling with the word lines can be made unequal between the logic cells to be programed and those not to be programed. As such programable logic cells, various forms can be adopted.

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Figures lla and llb and Figures 12a and 12b show an example of the alternative structure. Figure lla is a plan view oE a programed logic cell, while Figure llb is a sectional view thereof taken along line A - A'. Figure 12a is a plan view of an unprogramed logic cell, while Figure 12b is a sectional view thereof taken along line A - A'. In the logic cell shown in Figures lla and llb, a control wiring lead 502 passes over a Josephson junction 504, and the coefficient of magnetic coupling between them is great.
In contrast, in the logic cell shown in Figures 12a and 12b, a control wiring lead 502 is formed so as to make a detour around a Josephson junction 504, and the coefficient of magnetic coupling between them is small. The other symbols in these figures indicate the same members as in Figures 5a, 5b, 6a and 6b, respectively. When the logic cells illustrated in Figures lla and llb and Figures 12a and 12b are employed in the logic arrays 100 and 120, the inductances and capacitances of the respective bit lines become uniform.
Thus, waveforms at the time at which pulse currents are caused to flow through the bit lines are made uniform, and operations at read-out are stabilized. In addition, storage at a high density is permitted.
Figure 13 shows still another example of the logic cell 101. In this logic cell, a control line 502 is branched into a first subline 502A which passes near a Josephson junction 504 and a second subline 502B which detours around it. This logic cell is programed in such a way that either a portion 510 or a portion 512 is blown out by irradiating it with a laser beam. A logic array employing this logic cell is undesirable for mass-producing arrays of the same logic, but it is meritorious when correcting or altering logic frequently, because it can be programed immediately before its assemblage into a system.
Figure 14 shows the setup of still another logic cell. In this logic cell, logic cells of 2 bits are comprised, and two control lines 502-1 and 502-2 are allotted to a single Josephson element. The control line of the logic cell, 5~9 namely the word line in the logic array, is formed by either a path indicated by solid lines or a path indicated by broken lines, whereby the logic cell is programed.
Figure 15 shows a circuit diagram of the case where the logic cell of Figure 14 is applied to the first logic array 100 of Figure 1. With the illustrated example of programing, when logic signals A, B, C and D are respectively applied to word lines lOS-l, 105-2, 105-3 and 105-4, by way of example, output signals indicative of logic B-D and logic A-B-D are respectively provided from output terminals 104-1 and 114-4.
Figures 16 and 17 show a further example of the logic cell. When programing this logic cell, the width of a control line 502 is made small over a Josephson inter-ferometer, as shown in Figure 16, and in the unprogramed logic cell it is made large, as shown in Figure 17.
In the above modifications of the logic cells 101, the Josephson device may include a single junction or may well be a Josephson interferometer having a plurality of junctions.
Figures 18a and l~b and Figures 19a and l9b show a yet further example of the logic cell. In this example, when programing the logic cell, the distance between the two Josephson junctions 504 of a Josephson interferometer is made long, as shown in the plan view of Figure 18a and the sectional view of Figure 18b, whereas when not programing thedistance between the two Josephson junctions 504 is made short, as shown in the plan view of Figure l9a and the sectional view of Figure l9b.
Figure 20 shows a logic array 100" which is used instead of the first logic array 100 of the embodiment illustrated in Figure 1. This logic array 100" is employed in combination with the timed inverter circuits llO and second logic array 120 explained with reference to Figure 1.
Referring to Figure 20, aligned logic cells 101' are connected through first bit lines 103 in the lateral direction (bit direction). The terminal end of the first bit line 103 is grounded, while the other end is connected to s~

a first bit driver circuit 102. In the vertical direction ~word direction) of the logic cells 101', two common word lines 105a and 105b are arranged. One end of each of the two word lines 105a and 105b is connected to a terminating circuit 901, while the other end is connected to a word driver circuit 900. Figure 21 shows an example of the word driver circuit 900. The circuit shown in Figure 21 is what is called "~elf Gate AND circuit", and is described in detail in, for example, IE3 SC-13, No. 5 (1978) 583 - 590 by ~. Davidson. The circuit depicted in Figure 21 is constructed of foux magn~tic coupling Josephson OR circuits 910, 911, 912 and 913, and four resistors 914, 915, 916 and 917. It has the function of supplying the word line 105a with the same signal (affirmative signal) as a signal applied lS to a terminal 104 and suppl~ing the word line 105b with the inverted signal thereof, in synchronism with the timing at which a voltage is applied to a terminal 902. Figure 22 shows an example of the terminating circuit 901. In the terminating circuit 901, the word lines 105a and 105b are grounded through resistors 916 and 917.
Figures 23, 24 and 25 show the structures of the individual logic cells 101' in the logic array 100" of Figure 20. Among them, Figures 23 and 24 illustrate the structures of the logic cells in programed states, and Figure 25 illustrates the structure of the unprogramed logic cell. In the logic cell of Figure 23, only the word line 105a passes over the logic cell, while, in the logic cell of Figure 24, only the word line 105b passes the same. That is, the affirmative signal of the signal applied to the terminal 104 is programed in the logic cell of Figure 23, and the negative signal in the logic cell of Figure 24. There-fore, the logic cell of Figure 23 acquires the non-supercon-ducting state when current has flowed through the word line 105a, and the logic cell of Figure 24 acquires it when current has flowed through the word line 105b. In the logic cell of Figure 25, both the word lines 105a and 105b detour around the logic cell. Therefore, even when currents have flowed through both the word lines 105a and 105b, the logic cell remains in the superconducting state.
When the circuit which generates the aEfirmative and negative signals of the input signal and applies them to the respective word lines as illustrated in Figure 20 is added to the first logic array of Figure 1, logic outputs based on both the affirmative and negative signals of -the input signal can be obtained, and hence a programable logic array of wider applications can be realized.
The individual logic arrays 100, 100' and 120 of the foregoing embodiments fulfill the function of read-only memories which operate at high speed. In order to use such memory as a random access type read-only memory the stored contents of which are read out by appointing desired addresses, the word lines and bit lines may be furnished with decoders for decoding address signals so as to extract the information from desired cells in the logic array.
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Claims (16)

Claims:

1. A superconducting programable logic array comprising:
a first logic array including;
first Josephson devices arranged in the form of an array, first bit lines connecting respective rows of said first Josephson devices in series and each of which has one end connected to a power source and the other end grounded through a resistor, and first word lines arranged in respective columns of said first Josephson devices for selectively coupling in-put signals to the individual Josephson devices, a second logic array including;
second Josephson devices arranged in the form of an array, second bit lines connecting respective rows of said second Josephson devices in series and each of which has one end connected to a power source and the other end grounded through a resistor, and second word lines arranged in respective columns of said second Josephson devices for selectively coupling signals to the individual Josephson devices, connection means for connecting AND outputs of the rows of said first logic array to said second word lines respectively; and output means for deriving OR outputs of the respective rows of said second logic array.

2. A superconducting programable logic array according to Claim 1, wherein said connection means is composed of Josephson inverter circuits for inverting OR outputs of the input signals obtained from the respective first bit lines and delivering the inverted outputs to said second word lines in synchronism with a predetermined trigger signal.

3. A superconducting programable logic array according to Claim 1, wherein said connection means is composed of Josephson gate circuits for delivering AND outputs of the input signals obtained from the respective first bit lines to said second word lines in synchronism with a predetermined trigger signal.

4. A superconducting programable logic array according to Claim 1, wherein each of the Josephson devices to which the signals of said first and second word lines are coupled is a Josephson interferometer having a plurality of Josephson junctions, and each of the Josephson devices to which the signals are not coupled is a Josephson device having a single Josephson junction whose area is larger than a total area of said plurality of Josephson junctions.

5. A superconducting programable logic array according to Claim 1, wherein all said Josephson devices have substantially the same configuration, coefficients of magnetic coupling with said first and second word lines being unequal as between the Josephson devices to which the signals of said word lines are coupled and those to which the signals are not coupled.

6. A superconducting programable logic array according to Claim 5, wherein the word lines are arranged near said Josephson devices to which the signals thereof are coupled, and they are arranged so as to detour around said Josephson devices to which the signals thereof are not coupled.

7. A superconducting programable logic array according to Claim 5, wherein each of said word lines includes a first branch wiring lead arranged near a Josephson device, and a second branch wiring lead that detours around said Josephson device, wherein one of said first and second branch wiring leads is selectively blown out.

8. A superconducting programable logic array according to Claim 5, wherein said first and second word lines are narrow near said Josephson devices to which the signals of said word lines are coupled and are wide near said Josephson devices to which the signals thereof are not coupled.

9. A superconducting programable logic array according to Claim 1, wherein signals of a plurality of word lines are selectively coupled to the individual Josephson devices arranged in each column.

10. A superconducting programable logic array according to Claim 1, wherein each of said Josephson devices is constructed of a Josephson interferometer having a plurality of Josephson junctions, a distance between the plurality of Josephson junctions being longer in the Josephson devices to which the signals of said first and second word lines are coupled than in the Josephson devices to which they are not coupled.

11. A superconducting programable logic array according to Claim 1, further comprising a plurality of self AND circuits each of which generates an affirmative signal and a negative signal of the input signal in synchronism with a predetermined timing signal and outputs of which are respectively connected to said first word lines.

12. A superconducting programable logic array according to Claim 11, wherein two word lines connected to outputs of each of said self gate AND circuits are selectively coupled to the Josephson devices that are arranged in each row of said first logic array.

13. A superconducting read-only memory comprising:
Josephson devices arranged in the form of an array;
bit lines connecting respective rows of said Josephson devices in series and each of which has one end connected to a power source and the other end grounded through a resistor;
word lines arranged in respective columns of said Josephson devices and selectively coupled to the individual Josephson devices, depending upon whether they pass near said individual Josephson devices or detour around them; and a read-out circuit for deriving outputs from said bit lines.

14. A superconducting read-only memory according to Claim 13, wherein a plurality of word lines are selectively coupled to the individual Josephson devices that are arranged in each column.

15. A superconducting read-only memory comprising:
Josephson devices arranged in the form of an array;

bit lines connecting respective rows of said Josephson devices in series and each of which has one end connected to a power source;
word lines arranged in respective columns of said Josephson devices and selectively coupled to the individual Josephson devices, depending upon their widths near said individual Josephson devices; and a read-out circuit for deriving outputs from said bit lines.

16. A superconducting read-only memory comprising:
Josephson devices arranged in the form of an array;
bit lines connecting respective rows of said Josephson devices in series and each of which has one end connected to a power source;
word lines arranged in respective columns of said Josephson devices and selectively coupled to the individual Josephson devices; and a read-out circuit for deriving outputs from said bit lines;
wherein each of said Josephson devices is a super-conducting quantum interferometer having a plurality of Josephson junctions, and wherein a distance between said plurality of Josephson junctions is longer in the Josephson devices to which the signals of said word lines are coupled than in the Josephson devices to which they are not coupled.