CA1164101A - Method and apparatus for conversion of signal information between analog and digital forms - Google Patents

Abstract

ABSTRACT

Signal information is converted between analog and digital form in a two-step process employing con-version apparatus having stable, but not necessarily highly accurate components. The component tolerances on such conversion apparatus are much greater than those normally allowed on conventional conversion apparatus of equal accuracy. In an A/D conversion, an analog signal is first converted into an (n+m)-bit digital word in a special purpose digital code unique to the specific A/D conversion apparatus. The (n+m)-bit word is then translated into an n-bit word in binary digital code in accordance with a predetermined relationship therebetween. In a D/A conversion, an n-bit digital word in a binary digital code is first translated into a corresponding (n+m)-bit digital word in the special purpose digital code. The (n+m)-bit word is then con-verted into an equivalent analog signal; the latter step being performed by a conversion apparatus unique to the special purpose digital code. A plurality of A/D and D/A converters suitable for use with the present invention are disclosed. A number of converter calibra-tion techniques are also disclosed.

Description

~64~1 The present invention relates to a method and apparatus for converting signal information between analog and digital forms, and more particularly to A/D conversion device that employs stable but not highly accurate components for performing the conversion, and its associated method of operation.
This application is a divisional application of applicant's Canadian Application Serial No. 328,491, filed May 28, 1979.
There are many existing A/D and D/A converter designs for converting signals from analog to digital form and vice versa. Generally, in the conversion of a digital signal to a corresponding analog signal each bit of the digital signal is converted to a scaled analog equivalent in accordance with its bit position, and summed with all other proportionately scaled analog signals to produce a total analog signal that corresponds to the digital signal. A typical method of converting an analog signal into digital form is to successively compare the analog signal with subdivisions of a reference signal, each subdivision representing one bit and being related to other subdivisions through a power of two.
Whether the conversion is from analog-to-digital or from digital-to-analog, the converters generally require components of relatively high precision to assure adequate accuracy and resolution. If component values are not kept within a close tolerance of their nominal values, then the cumulative effect of excess tolerances will be reflected in converted signals that do not accurately correspond to ms/d)~

~1641~

the original signal. Specifically, excess component tolerances ~ay cause an analog signal to be converted into a digital representation that is incorrect in one or more of the lower order bits and similarly may cause a digital signal to be converted into an analog si~nal whose magnitude corresponds to a similar but different digital signal, In summary, the accuracy of the converter is a direct function of the accuracy o~ the components, or, stated otherwise, the number of bits that can be handled by a converter is limited by the accuracy of the converter components.
The current thrust in electronics design is toward microelectronics, where LSI technology allows an entire circuit to be laid down in monolithic form on a single chip. If a circuit is to be produced in suffi-ciently large quantity, LSI technology affor~s signifi-cant savings in circuit size and cost. However, one recognized limitation of LSI technology is the in-ability to closely control the tolerances of circuit components. See in this regard, J. D. Meindl, "Micro-electronic Circuit Elements", Science American, Sept.
1977, at 70, 76, There are methods for improving the accuracy of component values, e.~. laser trimming, hut these methods too have their limitations and require additional chip fabrication costs that may be even so great as to defeat the cost-effectiveness of monolithic c.ircuitry.
The present state of lhe art allows D/A and `A/D converters to be fabricated on an LSI chip with an 30 upper limit of accuracy on the order of 2 10 to 2 12 of maximum value~ i,e. ten to twelve bits, The general precision of LSI circuit components does not ~enerally permit the desi~n of converters with resolution ~eyond that bit level. However/ there are numerous applications for converters with up to sixteen bits.

It is an objective of the present invention to realize the efficiencies of LSI technology with a converter design and associated method of operation that accommodates imprecise component values without a corresponding reduction in converter accuracy.

DISCLOSURE OF T~E INVENTION
The present invention is a method and apparatus adapted for A/D signal conversion that affords a high degree of converter accuracy without requiring highly accurate converter components.
Broadly, the invention contemplates a converter apparatus and associated method of operation that performs the conversion in two basic steps. The first step is the transformation of the analog signal into a unique digital representation in a general digital ormat; the generalized digital format is not necessarily based on a coding scheme where each digital bit position represents a power of two.
The second step converts the unique digital representation in the generalized digital format into an equivalent representation in binary format, e.g. where each bit position represents a power of two. In the reverse process of digital-to-analog conversion, the normal binary digital si~nal is first converted into an equivalent signal in the general digitized format. The second step is conversion of the general digitized signal into an analoa equivalent.
Specifically, the invention relates to a method for converting an analog signal to an equivalent digital word in an n-bit digital word code where the weight of each of the bits in the n-bit digital word code is dependent upon its mg/~- - 3 -1~641~1 bit position, the method comprising: converting the analog signal to a corresponding word in a special-purpose (n+m)-bit digital word code, wherein the weight of each bit in the (n+m)-bit digital word code is dependent upon its bit position;
and translating the corresponding word in the (n+m)-bit digital word code to the equivalent word in the n-bit digital word code.
In its device aspect, the invention relates to a device for converting an analog signal to an equivalent digital word in an n-bit digital word code where the weight of each of the bits in the n-bit digital word code is dependent upon its bit position, the device comprising;
converter means, responsive to an analog signal for converting the analog signal to a corresponding word in a special-purpose, (n+m)-bit digital word code, where the weight of each bit in the (n+m)-bit digital word code is dependent upon its bit position; and translator means, responsive to the corresponding (n+m)-bit word, for translating the ~n+m)-bit word to the equivalent n-bit word.
The invention is generally applicable to converter designs that use components that have a predetermined ratio to one another, whether it be 2:1, 1:1, or some other ratio.
For example, a weighted-resistor D/A converter has N
resistors for the conversion of an N-bit digital signal to an analog signal, where each of the N resistors has a resistance with a 2:1 ratio to the resistor in the immediately preceding stage. Other conventional converter forms accomplish essentially the same weighting of each digital bit in accordance with its bit position by using components having a predetermined ratio to one anotherO

mg/~ - 4 -The present invention may be used with a converter where the components are imprecise relative to usual conver-ter component tolerances. More specifically, each component has associated with it a tolerance limit, but that tolerance limit is larger than normally acceptable tolerance limits for the particular converter design and the number of digital bits that it is to handle. The use of imprecise converter components is compensated for by using additional bits to compensate for errors. A converter modified in this manner will perform high accuracy D/A and A/D conversions, but not necessarily in agreement with conventional binary digital code. Stated otherwise, for each analog signal of a specific magnitude the A/D converter will produce a unique digital signal, but not necessarily encoded in the usual binary or power-of-two format. This non-binary digital code was previously characterized as a generalized digital code.
The invention, therefore, contemplates a secondary conversion step where the generalized digital code is translated into binary digital code or vice versa. The generalized digital code associated with each individual converter will be unique to that converter, owing to the imprecise nature of its component values. Accordingly, each converter is tested to determine what output signal will result for each level of input signal. A table or other type of cross-reference is generated to establish a conversion between the generalized digital code uniquely associated with the converter and conventional binary digital code. The conversion between the generali~ed digital code and binary digital code can be established mg~ii - 5 -:11641~1 through an exhaustive testing process performed upon all newly fabricated LSI chips. Alternately, a statistically-based sample of test signals can be used.
In the preferred embodiment of the invention, the conversion between the code types is implemented as a look-up table in a PROM (programmable read-only-memory) or similar type storage device. The generalized digital code from the A/D converter is used as an address for the corresponding binary digital code. The translation between code types is accomplished by putting the generalized digi-tal code on the address lines to the PROM and accessing the corresponding binary digital code stored at thataddress.
Conversely, with a D/A converter, the binary di~ital input signal is used as an address for the correspond.ng word in the generalized digital code.
Although the preceeding description is in terms of a binary digital code being the desired or conventional digital code, the invention is applicable to any desired digital code. The bits of the desired digital code ma~
have any set of desired relationships between bits, for example, binary-coded decimal or Gray coded binary.
The significance of the n+m bits of the special purpose code can be patterned after the normal n-bit code.
For example, n bits of the n+m bit code may have the same nominal significance as the bits of the n-bit code. The m bits of the n+m bit code may have the same nominal sig-nificance as some of the low order bits of the n-bit code.
Alternately, the n+m bits of the special purpose code need not be patterned after or repetitive of bits of the normal n~bit code. The only limitation on the special purpose code is that every analog value in the range represented by the normal n-bit code can also be accurately represen-tea by the special purpose (n+m)-bit code. For example, the ln+m)-bit code can have smaller ratios between adjacent bit weights, instead of having n bits patterned directly after the normal n-bit code and m bits repetitive of one or more selected bits of the n-bit code. Other variations are also ~6~3L01 allowab].e within this more general level of the invention.
In this manner the invention can adapt a great variety of D/A and A/D converter designs to LSI techno-log~ and achieve high conversion accuracy without being limited b~ the inherently imprec:ise parameter values of LSI circuit components.
BRIEF DESCRIPTION OF DRAWINGS

FIGURE 1 iS a block-diagram representation of an analog-to-digital conversion device in accordance with the present invention, also illustrating its associated method of operatio~; ~
FIGURE 2 is a block-diagram representation of a digital-to-analog conversi.on device in accordance with the present invention, also illustrating its associated method of operation;
FIGVRE 3 is a schematic representation of a general, parallel digital-to~analog converter;
FIGURE 4 is a schematic representation of a general, parallel digital-to-analog converter modified in accordance with the present invention;
FIGURE 5 iS another schematic representation of a general, parallel digital-to-analog converter modified in an alternative manner in accordance with the present in-vention;
FIGURE 6 is a schematic representation of a parallel, weighted-resistor digital-to-analog convexter in accordance with the present invention;
FIGURE 7 is a schematic representation of a parallel, resistor-ladder, digital-to-analog converter in accordance with the present i.nvention;
. FIGURE 8 is a schematic representation of a general, serial digital-to-analog converter;
FIGURE 9 iS a schematic representation of a general, serial digital-to-analog converter, modified in accordance with the present invention;

1~641()~

FIGURE 10 is a schematic representation of a general, parallel-feedback ana].og-to-digital con~erter in accordance with the present invention;
FIGURE 11 is a schematic representation of a servo analog-to-digital converter in accordance with the present invention;
FIGURE 12 is a schematic representation of a successive-approximation analog-to-digital converter in accordance with the present invention;
FIG~RE 13 iS a schematic representation of a general serial analog-to-digital converter;
FIGURE 14 iS a schematic representation of a general serial analog-to-dig.ital converter modified in accordance with the present invention;
FIGURE 15 is a schematic representation of a cascade-type analog-to-digital converter modified in accordance with the present invention;
FIGURES 16 and 17 are schematic representations of first and second types of single bit conversion stages forming the enumerated A/D conversion stages of FIGURE
15;
FIGURE 18 iS a timing diagram showing the re-lationship of various timing signals used in the conver-ters of the preceding figures;
FIGURE 19 iS a block-diagram representation of an analog-to-digital converter incorporating the present invention controlled by a programmable process.ing unit;
FIGURE 20 is a block-diagram representation of a digital-to-analog converter incorporating the present invention controlled by a programmable processing unit;
and . FIGURES 21~ 22 and 23 are flow charts illustrating respective first, second and third methods for calibrat-in~ an analog-to-di~ital conversion device of the present invention.

~641~

BEST MODE FOR CARRYING OUT T~E INVENTION
I . INTRODUCTION
The present invention is an improvement in the design and method of operation of devices for con-verting signal Information between analog and digital form. The improvement concerns the relaxation of the normally stringent tolerances that are imposed on the components of these conversion de~ices.
In conventional converter design, the component tolerances are determined by the desired accuracy of the converter; the greater the accuracy~ the more stringent the component tolerances. It is desirable to develop an improved converter design and associated method of operation that provides high conversion accuracy, without a corresponding reduction of component tolerances. An immediate benefit of such a converter design would be the ability to adapt the design and method of operation to large scale integrated (LSI) circuitry, where the inability to closely control the values of components on an LSI chip has limited converter accuracy in that technology.
In overview, the present invention per~orms the conversion in two steps, whether an A/D conversion or a D/~ conversion. The initial step, in either case, is the conversionfrom the original form of the signal into a special purpose digital code having a number of bits in excess of the number of bits of the normal digi-tal code. For example, if the normal digital code has an n-bit word, the special purpose digita~ code will have an (n+m)-bit word. The additional m bits are generally chosen to be repetitive of certain of the low order bits of the n-bit word. The second step in the conversion process then converts the ~n+m)-bit word to the final form in accordance with a pre-established ~6410~

relationship between the special purpose diyital code and the normal n-bit code.
The special purpose (n + m~ - bit digital code is a unique function of each converter incorporating the invention and, in fact, is fortuitous in nature within a permissible range of possibilities. Each converter is allowed a tolerance on its component values that is larger than the tolerance allowed on a normal converter of th~
same accuracy. The increased tolerances cause the conver-ter to transform an analog (or digital) input s~gnal into a corresponding digital (or analog) output signal whose value cannot be determined without knowledge of the actual component values for that specific converter. Accordingly, the relationship between the input and output signals of the converter is unique to that converter and reflects the actual values of the components employed.
A converter incorporating the present invention is allowed larger component tolerances by increasing the number of bit positions in the special purpose digital code.
More specifically, the special purpose digital code word uses n ~ m bits to obtain n bit accuracy, where m = 1, 2, ~he additional m bits are commonly chosen to be repetitive of the lowest or ~ext-to-lowest order bits of the normal n-bit digital word.
The invention is hereinafter disclosed in a number of alternative embodiments, particularly as modified forms of A/D and D/A conversion devices disclosed in the P~ 10 --~64~1 following series of articles: Schmid, D/A Conversion, Electronics Design 22, October 24, 1968, pp. 49 - 88;
Schmid, A/D ~onverslon, Part 1, Electronic Design 25, December 5, 1968, pp. 49 - 72; and Schmid, A/D Conver-sion, - Part 2, Electronic Design 26, December 19, 1968, pp. 57 - 76. However, the invention ~164101 is not li~ited in applic~tion to the specific converter types in this disclosure II. A/D AND D/A CONVERSIO~ SYSTEMS
FIGURE l is a block diagram representation of an analog-to~ditigal conversion system (A/D) incorporat-ing the present invention. The function of the A/D
system is to receive an analog input signal and convert it into an equiyalent n-bit binary digital output sig-nal. The choice of a binary code format for the output signal, however, is merely exemplary; other forms of digital codes are likewise adaptable for use with the present invention. The system of FIGURE 1 is described as follows:
A signal representing a condition of a physical variable is received on line 14 by a sensor or transducer 12. The sensor 12 outputs a corresponding analog signal, typically an electrical voltage or current, on line 16.
The analog signal on line 16 is received by an analog-to-special purpose digital converter 18. The converter 18 performs a conversion of ~he analog signal into an (n+m)-bit digital word in a special purpose digital code uniquely associated with the converter. The (n+m)-bit word is trans-mitted on cable 20 to translator 22. The function of the translator is to convert the (n+m)-bit digital word to a corresponding n-bit binary coded digital word. In practice, the translator 22 may be a memory unit containing a look-up table giving the conversion between the (n+m)-bit digital word in the special purpose digital code and the correspond-ing n-bit digital word in the binary digital code~ One method is to us~ the (n+m)-bit digital word as an address for the memory location of the corresponding n-bit binary digital word.
FIGURE 2 is a block diagram representation of a digital-to-analog (D/A) conversion system incorporating ~6410~

the present invention~ The function of the D/A conversion system is to receive an n-bit digital signal in binary ox other form of digita~ code and convert it into an equivalent analog signal. The D/A conversion system is described as follows.
The D/A conversion system of FIGURE 2 includes a translator 32 that receives an n-bit binary digital signal on cable 34. The function of translator 32 is to convert the n-bit binary digital signal into a correspond-ing (n+m)-bit word in a special purpose digital code on cable 36. The (n+m)-~it word in the special purpose code is received by a converter 3~ The function of the con-verter 38 is to convert the (n+m)~bit word into an equiva-lent analog signal appearing on line 40. The analog sig-nal on line 40 is received by the actuator 42 that ampli-fies or otherwise buffers the signal before transmitting it on line 44 to an analog device.
The translator 32 may, like the translator 22 of FIGURE 1, contain a look-up table relating each digi-tal word in the n-bit binary digital code with its corresponding digital word in the (n~m)-bit special pur-pose digital code. The n-bit binary word may be used as an address to access the memory location containing the (n+m)-bit special purpose digital word.
The converters 18 and 3~, of FIGURES 1 and 2, respectively, are most practicably modified forms of known converters that include extra stages or cycles to handle the additional m-bits of the special purpose digi-tal code. FIGURES 4, 5, 6, 7 and 9 show D/A converters suitable for use as converter 38 of FIGURE 2. FIGURES
10, 11, 12, 13, 14 and 15 show A/D converters that are suitable for use as conVerter 18 of FIGURE 1. Each of the converters inthe enu~erated fi~ures will presently be dis-cussed in detail.

~641~1 III. D/A CONVERTERS
A. Parallel D/~ Converters FTGURES 4, 5~ 6 and 7 are all variants of paral-lel~ D/A converters suitable for use with the present in-vention. Prior to a detailed description of each of these figures~ a brief overview of the principles of a general~type, parallel D~A converter will first be dis-cussed with reference to ~GURE 3, FIGURE 3 is a schematic diagram of a general form of a parallel D/A converter. Wlthin this classifi-cation are several converter types, including; weighted-resistor-D/A converter; resistor-ladder D/A converter;
weighted~voltage D/A converter; and inverted ladder D/A
converter. The generic representation of these conver-ters,illustrated in FIGURE 3, is briefly described as follows:
The conVerter comprises a plurality of stages equal in num~er to the number of bits in the digital in-put word IN. Each stage has assocated with it an analog switch, S(l~, S(2), S(3),...S(N) o the single pole-single throw type. Each of the switches S has a control terminal 54 that receives the input bit value for its respective bit position. If the bit value IN (i) appearing on line 5~(i) is high, i.e. a binary one, then the switch S(i) couples a reference voltage V on line 56(i) to line 58(i) that is connected to a resistor network 60. When the bit value is low, i.e. a binary zero, the switch S(i) de-couples the lines 56 and 58.
The resistor network 60 can assume any one of various forms, as will hereinafter be made apparent in the discussion of FIGURES 6 and 7~ The network 60 is internally divided into a plurality of stages likewise equal in number to the number of bits in the digital input word IN. Each stage tra~nslates the signal which may be received cn associated line 58 into a current that is output on associated line ~. The current from each i~641~1 stage ls scaled in accordance with the wei~ht of the bit position of that st~ge, i~e. the order of the bit determines the ma~nitude of current appearin~ on associated line 62. In the case of a binary digital converter, each stage is weighted with respect to an adjacent stage by a factor of two. In this relation-ship, the highest order stage has a current magnitude of I/2, the second highest stage has a current magnitude of I~, and the nth stage has a current magnitude of I/2n. As used herein, the "weight" of a bit position is intended to mean its equivalent analog Yalue.
The currents on all of the output lines 62 are combined at node 64 and supplied to an amplifier 66.
The amplifier 66 outputs an amplified analog signal on line 68 that represents the sum of the currents from each stage, and is the analog equivalent of the digital input signal IN.
FIGURE 4 is a D/A converter of the type illustra-ted in FIGURE 3 that has been modified according to the present invention. The D/A converter is divided into a plurality of stages equal in number to the number of bits in the digital input word IN. Now, however, the digital input word will be in the (n+m)-bit special purpose digi-tal code, as was indicated by cable 36 of FIGURE 2.
Each of the n+m stages has associated with it a switch, S(l), S(2), S(3),...StN,O),...S(N,M). Each of the switches S(i) is a single pole-single throw analog switch having a control terminal 74(i). The signal appearing on control terminal 74(i) is the value of the bit for the ith bit position. If the bit value is high, i.e.
a digital one, the switch S(i) couples a reference voltage V on terminal 76ci) to output term~nal 78(i). If the bit value is low, i~e. a binary zero, the switch decouples line 76Ci~ from line 78(i).
~ resistor network 80 receives its input from each of the lines 78 associated with the switches S. The resistor network 80 is internally divided into a plurality ~ ~4101 of n+m stages. Each stage of the resistor network 80 translates the signal on line 78 into a current scaled in accordance with the bit position of the stage. The scaled currents could be chosen in several ways. As labeled in Figure 5, the highest order stage will produce a current on line 82(l) of I/2,the next highest orderstage will produce a signal on line 82t2) of I/4, etc. In the illustrated embodiment, the ith stage of the first n sta-ges produces a current having a value of I/21.
The final m stages, however, do not ~ollow the binary relationship between the first n stages. In the disclosed embodiment, the low order m stages are chosen to be repetiti~e in weight of the nth stage. The nth stage is nominally the lowest order bit of the n-bit digital word in which the (n+m)-bit digital word was originally encoded. Stated otherwise, the resistor network 80 includes m repetiti~e stages of the lowest order bit. The current carried by each of the output lines 82 (n,0) through 82 (n,m) is equal to I/2 . By the use of repetitive low order bits, the tolerances on the components used in each of the n+m stages can be relaxed beyond the tolerance levels nor-mally allowed for a converter with n-bit accuracy.
All of the currents on lines 82 are summed at node 84 and provided to an amplifier 86 for amplification into an analog output signal on line 88 which is the analog equivalent of the original n-bit binary digital signal.
As stated previously, the scaled currents could be chosen in alternate ways. For example, the current pro-duced in line 82 (i), when the corresponding digital bit value is high, could alternately be I/Kl for i from one to n+m. K can be any scale factor less than two, but greater than onej such that Km+n is greater than or equal to 2n.
By the use of a K value less than 2, the tolerances on the components are relaxed proportional to the difference from 2.
FIGURE 5 illustra~es a second, alternative paral-lel D/A converter suitable for use with the present inven-tion. Again~ this D/A converter has a plurality of n~m ~i6~01 stages which is e~ual to the number of bits in the digi-tal input word IN, as ~as indicated by cable 36 of EIGUR~ 2.
Each of the plurality of stages has associated with it a single pole-single throw analog switch S(l),S(2), S(3), etc. Each switch S(i~ has a control line 94(i) that receives the bit value for that bit position in the digital input word. If the bit at the ith position is high, i.e.
a binary one, the switch S~i) couples a reference voltage on line 96(i) to an output terminal 98(i). If the ith bit value is low, i.e. a binary zero, the switch S(i) decouples line 96(i) from line 98(i).
A resistor network 100 receives as input the signals on lines 98. The resistor network 100 is internally divided into a plurality of n+m stages. Each internal stage of the network 100 is weighted in relation to its position, and will produce a scaled output current on line 102 when the input signal on its associated line 98 is high.
With the normal binary relationship between stages, the current appearing on the ith line lO~ would be greater than the current appearing on the i+lth line 102(i+1) by a factor of two.
However, in the present D/A converter, selected ones of the low order bits are repeated through m stages.
Specifically, the n-2th bit is repeated once, the n-lth bit is repeated two or more times; and the nth bit is re-peated once. The use of repetitive low order bits will cause currents of repetitive weight to flow in lines 102.
The currents in lines 102 are summed at node 104 and provided as signal input to an amplifier 106. The amplifier 106 outputs a signal on line 108 which is the analog equivalent of the original n-bit digital word.
FIGURE 5 is a parallel D/A converter in accordance with the present invention that employs a weighted-resistor network as the resistor network 90 of FIGURE 4. The D/A converter is divided into a plurality of n~m stages. Each stage has associated with it a single 1~6D~

pole-double throw analog switch s. Each of the s~litches s has a control terminal 114 that receives the bit value for the bit position of that switch. In the present embodiment, each switch S also has a ground terminal 118 that is joined in common with the ground terminal of every other switch and held at ~ero potential. When the bit value appearing on control terminal 114 is high, the switch couples a reference voltage Y on line 116 to out-put line 120. When the bit value on control terminal 114 is low, the switch S couples the ground potential on line 11~ to line 120.
Each stage of the resistor network comprises a resistance 122 having an ohmic value weighted in relation to its position in the network. When the signal on line 120(i) is high, the resistance 122(i) will produce a current scaled in proportion to the significance of the ith bit position. The highest order stage has a resistance 122(1) with an ohmic value of R and produces a current of I/2. The next highest stage has a resistance 122(2) of

2~ and produces a current o~ I~4. In the present embodi-ment, this pattern holds for the first n stages, i.e. the ith stage has a resistance 122(i) equal to 2(i l)R, and produces a current equal to I/2 .
In the illustrated converter of FIGURE 6 the number m is chosen equal to 2, and the last two stages are chosen to be repetitive in weight with the nth stage,which nominally represents the lowest order bit in the n-bit binary digital code. Each of the two repetitive stages has a resistance 122(n,1) and 122 (n,2) equal in ohmic value to 30 the resistance 122(n,0) of the nth stage, i.e. 2(n l)R.
The current on lines 124 (n,l) and 124 (n,2) will, there--fore, he equal in magnitude to the current on line 124(n,0).
- The currents carried by all of the lines 124 are summed at node 126. The summed currents are received by amplifier 128 which prcduces an analog output signal on line 130 that is the analog equivalent of the ~64~01 original n~bit binary digital signal~ The ampli~ier 128 has a ~eedback resistor 132 to stabilize its output.
EIGURE 7 is another form of parallel D/A con-verter modified in accordance with the present invention;
specifically, a resistor~ladder D~A converter. The D/A
con~erter is div~ded înto a plurality of n+m stages.
Each of the stages includes a single pole~double throw analog switch, S, Each switch S has a control terminal 140 that receives the bit value for that bit position.
Eac~ sw~tch ~ also has a ground terminal 146 that is connected ~n common w~th the ground terminals of the other sw~tches and held at zero potential, If the bit value appearing on control terminal 140(i) is high, the switch S(il couples a reference voltage V on terminal 144(i) to an output terminal 148Ci)~ If the bit value appearing on control terminal 140(i) is low, the switch S(i) couples the ground potential on line 146(i) to terminal 148(i)~
The voltage appearing on each line 148 is 2Q applied across a reslstor 150 having a nominal resistance value of 2R. Each of the adjacent resistors 150 are normally interconnected by a reslstor 152 having a nominal resistance of R. However, an exception is made for re-petitively scaled stages. In the disclosed embodiment, the stage corresponding to the lowest order bit, i.e.
the nth bit position, is repeated once. The resistors 150 for each of the repetitive stages are directly coupled together without an interposed resistor 152.
A resistor 156 having a nominal value of 2R is 3Q connected between the resistor 150 of the rightmost or highest order stage and the input 160 of an amplifier 158.
The analog signal appearing on the amplifier output 162 is the analog e~uivalent ~f the orlginal n-bit binary digital signal that was to be converted, A feedback resistor 164 IS lnterconnected between the amplifier output 1~641~

line 162 and the amp]ifier input 160 to stabilize the amplifier 158.
The principles of operation of a resistor-ladder D/A converter are generally known. In brief, the current through each of the resistors 152(i) is branched off in ~qual parts at the co~mon node with resistors 150 and 152(i~1). The contribution of each stage is measured by the amount of current attributable to it that flows into resistor 156. As each stage becomes more distant or remote from resistor 156, its contribution is re-duced by a power of two. This principle is generally well-known in relation to a resistor-ladder network, and can easily be derived from Kirchoff's current law.
However, the repetitive stage associated with switch S(N,1) is scaled equally with the stage associated with switch StN,0) which is the next stage nearer to resis-tor 156. Because there is no resistor 152 connecting the resistors 150 of these stages, the current from both of these stages experiences an equal number of divisions be-fore reaching resistor 156. Accordingly, the two left-most stages associated with switches StN,l) and StN,0) are equally scaled.
The resistor-ladder D/A converter of FIGURE 7 is merely exemplary of a number of possible embodiments that are suitable for use with the present invention. For ex-ample, any two adjacent stages can be repetitively scaled by directly connecting resistors ]50 of each of the respect-ive stages, and removing the interposed resistor 152.
The resistance values must also be computed to give the proper currents into resistor 156; the resistor values needed will no longer be only R and 2R.
B. ~erial D/A Converters.
FIGURE 8 is a schematic diagram of a general form of serial D/A converter. FIGURE 9 is a schematic representation of a serial D/A converter modified from the embodiment of ~IGURE 8 according to ~41~1 the present invention, It is helpful to obtain an understanding of the principles of operation of a general serial D/A converter as a basis for understand-ing how it may be modified for use with the present invention~ Therefore~ a brief description of the serial ~f~ converter of FIGURE 8 will be given prior to a detailed description of the modified D/A conver-ter of FIGMRE 9, Referring to FIGURE 8, the serial D/A conver-ter includes a first switch S(l~. The switch S(1) isa single pole~single throw analog switch having a control termlnal 172~. The control terminal 172 recei~es each bit of a digital inPut word in serial order, least significant bit ~irst, The receipt of each bit is syn chronized with the occurence of a clock pulse 0. The timing pulse 0 is represented on the first line of the timing diagram of FIGURE 18~ If the bit value appear-ing on cont~ol terminal 172 is high, the switch S(l) couples a reference voltage V on l.ine 174 to output line 176. If the bit value appearing on control terminal 172 is low, the switch S(l) decouples line 174 from line 176.
A summing amplifier 178 receives as a first input the signal on line 176, and as a second input a feedback signal on line 180. The summing amplifier produces an output signal on line 182 that is the ampli-fied sum of the input signals appearing on lines 180 and 176.
The amplified difference signal on line 182 is received by a scaling amplifier 184 that produces an output signal on line 186 that is one-half of the magni-tude of the input signal on line 182, The signal on line 186 is rece~ed by another switch S(3~. Switch S(~) is a sin~le pole-double throw switch ha~ing a control terminal 200~ The control terminal 200 has applied to it the per~odic timing signal ~, As can be seen in the timing diagram of FIGURE 18, ~ is high ~ ~4~01 for one-half of the timing period and low for the other half. When ~ is high, the switch S(3) couples line 202 to an output line 186. This applies the signal on line 186 to an analog storage device 204, typically a capaci-tance The analog storage device 204 is coupled to ground through a line 206. During the second half of the timing period, the switch S(3) decouples lines 186 and 202, and couples lines 202 and 208. During this interval, the sig-nal stored in the analog storage device 204 is applied by 10 way of line 210 as the feedback signal to input 180 of the summing amplifier 178. In addition, this signal is pro-vided as an output signal on terminal 212.
The conversion of the serial digital input word into an equivalent analog signal is accomplished through a plurality of cycles equal in number to the number of bits in the digital input word. Specifically, if there are n bits in the digital input word, then the equivalent analog signal appears as the output signal on terminal 212 after n timing periods.
The simplest modified form of serial D/A conver-ter is the same as FIGURE 8 with one exception: Scaling amplifier 184 produces an output 186 which is greater than one-hal~ of its input 182, but less than its input~ The serial input 172 now includes n+m bits, and the analog out-put 212 appears after n+m t ~ ng periods. If the scaling amplifier gain is l/K, then K must be large enough so that Km n is greater than or equal to 2n.
FIGURE 9 illustrates a modified serial D/A con-verter for use with the present invention. The modified D/A converter incorporates the entire circuitry of the serial D/A converter of FIGURE 8, plus certain additional components that provide for a digital input signal having m repetitively weighted extra bits.
The modified,serial D/A converter includes a switch S(l). The switch S(l) is a single pole-single throw switch having a control terminal 172. The control terminal receives the serially-ordered bits of the ~16~

digital input word. In the present case, it is assumed that the digital input word has n~m bits, as was indicated by the cable 36 of FIGURE ~. If the bit value on line 172 is high, the switch S(l) will couple a reference voltage on line 174 to line 176. If the bit value on line 172 is low, the switch S(l) will decouple lines 174 and 176.
A summing amplifier 178 has as a first input the signal on line 176, and as a second input signal a feedback signal on line 180. The summing aplifier 178 produces an output signal on line 182 that is the amplified sum of the signals on lines 180 and 176.
Line 182 branches off into two parallel signal paths 182a and b. A first scaling amplifier 184 receives the signal on line 182a. The output of the amplifier 184 appears on line 186 as one-half of the amplitude of the signal on line 182a.
A second scaling amplifier 188 receives the signal on line or signal path 182b. In the illustrated embodiment, the second scaling amplifier 188 has a gain of unity, and the output signal appearing on line 190 is equal to the input signal on line 182b. In the practical embodiment of the invention, where the scale factor of the second scaling amplifier 188 is unity, the amplifier can be deleted in favor of a direct connection between lines 182b and 190. In fact, the selection of a scale factor of unity for the second scaling amplifier 188 is synonymous with such a direct connection.
A second switch S(2) receives the signals on lines 186 and 182. The switch S(2) is a single pole-double throw analog switch having a contxol terminal 192. The sig-nal appearing on the control terminal 192 is governed by the output of a NOR gate 194. The NOR gate 194 has a plurality of input terminals equal in number to the m extra bits. Each of the NOR gate input terminals is coupled to a timing signa~T, that goes high during the clock period associated with the corresponding repetitive bit. The timing diagram of FIGURE 18 illustrates schematically the 1~64~

t~n~signal T for each o~ the n+m bits of the digital input word.
I$ a,n~ one ~f the input si~nals T applied to the NOR gate 194 is hlgh, then the output signal of the NOR ~ate on the control ter~inal 192 is low, A low con-trol signal will cause the single pole-double throw switch S(2) to couple lines 190 and 196~
If none of the ~Pput signals T to the NOR
gate 194 are high, then the output signal of the NOR
gate on control terminal 192 will be highl A high con-trol signal ~i,11 cause the double pole-single throw switch S(2) to couple lines 186 and 196. The coupling of lines 186 and 196 was t~e normal relatton in the unmodif~ied serial D/A converter of FIGURE 8, A third switch S(,3~ receives the output signa].
on line 196 from the second switch S(2). The switch S(3) is a single pole-double throw analog switch having a control terminal 200, The control terminal 200 re-ceives the periodic timing signal ~. During the first half of each clock period when 0 is high, the switch S(3) couples lines 196 and 202, This coupling provides a path for the signal on line 196 to an analog storage device 204, typically a capacitance. The storage device 204 has a terminal 206 connected to ground.
During the second half of the clock or periodic timing signal 0, the switch S(3) decouples lines 196 and 202, and couples lines 202 and 208. The line 208 branches into a first line 210 that carries the signal value stored in the storage device 204 back to the in-put I80 of the summing amplifier 178 as the feedback signal. A second branch 212 represents an analog output signal terminal.
The modified, serial D~A converter converts the (n+m)~bit digital input word into the equivalent analog signal after n+m iterative cycles through the con-verter. That is, the analog output slgnal appearing on 1~6~

terminal 212 after the n+~th clock period is the analog equivalent of the ori~inal n bit binar~ digital input signal~
The modified, serial D/A converter of FIGU~E
9 is generic to a class of modified serial D/A converters r More spec~ically, the 'converter of FIGURE 9 is proyided as a generic model of an~ one or more of the following specific, serial D/A con~erter types modi~ied in accordance with the present lnvention; Shannon-Rack decoder; sample-hold D/~ converter; cyclic-D/A conver~
ter; and charge-equalIzing D/A converter, Each of these latter-recited specific converter types is des-cribed in its umodified ~orm inthe first of the earlier-referenced Schmid articles~
IV. A/D CONVERTERS
A. Parallel A/D Converters.
Referring again to E'IGURE 1 r the block-diagram representation of an A/D converter system incorporating the present invention includes an analog to special pur-pose digital converter 18. There are a plurality of known converter types that may be modified in accordance with the present invention to function as the analog to special purpose digital converter 18. More specifi-cally, the A/D converter types illustrated in FIGURES 10, 11, 12, 14 and 15 are all forms of known A/D converter types that have been modified for use with the present invention. Each of the converter types shown in these figures will be described presently.
FIGURE 10 is a schematic diagram of a general, parallel feedback A/D converter modified according to ~0 the present invention. The A/D converter includes a summing circuit 222 that has a first input 224 receiving an analog input voltage VA, and a second input line 226 that carries the feedback voltage VF~which is ofopposite polarity to the analog ~oltage VA~ The summing circuit 222 produces an error or dif~erence signal VE on line 228 that, represents the difference between the analog ~L~6a~0~

input and feedb~ck voltages ~ threshold circuit 230 receives the differ-ence signal VE on line 228. The function o~ the threshold circuit 220 is to produce an up or down count pulse, ~ or ~E, respectively, depending on the polarity of the difference signal VE. The threshold circuit has control input lines 232 and 234 that are held at upper and lower threshold voltages, +VTH and -~T~' respectively. The absolute value of the ~hreshold voltages is selected as a function of the magnitude of the least significant bit in the (n+m)-bit digital output word. If the differ-ence voltage ~E is more positive than the positive thresh-old voltage +VTH, the threshold circuit 230 outputs a count-up pulse +E on line 36. If the difference voltage VE is more negative than the negative threshold voltage, the threshold circuit 230 outputs a count-down signal -E on line 238.
A logic and storage circuit 240 receives as inpu~ the up and down count signals, +E and -E
respectively. The function of the logic and storage circuit 240 is to count up or down, in response to the signals on lines 236 and 238, through an (n+m)-bit digital word. The logic and storage circuit sets one bit position for each count pulse received on either lines 236 or line 238. The output of the logic and storage circuit 240 is an (n+m)-bit digital word carried on lines 242(1), (2), ...tn)...(n+m).
~ parallel D/A converter 244 receives as in-put the (n+m)-bit digital word appearing on lines 242.
The parallel D/A converter 244 may, for example, be any of the types of parallel D/A converter earlier described herein. The converter 244 has n+m conversion stages corresponding to the bits on lines 242. A reference ~oltage _VR of negative polarity is received on line ~6~

246 by the converter 244. The output signal of the con-vPrter 244 appears on line 226 as the feedback voltage VF. In practical effect, the feedback voltage VF is the negative analog equivalent of the (n+m)-bit digital word appearing on line 242. The comparison of the ana-log input signal VA with the feedback signal VF deter-mines whether the digital word on lines 242 is less than, greater than, or equa] to the analog i~put signal VA- The (n+m)-bit digital word appearing on line 242 after2~tm)cycles or some lesser number of iterations of the converter will define the digital output word in the special purpose code, as was shown by cable 20 of FIGURE 1.
FIGURE 11 illustrates a servo-AJD converter, that is modified in accordance with the present inven-tion. The servo-A/D converter is a species of the general parallel feedback A/D converter of FIGURE 10.
The servo-A/D converter is logically divided into three distinct stages: a summing and threshold 20 stage 252, an up/down counting stage 254, and a D/A
conversion stage 256. Each of these stages will be indi-vidually discussed as follows.
The general function of the summation and threshold stage 252 is to perform a comparison of a feedback signal from the D/A conversion stage 256 with an analog input voltage VA, and produce an up or down count signal depending upon whether the comparison shows the feedback signal to be less than or greater than the analog input signal, respectivel~.
The summing and threshold stage 252 includes a high-gain DC amplifier 258. The amplifier 258 receives as input the current flowing into it from node 260. The input current is the difference between a ~164101 first current component IA caused by the analog input signal VA applied across a resistor 262, and a second current component IF that flows in line 318 as the out-put from the D/A conversion stage 256. I'he difference between the currents IA and IF is reflected as an amplified error or difference voltage VE appearing on output line 264.
The upper and lower bounds of the error or difference voltage VE are defined by a pair of respective upper and lower feedback paths 266 and 270. The upper feedback path 266 includes a pair of serially-connected diodes 268a and b. The anode of diode 268a is connec-ted to node 260, and the cathode of diode 268b is co~mected to output line 264 to limit the difference voltage VE to values smaller than approximately 1.2 volt. Similarly, the lower feedback path 270 includes a pair of serially-connected diodes 272a and b. The diode 272a has its cathode connected to the node 260, and the diode 272b has its anode connected to output line 264, to limit VE to values more positive than approximately -1.2 volt.
The difference voltage V~ is first applied through a resistor 278 to the emitter of an NPN transis-tor 276. The base of the transistor 276 is grounded, and the collector is energized through a resistor 282 by a reference voltage VDc.
The difference voltage VE is also applied to the base of another NPN transistor 290 through a resistor 286. The emitter of the transistor 290 is held at ground potential, and the collector is ener-gized by the reference voltage VDc through a resistor 296.
When the difference voltage VE is within a ~641~

deadband centered at 0 valts ~w~th. a rad~us of approxi~
mately 0,6 volt~ neither of the transisto~s 276 and 290 become conduct~ve, ~owever, when the difference signal V~ is negative and outside the range of the deadband, the base~emitter ~oltage o~ the transistor 276 becomes great enough to.cause that transistor to become con-ductive. This ~ndIcates a negative error and causes a count up si~nal +E to appear on line 284. In the complementary situation~ where the difference voltage 10. VE is outside of the deadband and positive, the base-emitter voltage of the transistor 290 will become suffi-ciently great to cause that transistor to become con~
ductive, This indicates a positive error condition, and causes a countdown signal -E to appear on line 298, The up/down counting stage 254 compr.ises an (n~m)-bit up/down counter 300. The counter 300 receives as input the count signals on lines 284 and 298 and a clock or periodic timing signal 0 on line 302. The counter 300 will count up or down once for each clock signal depending upon the occurrence of one or the other of the count signals +E or -E on lines 284 and 298, respectively. The output signal of the counter 300 is an (n+m)-bit digital word carried on lines 304(1), ~2),...(n),~ n+m), The D/A conversion stage 256 performs a digital-to-analoaconversion of the tn+m)-bit digital word carried on lines 304. .The D/A converter stage 256 includes a switchi.ng circuit 306 having n+m analog switches, and a cooperative resistor network 314 having n+m conversion stages, The switching network 306 receives as input the (n+ml-bit digital ~Jord on line 304, An inverted reference voltage VR is applied on line 308 to each of the n+m analog switches. A ground terminal 310 is like-wise coupled to another terminal of each of the n+m _~..29 -~ 16~

analog switches, Each of the analog switches is pre-~erably a sin~le pole-double thro~ switch that couples -VR to its associated output line 312 when the bit value on the correspondin~ input line 304 is high, and couples the ~round terminal 310 to its associa-ted output line 312 when the bit value on its correspond-ing input line 304 is low, Accordingly, the output of the switching circuit 306 on line 312 will have the reference voltage -VR on each line 312 where a binary one or high si~nal appeared on the corresponding input line 304, and the ground potential on each line 312-where a ~inary zero or low sgnal appeared on the corresponding input line 304.
The (n+m~-bit resistor network 314 has each of its stages receiving the output signal of the corres-ponding stage in the switching circuit 306. The resistor network 314 may, for example, be a resistor-ladder network as was illustrated in FIGURE 7 and described in connection therewith.
A ground terminal 316 provides a ground connec-tion for the resistor network 314. The output of the resistor network 314 is a feedback current IF that flows on line 318 to node 260, as was hereinbefore described.
The feedback current IF is the analog current equivalent to the (n+m)-bit digital word appearing on lines 304.
The output signal of the servo-A/D converter 250 is the (n+m)-bit digital word appearing on lines 304 where there is no signal on +E or -E, or at the latest by the 2(n~m) clock si~nal. This (n+m)-bit digital word corresponds to the signal carried on cable 20 of FIGURE 1.
FIGURE 12 is a successi~e-approximation A/D
con~erter that represents another species of the general, D~A conyerter of FIGURE 10. The successive-approximation A~D converter has been modifi~d from its conventional 4~1 form for use in accordance with the present invention and is described in detail as follows~
The successive~approximation A/D converter includes an amplifier 322 that produces an output sig-nal at node 328 that repxesents the amplified sum of the currents ~lowing into input node 324, One current component flowing into the node is the analog input current IA that is caused by the application of the analog input voltage VA to the input terminal of resis~
lQ tor 326. The other current component is a feedback current IF that flows on line 334~ The polarity of the feedback current IF is opposite that of the analog input current IA, and therefore the current flowing from node 324 into the amplifier 322 is the difference in the magnitude between these two currents.
The amplifier 322 has a feedback path 330 including a zener di.ode 332 whose purpose is to limit the output voltage swings of the amplifier between a range of -0.6 volt and ~3.0 v~lts, whereby a level of -0.~ voit indicates that the absolute value of the analog input current IA is larger than the feedback current IF and the level of +3,0 volts indicates that the absolute value of the analog input current IA is smaller than t~e feedback current IF. There is no in-formation indicating when the currents are equal in maqnitude, as this information is not necessary for con-verter operation.
The output signal of the amplifier 322 is applied directly to one input of a NAND gate 336~
The other input signal on line 348 to the NAND gate 336 is the time derivative of the inverse of the clock signal 0. This signal is developed by applying the inverse o~ the clock signal on line 340 to a dififerentiator 344. The output of the differentiator is directly coupled to the N~ND gate 336 by line 348.

4~1 An~the~ N~ND gate 338 h~as a single input and functions a$ an ~nyerte~ for the time derivative of the clock si~nal ~ Specifica~ly~ the clock signal 0 is applied by line 342 to another di~ferentiator 346.
The output of the differentiator 346 is applied directly by line 350 to the NAND gate 338.
The clock siqnal 0 is also applied as input to an N+M~2 stage timing generator 352 The timing genera-tor 352 produces a set of at least n~m~2 timing signals Tl~ T2~ Tn~m~- ,Tn~m+2. The timing generator 352 can be implemented as an (n~2~-bit ring counter with n+m+2 flip~flops interconnected as a shift register and with additional logic to set the first stage to one when all other stages are zero. Such a ring counter can be built very economically with a serial-IN,parallel-OUT shift register.
A set of n+m bistable latches 370(1), 370(2), 37C(n+m) correspond to the n+m bits of the d~gital out-put word of the converter~ Each of the bistable latches 370 is identical to the other latches, and a description of latch 370(1) is provided as representative of all the latches.
The blstable latch 370(1), which is the highest order latch, has a set input S and reset input R. The latch 370(1~ is set, i.e. its output signal ~ecomes ~.igh, when the signal applied to one of its set terminals is low, and the latch is reset, i.e. its output signal be-comes low, when the signal applied to one of its reset terminals is low. The latch 370(1) receives input signals on lines 366 and 368 that are a function of the set of n-~m ti~ing si~nals T, the clock si~nal ~ and the dif~erence sl~nal from the amplifier 322. More specifi~
cally, the output si~nal from the N~ND gate 336 on line 347 is applied on line 362 as one input to a NAND.
gate 356, The other tnput signal on line 364 is the timing signal corresponding to this latch, in this ~64~

i,nstance Tl. The same timin~ si~nal is likewise applied as an input s1,gnal on line 360 to another NAND gate 354.
The other input si~nal to N~ND gate 354 is the inverse of the de~iyative o~ the clock si~nal'~. This signal is carried on line 358 which is connected to the out-put line 34~ o NAND ~ate 338~
The output condition of the latch 370(1), i.e.
the signal appearing on line 372(1), will undergo the following transition during timing period Tl. The latch is initially set by applying a low signal to line 366 This is accomplished hy qating the timing signal Tl and the inverse of the derivative of t~e clock signal 0 through the NAND gate 354. The latch 370(1) will remain set i~ the amplifier output signal at node 328 is low ~or this timing period, indicating that the bit position represented by this latch is needed to approximate the analog input signal VA. On the other hand, the latch will be reset if the amplifier output signal at node 328 is high, indicating that the bit position represented bythis latch is not needed to approximate the analog input signal. To reset the latch when needed, the amplifier output signal appearing at node 328 and the derivative of the inverse of the clock signal on line 348 are applied to NAND gate 336. The output signal of the NAND
gate 336 appearing on line 362 and the timing signal Tl are applied to NAND gate 356, If the amplifier output signal at node 328 is low, then latch 370(1) will not be reset. However, if the signal at node 328 is high, then the latch will be reset.
This basic process is repeated n+m times, onoe for each of the latches.
An (n+m)~bit parallel D/A converter 380 re-ceiVes as input the signals on lines 372~,1), 372(,2)~
372,(n+m2. The functi~on of the D/~ converter 3g0 is t,o convert its (n+m~,-bit digital input word into a ~16~

corresponding feedback current IF on line 334. The D/A
converter 380 may be any one of the several types of such converters hereinbefore described. Each of the n+m stages of the D/A converter 380 is energized by a ne~ative reference voltage VR on line 382. Each of the stages is likewise connected to ground by line 384.
The (n+m)~bit digital output word of the converter in the special purpose code appears on lines 372 after the n+mth timing period. An output gating circuit 374 re-ceives as input the signals on lines 372. The circuit 374 has a control terminal that receives the timing signal Tn+m+l. The output gating circuit 374, upon receipt of the timing signal Tn+m+l, will output the (n~m)-bit digital word in the special purpose code. The converter can be re-set for a subsequent A/D conversion by resetting all of the latches 370. Accordingly, the inverse of the timing signal Tn~m+2 is applied to the reset terminals R of thè latches 370 to reset them for a subsequent conversion.
B. Serial A/D Converters.
Another general form of A/D converter that can be modified in accordance with the present invention to serve as the analog-to-special purpose digital converter 18 of the A/D conversion system of FIGURE 1 is the serial A/D
converter. FIGURE 13 is a general, schematic model of the known forms of serial A/D converter. FIGUXE 14 is the general converter of FIGURE 13 modified for use with the present invention. A brief description of the general, serial A/D converter of FIGURE 13 is helpful as a basis for understanding the modified, serial A/D converter of FIGURE 14.
Witp re~erence to FIGURE 13, a serial-feedback A/D converter converts an analog input signal VA on line 392 into an equivalent n-bit binary digital word in the form of a series of digital bits a~pearing on out-put terminal 424. The serial-feedback A/D converter 6~

39Q includes a ~ S~t switch S(.l) The switch S(l) is a s~n~l.e pole~.double thro~ switch with a control terminal 396 that receives the initial timing pulse Tl, The time pulses Tl, T2~..Tn can be developed from a rin~ counter 456 as a function of a clock signal ~ .
When ~e ti~ing signal Tl is high~ the switch S(l) connects line 392, which carries the analog input voltage V-A, with lin.e 398, When the timing signal Tl lO. is low, i e. at all other times than the initial timing period, switch S(l~ connects line 394, which carries a feedback signal, with line 398, A summin~ amplifier 400 receives as a first input the signal on line 398~ The summing amplifier 400 has a second input from line 402 which is developed as the negative of the output signal of another switch S(2). The switch S(2) is a single pole-double throw analog switch having a control terminal 410 that carries a digital feedback signal. When the signal on control terminal 410 is high, line 406, which carries a refer-ence voltage V, is connected to output line 412. When the feedback signal on control termlnal 410 is low, the switch S(2) connects line 408, which is held at ground potential, to the output line 412. The signal on line 412 is applied to an amplifier 404 with a scale factor of negative one. The output signal from the amplifier 404 appears on line 402 as the negative of the signal on line 412.
The summing amplifier 400 produces a signal on line 414 that is the summation of the input signals on lines 398 and 402, In an alternative embodi-ment of the invention, th.e summing amplifier 4Q0 and amplifier 404 could be replaced with a comparator or similar~t~pe device that would produce a difference si~nal representing the difference between the signals on line 39~ and line 412, ~641~1 A comparator 418 has a fir~t input terminal 416 that carries the difference signal as it branches off fr~m line 414, The comparator 418 has a second, negative input terminal 420 that has applied to it one-half of the reference voltage V/2. When the magnitude of the signal on the first tnput terminal 416 equals or exceeds the magnitude of the signal on the second input terminal 420, the comparator 418 will produce a high digital signal on line 422, Conversely, when the magni-tude of the signal on the second input terminal 420 ex-ceeds the magnitude of the si~nal on the first input terminal 416, the comparator 418 will produce a low digital signal on line 422.
The digital signal appearing on line 422 is significant in two respects. First,it appears on out-put terminal 424 as the bit value for the corresponding clock period in the n-bit binary digital output word.
Secondly, the digital s.ignal on line 422 is applied on line 410 as the digital feedback signal to the switch S(2).
The difference signal that appears on line 414 as the output of the summing amplifier 400, is also applied on line 426 as the input signal to a scaling amplifier 428. Typically, the scale factor of the amplifier 428 will be two (2). Accordingly, the ampli-fier output signal appearing on line 430 has a magnitude twice that of the difference signal.
A switch S(4) receives as input the scaled amplified signal on line 430~ The switch S(.4) is a single pole-double throw analog switch having a control terminal 450. The control terminal 450 has applied to it the clock or periodic timing signal 0, When the clock signal ~ is hi~gh, the swi.tch S(4) connects line 430~
whi~ch carrieS the scaled difference signal to line 452, which is the input terminal to an analog storage device 454. The analog storage device is generally a capacitance

- 3~ -~64~1 , . .

and serves to store the sign~l carried on line 430.
When the clock signal 0 is low, the switch S(4) connects line 452 with line 394. This connection allows the analog storage device 454 to provide its stored signal information onto line 394 which provides the stored signal information to switch S(l) as the analog feed-back signal.
The operation of the serial-feedback A/D con-verter 390 can best be understood by means of a pro-10 cedural example. For purposes of analysis, it is assumedthat n equal 4tVA equals 13, V equals 16 and V~2 equals 8, that the scale ~actor of the summing amplifier 400 is unity. The procedural execution is described as follows.
During the initial ti~ning period when Tl is high, the analog input voltage VA will be applied by switch S(l) to line 398. Initially, the digital feed-back signal on line 410 will be low, and the signal ' value on line 412 and line 402 will be zero. Accordingly, the difference signal will have a value of 13 at the output of comparator 418. The value 13 on line 416 is greater than the value 8 on line 420, and, therefore, the comparator output signal on line 422 will be high.
The first bit in the n-bit digital output word will be high, and the feedback signal on line 410 will be high, The difference signal is also applied to the scaling amplifier 428. ~e output of the scaling alrg?lifier will have a value of 26, and likewise will the analog feedback signal on line 394.
During the second clock period, the signal on line 398 will have a value oi~ 26, and the signal on line 402 will have a value of -16. Accordingly,the difference signal on line 414 will be 10, The signal on line 416 will have a value of 10 and the signal on line 420 will have a value of 8, and, therefore, the second bit in the n-bit digital output word will be high, as ~16D,t~

will the digital feedback signal on line 410. The differ-ence signal will be scaled to a value of 20 by amplifier 428, and, therefore, the analog feedback signal on line 394 will be likewise valued.
During the third clock period, the signal on line 398 will have a value of 20, and the signal on line 402 will have a value of ~16. Accordingly, the difference signal will have a value of 4. The signal on line 416 will have a value of 4, and the signal on line 420 will have a value of 8 Accordingly, the signal on line 422 will be low, causing the third bit in the n-bit digital output word to be low, as well as the digital feedback signal on line 410. The difference signal will be scaled by amplifier 428 to a value of 8, and the analog feedback signal on line 394 will be likewise valued.
During the fourth clock period, the signal value on line 398 will be 8, and the signal value on ]ine 402 will be zero. Accordingly, the difference signal on line 414 will be 8. The signal value on line-416 will be 8, and the signal value on line 420 will be 8 and~ therefore the digital signal on line 422 will be high. This will result in the fourth bit of the n-bit digital output signal being high. This sequence of four cycles has produced the correct n-bit digital equivalent signal, viz. 1101 is equivalent to 13 in binary digital code.
The simplest modified form of serial A/D converter is the same as FIGURE 13 with one exception: scaling ampli-fier 428 has a scale factor K which is less than two, but more than one. The serial output 424 now includes m+n bits.
K must be large enough that Km n is greater than or equal to 2n.
FIGURE 14 illustrates a modified serial-feedback A/D converter. The A/D converter of FIGURE 14 incorpor-ates the entire A/D converter of FIGURE 13, and includes additional circuit elements to adapt it for use with the present invention. In view of the preceding detail des-cription of the ~/D converter of FIGURE 13, only those ~6~

added circuit elements that are pertinent to an under-standing of the present invention will be described in the A/D converter of FIGURE 14.
The difference signal which appears on line 414 as the output of the summing amplifier 400, is now branch-ed off onto an additional signal path or line 432. A
second scaling amplifier 434 recei~es as input the differ-ence signal on line 432 The scaling amplifier 434 in the illustrated embodiment has a scale factor of unity, however, it is possible to select other scale factors less than two (2). When a scale factor of unity is selec-ted, as in the present illustration, the second scaling amplifier 434 is synonymous with a direct connection of lines 432 and 436.
A switch S~3) is interposed between the outputs of the first and second scaling amplifiers 428 and 434 and the switch S(4). The switch S(3) is a single pole-double throw analog switch having a control terminal 438. The control terminal 438 receives the output of an OR gate 440 that has m input terminals. In the present embodiment, the m input terminals of the OR gate 440 have applied to them the timing signals Tn+l-Tn+m. The timing signals T can be developed from a rîng counter 456 as a function of the clock signal 0. During the clock or timing periods associated with the selected timing signals Tn+l-Tn+m, the output sig-nal of the OR gate 440 on line 438 will be high. At all other times the signal on line 438 will be low.
When the signal on control terminal 438 is low, the switch S(3) will connect line 430, which carries the 30 difference signal as scaled by amplifier 428, with line 442.
When the signal on control terminal 430 is high, the switch S(3) will connect line 436, which carries the difference signal as scaled by amplifier 434. The line 442 supplies the scaled difference signal to switch S(4) in the manner hereinbefore described.
The selection of specific ones of the timing signals T is determinative of which bit positions in ` . . 1~64~

the (n+m)-bit digital output woxd will be repetitive of adjacent bit positions, In the pxesent illustration, the selection of the final m timing signals as inputs to the OR gate 440 will cause the final m bits of the (n+m)-bit digital output word to be repetitive in weight with the nth bit. Other bits can be chosen to be repetitive as an input signal to the OR gate 440. Accordingly, the (n+m)-bit digital output word will be produced by the sequence of bit values appearing at terminal 424 of the A/D con-ve~ter after n~m clock periods, The serial-feedback A/D converter of FIGURE 13 is general to several known species of serial-feedback A/D
converters, Among such species of converters are the (1) single-amplifier circulation A/D converter; (2) dual-amplifier circulation A/D converter, and (3) charge equal-izing A/D converter, All of the latter three converter types are described in their unmodified forms in the second of the earlier-referenced Schmid articles.
C. Cascade A/D Converters.
FIGURE 15 is a cascade type A/D converter, modified for use with the pres~ent invention. The A/D
converter converts an analog input signal on line 464 into a corresponding (n+m)-bit digital output word in parallel form on lines 488, or in serial form on line 490.
The cascade-type A/D converter includes a sample hold circuit 462 that receives the analog input signal on line 464. The sample hold circuit 462 is controlled by the clock signal ~, and receives the clock signal on line 468 which connects to clock line 470.
The cascade-type A/D converter also includes a pl~rality of single bit A/D conversion stages denoted A/D(l), A/D(2~,...A/D(N)~...A/D(n+m). There is one single bit A/D conversion stage for each bit in the (n~m)-bit ~64~1 digital output word.
The terminal connections for each of the n+m stages can be exemplified by the description of the first conversion stage A/D(l). The first conversion stage receives a like enumerated analog input voltage Vl on line 476tl), which in this instance is equal to the analog input signal VA. A reference voltage VR/2 on line 472 is taken off by line 474(1) and applied to the conversion stage A/D(l). The bit value corresponding to the conversion stage is output on line 478(1).
Another output line 476(2) carries the analog input signal V2 to the next adjacent single-bit conversion stage.
In overview, the cascade-type A/D converter operates as follows. At the first single bit conversion stage A/D(l) the analog input signal Vl is compared against the reference signal VR/2 to determine if the first bit position is to be a binary 1 or 0. If the analog input signal Vl exceeds VR/2, it indicates that the bit value for this position is 1. Conversely, if VR/2 exceeds Vl, it indicates that the bit value for this position is 0. In a normal binary form of cascade-type A/D converter, if the bit value is 1, then the reference signal VR/2 is subtracted from the analog input signal and the difference is multiplied by two to provide the analog input signal for the next adjacent single bit conversion stage.
FIGURE 16 illustrates the internal construc-tion of a single bit conversion stage of FIGURE 15 that obeys the normal binary form. There are n single bit conversion stages of the type illustrated in FIGURE 16 in the cascade-type A/D converter of FIGURE 15.
More specifically, an exemplary single bit binary conversion stage A/D(i) is described as follows.
The analog input voltage Vl from the preceding single bit conversion stage is received on line 476(i). The ~64~

reference voltage VR/2 is received on line 474(i). A
comparator 496 has a positive input terminal 492 that receives the analog input voltage Vi, and a negative in-put terminal 494 that receives the reference voltage VR/2. The comparator 496 produces a digital output signal having a value depending upon the relative magnitudes of its input signals. Specifically, if the signal value on input terminal 492 exceeds the signal value on input terminal 494, the digital output of the comparator will be high and a binary one will appear on line 478(i). Conversely, if the signal value on in-put terminal 494 exceeds the signal value on input ter-minal 492, then the digital output of comparator 496 will be low and a binary 0 will appear on line 478(i~.
A single pole-single throw switch has a con-tact 498 controlled by the digital output of the com-parator 496. When the comparator output is high, the contact 498 couples line 500, which carries the refer-ence voltage VR/2, with line 502, which is the negative input terminal of a summing circuit 504. When the digi-tal output o~ the comparator 496 is low, the contact 498 remains open.
The summing circuit 504 also receives at its positive input the analog input voltage Vi on line 476(i).
The summing circuit 50~ outputs a signal on line 506 that is the difference between the signal values supplied to its positive and negative inputs.
~ scaling amplifier 508 receives the signal on line 506 and produces an output signal on line 476(i) that is twice the input signal. This signal then functions as the analog input signal Vi+1 for the adjacent single bit conversion stage A/D(i~l).
In accordance with the present invention, m single bit conversion stages may be modified slightly to produce bits that are repetitive in weight with the bits - ~2 ~

116a~

of at least one of the other n stages. In the cascade-type A/D converter of FIGURE 15, m is equal to 2, and the final two bits are chosen to be repetitive of the nth bit. The final two conversion stages A/D(N+l) and A/D(N+2) incorporate the modifiecl internal construction of FIGURE 17.
FIGURE 17 illustrates conversion stage A~D ~n+i) and is modified slightly from the conversion stage of FIGURE 16. More specifically, the scaling amplifier 508' has a different scaling factor. In this case, the different scale factor is unity, although other scale factors less than 2 are possible. In fact, the use of an amplifier 508' with a scale factor of unity is synonymous with a direct connection of lines 506 and 476(n+i+1).
Referring again to FIGURE 15, each of the single bit conversion stages performs the single bit conversion for its bit position during the first portion of the clock period. During the second portion of the clock period, the bit values appearing on the lines 478 are loaded into an N+2 bit intermediate storage buffer 486 through the closing of a plurality of switches.
More specifically, each single bit conversion stage has associated with it a single pole- single throw switch.
The contact 482 of the switch is controlled by the out-put signal from a clock inverter 480. The inverter 480 receives the clock signal 0 on line 470 and inverts it.
The output of inverter 480 is low during the first por-tion of the clock period when 0 is high, and high during the second portion of the clock period when 0 is low.
When the inverse of ~ is high, the switch contact 482 closes and connects each line 478 with a corresponding line 484. The closure of the switch causes the bit value on line 478 to be loaded into a corresponding stage of the N+2 bit intermediate storage buffer 486.
The (n+m)-bit digital output word in the special purpose code can be obtained in parallel form on lines 488, ~L~64~

or in serial form on line 490.
The above-described cascade-type A/D conver-ter is described in its unmodified form in the third of the earlier-referenced Schmid articles.
V. PROCESSOR IMPLEMENTED SYSTEMS
FIGURE 19 is a processor-implemented A/D con-version system patterned after the A/D conversion system of FIGURE 1. The A/D conversion system is controlled by a central processor unit (CPU) 5Z2 that may take the form of a commercially available micro-processor or mini-computer. Information is communicated between the CPU
522 and units under the control of the CPU through three busses: a control bus 524C; an address bus 524A; and a data bus 524B~ This is in accordance with usual computer system architecture.
The analog input signal that is to be conver-ted to binary digital form is received on line 528.
The signal is applied to an analog-to-digital converter 526 that may be any one of the types hereinbefore dis-cussed as suitable for use with the present invention~
The output signal of the A/D converter 526 is the (n+m)-bit digital word in the special purpose code. A
buffer unit 530 under the control of the CPU 522 pro-vides temporary storage for the (n+m)-bit digital word.
The (n+m)-bit digital word in the special purpose code is translated into the corresponding n-bit digital word in the binary digital code by means of a look~up table stored in a programmable read-only-memory (PROM) 532. The CPU 522 uses the (n+m)-bit digital word as an address for the corresponding n-bit word in binary digital code. Once the n-bit binary digital word is accessed, it is sent out by the CPU to an output port 534. The desired n-bit word in binary digital code appears on the output cable 536 of port 534.
One method of obtaining the binary digital code 1~64~

word is to store the difference between the (n+m)-bit code word corresponding to the n~bit word and the n-bit word. This difference is then subtracted from the (n-~m)-bit word to obtain the corresponding n-bit word.
Another method of obtaining the binary digital code word is to partition the memory PROM 532 into two separate look-up tables; one for each half of the (n+m)bit access word. Each half of the tn+m)-bit digital word is then used to access an n-bit digital word, which is the correct n-bit word if the other half of the (n+m)-bit digital word were all zero. These two n-bit digital words are ad-ded to obtain the correct n-bit word corresponding to the complete (n+m)-bit digital word. This affords a great sav-ings in memory space relative to a look-up table contain-ing all 2n m permutations of the n+m-bit word. Alternat-ely, each table entry may have an (n+p)-bit word, where p is one (1) or more; this will provide more accuracy in the translation. This method could be extended to any number of separate look-up tables, each accessed using part of the tn+m)-bit digital word. In the limit, there would be n+m tables, each with 2 entries; indeed, one entry in each table may always be zero and not actually stored. The correct n-bit word would be obtained by adding all n+m of the (n+p)-bit word obtained from the tables.
FIGURE 20 illustrates a processo~-implemented D/A
conversion system that is patterned after the D/A conver-ter system of FIGURE 2. The D/A converteY system converts an n-bit binary digital signal on cable 548 into an equiva-lent analog signal on line 556.
The D/A conversion system includes a central proces-sor unit (CPU) 542. Information is communicated between the CPU 542 and the ae~ices under its control by a group of busses: a control bus 544C; an adaress bus 544A; and a data bus 544~.
A buffer unit 546 receives the n-bit binary aigital signal on cable 548 and provides temporary storage for it.

- ~164~

The n-bit binary digital signal is translated into a CQrrespOn~ing (n+m)-bit digital word in a spècial pur-pose code by means of a look-up-table contained in a pro-grammable read-only-memory (PROM) 549. The n-bit binary digital word is used as an address for the corresponding tn+m)-bit binary digital word stored in the PROM 549.
The alternate methods associated with the previously dis-cussed (n+m)~bit to n-bit translation can be applied in analogous fashion to the presently discussed n-bit to (n+m)-bit conversion.
A digital-to-analog converter 550 which may be any one of the types hereinbefore discussed as useful with the present invention is under the control of the CPU 542.
The D/A converter 550 converts the (n+m)-bit digital word into the equivalent analog signal and outputs it on line 552.
An actua~or 554 receives the equivalent analog signal on line 552 and outputs an amplified or otherwise modified form of the analog signal on line 556 to an analog device.
VI. CALIBRATION METHODS
A number of methods have been developed for cali-brating an A~D converter modified in accordance with the present invention, to establish the relation between the special purpose code unique to each converter and the nor-mal binary digital code. Three of these methods are illus-trated in flowcharts of FIGURES 21l 22 and 23. A descrip-tion of each method is provided as follows.
FIGURE 21 illustrates a first method for calibrat-ing an A/D converter of the present invention. In step 558, a test analog signal is generated.
In step 566, an equivalent n-bit binary digital word is analytically determined for the known value of the test signal. Alternatively, a highly accurate n-bit A/D conver-ter can be used for the same purpose.
In step 568, the test analog signal is applied to an A/D converter modified for use with the present invention.

1~L641~1 The output of the converter is an (n~m)-bit digital word in the special purpose code uniquely associated with that converter.
In step 574, the n-bit word resulting from step 566 and the (n+m)-bit word resulting from step 568 are used as a table entry and a table address, respectively, to generate an entry in the look-up table for translating digital words.
In decision 576, a check is made whether all analog signals have been tried. If yes, the calibration is com-plete, and the YES path is followed to terminal 578. I~
not, the N0 path is followed back to step 558, where a new analog test signal having a closely-controlled value is generated. This new test signal is changed in magnitude from the preceding test signal by an amount equal to the value of the nth bit in the n-bit binary digital word. The cycle is then repeated a plurality of times until a com-plete set of analog signal values has been generated and the conversion from each possible (n+m)-bit word to the corresponding n-bit word has been established.
FIGURE 22 i5 a flowchart illustrating another n~ethod of calibrating an A/D converter of the type suitable for use with the present invention. In general, the approach is to adjust an analog signal applied to the converter until exactly one bit of the (n-~m)-bit digital output word is equal to one (1). The analog value giving rise to this output is then recorded and the bit position having the single binary one (1) is weighted in proportion to that analog value.
In step 580, a count variable designated BIT NO is set to one (1). The flow then enters an iterative loop at step 584. In step 584 an analog test signal is applied to the A/D converter. In step 588 the analog test signal is converted to the corresponding (n~m)-bit digital word in the special purpose code, using the converter being calibrated~

- 4~ -In decis.ion 592, the (n+m)-bit digital word is tes-ted to determine if all bit positions except the bit posi-tion represented hy BIT NO are equal to 0. If no, the NO
path is followed back to step 584 where the analog test signal is adjusted. If any bit higher than the desired bit is one (1), the analog test signal is reduced. If the desired bit and all higher bits are 0, the analog test signal is increased, If the desired bit is one (l),all higher bits are 0, and any lower bit is one (1), then the analog test 9ignal is reduced. After adjusting the analog test signal, steps 584 and 588 are repeated until decision 592 is satisfied.
When decision 592 is satisfied, the YES branch is followed to step 598. In step 598 the analog test signal value that satisfied decision 592 for this BIT N0 is saved.
In step 602 BIT NO is set equal to BIT N0 +1 preparatory to repeating the loop.
In decision 608, the count variable BIT NO is tested against the total number of bits, i.e. n+m. If BIT
20 NO is less than or equal to n+m, the NO path from decision 608 is followed to step 584. Steps 584 through 598 are then repeated until each bit position is assigned a weight in terms of an analog signal value.
When decision 608 is satisfied, the YES branch is followed to step 614. In step 614 a look-up-table is gen-erated for converting the (n+m)-hit special purpose digital code into the n-bit binary digital code, based on the pre-viously determined signal values of the bits in the (n~m)-bit special purpose digital code. For each possible (n+m)-bit digital code, the sum of the analog signal valuescorresponding to one (1) bits in the code is calculated.
The n-bit binary code corresponding to this analog sum is then determined and inserted in *he table.
FIGURE 23 is a flowchart illustrating another method forcalibrating an A/D converter of the type suitable for use with the present invention. In overview, the method calls for the use of a predet~ned s ~ le of analog test signal ~641q~

values to generate corresponding (n+m)-bit digital words in the special purpose code. The number of sample analog signals is significantly less than 2n, i.e. the number of all possible distinct test signals. The results of the sample conversions are then statistically analyzed to de-velop the conversion between the special purpose code and the binary digital code.
In step 620, an analog test signal value is selec-ted from a statistical sample of such analog test sig-nal values. In step 624, the selected analog test signal is applied to the A/D converter being calibrated to produce an tn~m)-bit word in the special purpose digital code. In step 628 the resulting (n+m)-bit digital word for this test analog value is saved.
In decision 632, the question is asked if all analog test signals from the statistical sample have been tested.
If no, the NO path is followed back to step 620, and the routine is repeated until all of the samples have been tested.
If decision 632 has been satisfied, the YES path is followed to step 63~. In step 638 a statistical analysis is performed on the stored (n+m)-bit digital words in the special purpose code to determine the analog value of each bit position in the special purpose (n+m)-bit code. For example, the bit values can be found by a least-squares fitting technique as is taught in F. B. Hildebrand, Intro-duction to Numerical Analysis, Chapter 7, McGraw Hill,1956.
A linear combination of binary-valued functions is least-squares fitted to the measured analog values. The binary-valued functions are the bits of the (n+m)-bit digital word. The linear combining coefficients are the analog values of bits being determined. This techni~ue will tend to average out small random measurement and converter errors, and thus produce more ac~urate results.
In step 642, a look-up-table is generated convert-ing the special purpose digital code to the binary digital code based on the results of the statistical analysis ~6~

of step 638. This generation is the same as step 614 of FIGURE 22.
The cali~ration processes described in connection with the calibration o~ an A/D converter of the present invention can be made to apply in analogous fashion to the calibration o~ a D/A converter of the present inven-tion.
The preferred form of D/A calibration is directly analogous to the single bit adjustment method illustrated in FIGURE 22 and described in connection therewith. In the case of D/A calibration the method involves the following steps.
Initially, an (n+m)-bit digital word having zeroes in all but a single bit position is applied as an input signal to a D/A converter of the present invention. This yields an analog output signal of a value that represents the weight of the non-zero bit position of the input word.
This analog value is then applied to an accurate n-bit ~/D converter to translate it into an n-bit output word. The resulting n-bit output word, which is the n-bit image of the (n+m)-bit input word, is saved. Alternately, this accurate A/D converter may have n+p bits, where p is one (1)~ two (2), or more; this will provide more accuracy in the calibration.
Another distinct (n~m)-bit digital word having zeroes in all but one bit position is selected. The sequence iter-ates, beginning with the initial step.
When all possible distinct n+m digital input words have been applied, a look-up table is generated on the ba-sis of the information relating each bit position of the(n~m)-bit digital code to a corresponding n-bit digital word. The look-up table may be partitioned into two parts to conserve memory space as was hereinbefore described under the part headed "Processor Implemented Systems".
If an ~/D or D/~ conversion system incorporating the present invention is to be implemented on a large ~L6~

scale integrated circuit, then it is not unreasonably burdensome to perform the calibration technlques illustrated in FIGURES 21, 22 or 23 for each LSI circuit produced. In fact, each circuit fabricated by LSI tech-niques is normally e~tensively tested by automated test methods. It would be possible to include the previously-described calibration techniques in the normal testing procedure.
VII. EPILOGUE
The foregoing has provided exemplary embodiments of the invention in forms that are readily achievable by modification of known converter types. ~owever, as here-inbefore stated in the Disclosure of the Invention, the invention can be taken to a more general'level where the only limitation on the special purpose code is that every analog value in the range represented by the normal n-bit code can also be accurately represented by the spe-cial purpose (n+m)-bit code. Specific embodiments of the invention, other than those hereinbefore described, but within the ull and proper scope of the invention, will suggest themselves to those having skill in the art. Many modifications and variations in the present invention are possible in light of the above teachings. It is, there-fore, to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as speci~ically described.

Claims (40)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A method for converting an analog signal to an equivalent digital word in an n-bit digital word code where the weight of each of the bits in the n-bit digital word code is dependent upon its bit position, the method comprising:
converting the analog signal to a corresponding word in a special-purpose (n+m)-bit digital word code, wherein the weight of each bit in the (n+m)-bit digital word code is dependent upon its bit position; and translating the corresponding word in the (n+m)-bit digital word code to the equivalent word in the n-bit digital word code.

2. The signal conversion method as defined in claim 1, wherein the n-bit digital word code is a binary digital code having each bit position related to the next lower order bit position by a factor of two.

3. The signal conversion method as defined in claim 1, wherein the (n+m)-bit special purpose code has n bits comparably weighted with the n bits of the n-bit digital word code and m bits comparable in weight with at least one selected bit of the other n bits of the (n+m)-bit code.

4. The signal conversion method as defined in claim 1, wherein the m bits of the (n+m)-bit word are repetitive of selected low order bits of the n bits.

5. The signal conversion method as defined in claim 1, wherein the m bits of the (n+m)-bit word are repetitive of the lowest order bit of the n bits.

6. The signal conversion method as defined in claim 1, wherein each bit of the (n+m)-bit word is related to the next lower order bit position by a factor less than two (2), but greater than one (1).

7. A device for converting an analog signal to an equivalent digital word in an n-bit digital word code where the weight of each of the bits in the n-bit digi-tal word code is dependent upon its bit position, the device comprising;
converter means, responsive to an analog signal for converting the analog signal to a corresponding word in a special-purpose, (n+m)-bit digital word code, where the weight of each bit in the (n+m)-bit digital word code is dependent upon its bit position; and translator means, responsive to the correspond-ing (n+m)-bit word, for translating the (n+m)-bit word to the equivalent n-bit word.

8. The signal conversion device as defined in claim 7, wherein the n-bit digital word code is a binary digital code having each bit position related to the next lower order bit position by a factor of two.

9 . The signal conversion device as defined in claim 7, wherein the (n+m)-bit special purpose code has n bits comparably weighted with the n bits of the n-bit digital word code and m bits comparable in weight with at least one selected bit of the other n bits of the (n+m)-bit code.

10. The signal conversion device as defined in claim 9, wherein the m bits of the (n+m)-bit word are repetitive of selected low order bits of the n bits.

11. The signal conversion device as defined in claim 9, wherein the m bits of the (n+m)-bit word are repetitive of the lowest order bit of the n bits.

12. The signal conversion 'device as defined in claim 7, wherein each bit of the (n+m)-bit word is related to the next lower order bit position by a factor less than two (2), but greater than one (1).

13. The signal conversion device as defined in claim 7, further comprising control logic means for receiving the (n+m)-bit digital word from the converter means, applying it to the translator means, receiving the n-bit digital word from the translator means, and applying the n-bit word to an output part.

14. The signal conversion device as defined in claim 7, wherein the translator means includes an address-able storage array with the address of each element of the array defined in terms of a unique (n+m)-bit digital code word, and where each element of the array contains the n-bit digital code word corresponding to its (n+m)-bit word address.

15. The signal conversion device as defined in claim 7, wherein the translator means includes an addressable storage array with each address location defined in terms of a unique (n+m)-bit code word, and which con-tains the difference between the (n+m)-bit digital code word corresponding to the n-bit word and the n-bit word.

16. The signal conversion device as defined in claim 7, wherein the translator means includes two or more addressable storage arrays, and where:
each storage array is associated with a differ-ent subset of the (n+m)-bits in the (n+m)-bit digital code word, each address location in each storage array is defined in terms of a unique code for the corresponding subset of the n+m bits, each element of each array contains an (n or greater)-bit code word corresponding to the bits used in its address, and the two or more (n or more)-bit code words obtained from the two or more storage arrays are combined to obtain the n-bit code word corresponding to the complete (n+m)-bit digital code word.

17. The signal conversion device as alternately defined in claim 14, claim 15, or claim 16,wherein the addressable storage arrays comprise programmable read-only-memories (PROM).

18. The signal conversion device as defined in claim 7, wherein the converter means comprises a con-version network for converting the analog signal in a sequence of iterative steps, the conversion network being defined to include, summing means for receiving the analog signal and a feedback signal of opposite polarity to the analog signal and producing a difference signal represent-ing the summation thereof, threshold means, responsive to the difference signal, for outputting a first error signal if the differ-ence signal exceeds a predetermined threshold, and a second error signal if the difference signal is less than the negative of the predetermined threshold;
logic and storage means, responsive to the first and second error signals, and having an (n+m)-bit digital output signal, for increasing the value of the digital output signal upon the receipt of the first error signal, and decreasing the digital output signal upon the receipt of the second error signal, and D/A converter means, responsive to the (n+m)-bit output signal of the logic and storage means, for producing another analog signal corresponding in negative relation to the output signal of the logic and storage means and which defines the feedback signal, whereby the corresponding word in the special pur-pose code is derived from the (n+m)-bit digital output signal of the logic and storage means.

19 The signal conversion device as defined in claim 18, wherein the D/A means comprises a parallel (n+m)-stage D/A converter, with m stages comparable in weight with at least one of the n stages.

20. The signal conversion device as defined in claim 18,wherein, the summing means is defined to include amplifier means for amplifying the difference signal.
and the threshold means is defined to include first switch means, responsive to the amplified differ-ence signal, for outputting the first error signal when the amplified difference signal is above the predetermined threshold, and second switch means, responsive to the amplified difference signal, for outputting the second error signal when the amplified difference is less than the negative of the predetermined threshold.

21. The signal conversion device as defined in claim 20, wherein the summing means further includes limiting means for limiting the absolute value of the amplified difference signal.

22. The signal conversion device as defined in claim 18, further comprising timing means for producing a train of periodic timing signals, and wherein the logic and control means comprises an up-down counter having at least n+m bits, and is respon-sive to the periodic timing signal to increment or decre-ment the digital output signal in accordance with the presence of a first or second error signal once for each occurrence of a periodic timing signal.

23. The signal conversion device as defined in claim 7, wherein the converter means comprises a conver-sion network for converting the analog signal in a sequence of iterative steps, the conversion network being defined to include, timing means, having at least n+m ordered timing stages, for producing a sequence of timing signals, each stage producing one signal in the sequence in timed relation to its order, summing means for receiving the analog signal and a feedback signal and producing a difference signal of a first polarity if the difference between the analog and feedback signals is positive, and of a second polarity if the difference is negative, storage means, having n+m ordered stages, each of the stages being responsive to the concurrence of a timing signal from a correspondingly ordered timing stage and the difference signal, for unconditionally setting an output signal to a first level, and condition-ally setting the output signal to a second level if the difference signal is of the first polarity, the combined output signals from the n+m stages defining a (n+m)-bit output word, D/A converter means, responsive to the (n+m)-bit output word of the storage means, for producing another analog signal corresponding in negative relation to the output signal of the logic and storage means and which defines the feedback signal, whereby the corresponding word in the special purpose code is the (n+m)-bit output word of the storage means after the occurrence of the (n+m)th timing signal.

24. The signal conversion device as defined in claim 23, wherein the timing means has at least (n+m+1) ordered timing stages, and further comprising, output gating means, responsive to the (n+m)-bit output word of the storage means and the (n+m+1)st sequential timing signal, for producing the corresponding word in the special purpose code upon the occurrence of the (n+m+1)st timing signal.

25. The signal conversion device as defined in claim 23, wherein each stage of the storage means includes means for resetting its output signal.

26. The signal conversion device as defined in claim 23 r wherein the summing means includes amplifier means for amplifying the difference signal by a predeter-mined scale factor.

270 The signal conversion device as defined in claim 23, wherein the summing means further includes limit means, associated with the amplifier means, for limiting the output magnitude of the amplified differ-ence signal to within a predetermined range of magnitudes.

28. The signal conversion device as defined in claim 23, wherein each stage of the storage means includes a bistable latch.

29. The signal conversion device as defined in claim 23, wherein the D/A means comprises a parallel, (n+m)-stage D/A converter, with m stages comparable in weight with at least one of the n stages.
30. The signal conversion device as defined in claim 7, wherein the converter means comprises a conver-sion network for converting the analog signal in a sequence of iterative steps, the conversion network being defined to include, timing means for producing a sequence of periodic timing signals having at least n+m signals in the sequence, summing means, having first and second in-puts, for summing the signals applied to the first and second inputs to produce a difference signal, first switch means, responsive to the sequence of periodic timing signals, for coupling the analog signal to the first input of the summing means upon the occurrence of the initial timing pulse in the sequence, and coupling an analog feedback signal to the same first input upon the occurrence of the remaining timing pulses in the sequence,

Claim 30 . . . continued.
second switch means, responsive to a digital feed-back signal for coupling an inverted reference signal to the second input of the summing means when the digital feedback signal is of a first level and coupling the same input to a ground reference signal when the digital feedback signal is of a second level, comparator means having a first input receiving the difference signal from the summing means and a second input receiving a scaled representation of the reference signal,for producing a single-bit digital signal of a first level when the first input signal exceeds the second input signal and of a second level when the second input signal exceeds the first input signal, first scaling means, responsive to the output of the summing means, for scaling the difference signal by a first scale factor, second scaling means, responsive to the output of the summing means, for scaling the difference signal by a second scale factor, storage means for storing an analog signal defin-ing the analog feedback signal, third switch means, responsive to the sequence of periodic timing signals, for enabling the first scaling means upon the occurrence of preselected ones of the timing signals, and enabling the second scaling means upon the occurrence of the other timing signals, fourth switch means, responsive to the sequence of periodic timing siqnals, for coupling the storage means to the enabled scaling means during one predeter-mined interval of a timing signal period, and the storage means to the first switch means during another predeter-mined interval of the timing signal period, whereby the sequence of single-bit digital signals from the comparator means during n+m timing sig-nal periods defines the digital word in the special pur-pose code.

31. The signal conversion device as defined in claim 30, wherein the third switch means includes an analog switch having a control input and gate means, coupled to said control input, for gating the preselec-ted ones of the timing signals to the control input.

32, The signal conversion device as defined in claim 30, wherein the first scaling means has a scale factor of two (2), and the second scaling means has a scale factor of unity.

33. The signal conversion device as defined in claim 30, wherein the preselected ones of the timing signals are the initial n signals and the other timing signals are m succeeding timing signals.

34. The signal conversion device as defined in claim 30, wherein the summing means is further provided with an amplifier means for amplifying the summed repre-sentation of the first and second input signals.

35. The signal conversion device as defined in claim 30, wherein each of the switch means comprises a single pole-double throw analog switch.

36. The signal conversion device as defined in claim 7, wherein the converter means comprises a conver-sion network for converting the analog signal in a sequence of iterative steps, the conversion network being defined to include, timing means for producing a sequence of periodic timing signals having at least n+m signals in the sequence, summing means, having first and second inputs for summing the signals applied to the first and second inputs to produce a difference signal, first switch means, responsive to the sequence of periodic timing signals, for coupling the analog signal to the first input of the summing means upon the occurrence of the initial timing pulse in the sequence, and coupling an analog feedback signal to the same first input upon the occurrence of the remaining timing pulses in the sequence, second switch means, responsive to a digital feed-back signal for coupling an inverted reference signal to the second input of the summing means when the digital feedback signal is of the first level, and coupling the same input to a ground reference signal when the digital feedback signal is of a second level, comparator means having a first input receiving the difference signal from the summing means and a second input receiving a scaled representation of the reference signal, for producing a single-bit digital signal of a first level when the first input signal exceeds the second input signal and of a second level when the second input signal exceeds the first input signal, scaling means, responsive to the output of the summing means, for scaling the difference signal by a scale factor, wherein the scale factor is less than two, but greater than one, storage means for storing an analog signal de-fining the analog feedback signal, third switch means, responsive to the sequence of periodic timing signals, for coupling the storage means to the scaling means during one predetermined inter-val of a timing signal period, and the storage means to the first switch means during another predetermined interval of the timing signal period, whereby the sequence of single-bit digital signals from the comparator means during n+m timing signal periods defines the digital word in the special purpose code.
37, The signal conversion device as defined in claim 7, wherein the converter means comprises a conver-sion network including, digital storage means, having at least n+m ordered

Claim 37 . . . . continued.
storage stages, for receiving and storing a bit value in each of the stages, analog storage means for storing the analog signal, a plurality of at least n+m ordered A/D conversion stages, each stage defined to include, comparator means, having a first input receiving a reference signal and a second input receiving an analog output signal from an immediately preceding stage, the initial stage receiving the analog signal from the analog storage means, for producing a single-bit digital output of a first value if the second input signal exceeds the first input signal, and of a second value if the first input signal exceeds the second input signal, difference means, having a first input re-ceiving the analog output signal from the immediately preceding stage and a second input, for producing a difference signal proportionate to the difference between the signals received on the first and second inputs, switch means, responsive to the single-bit digital output of the comparator, for coupling the reference signal to the second input of the difference means when it is of the first value, and decoupling the same when it is of the second value, signal scaling means, responsive to the difference signal, for scaling the difference signal by a scale factor preselected for that A/D conversion stage to provide the analog output signal for that stage, and control switch means, responsive to a timing signal, for coupling the comparator means output of each of the ordered D/A conversion stages to a correspondingly ordered digital storage stage to load the comparator means output into that stage, whereby the corresponding digital word in the special purpose code is defined by the n+m bits loaded into the digital storage means.

38. The signal conversion device as defined in claim 37, wherein the scale factor for the scaling means of the initial n stages is two (2), and the scale factor of the scaling means for the succeeding m stages is unity.

39. The signal conversion device as defined in claim 37, wherein the scale factor of the scaling means is less than 2, but more than 1, for each of the n+m stages.

40. The signal conversion device as defined in claim 37, wherein the control switch means comprises a plurality of single-pole switches interposed between correspondingly ordered A/D conversion stages and digital storage stages, each responsive to a periodic timing signal to couple corresponding stages.