CA1158307A - Push-pull switching power amplifier - Google Patents

Abstract

ABSTRACT
Disclosed is a switching power amplifier of high efficiency, small size and weight and excellent dynamic performance, together with reduced pul-sating for both input and output currents. Switching ripple is completely eliminated, unlike in conventional designs. The amplifier is provided by a pair of converters with feedback control of the pulse width of applied switch-ing pulses. Each converter has two inductances, one in series with a DC power source and one in series with the load, storage capacitance, and switching means for alternately connecting the junction between the first inductance and the storage capacitance to ground return for the source, and connecting the junc-tion between the storage capacitance and the second inductance to ground return for the load. When the input inductances of the two converters are made equal, the ripple input currents to the two converters result in zero-ripple source current. The switching means for one of the two converters is driven with the complement of the pulse-width modulated control signal applied to the other. In each converter, the input and output inductors are coupled by providing the in-ductors as windings of a transformer designed for the condition n = k, where n is equal to the square root of the ratio of the self-inductances of the input and output windings, and k is the coupling coefficient between the windings for zero output current ripple.

Description

1 ;IS~307 ORIGIN OP INVENTION
The invention described herein was made in the performance of work under a NASA contract~ This application is a division of our Canadian patent application Serial Nwnber 326,865 filed May 3, 19790 BACKGROUND OF T}E IN~N ION
This invention relates to switching power stages and amplifiers, and ~ore particularly to a push-pull switching amplifier having zero output switch-ing ripple.
Switching amplifiers based on the buck-type converter have been kno~n in the past, but not widely used because of their deficiencies. A con-ventional buck-type am~lifier will be described and some of its deficiencies di~cussedO Then after the present invention disclosed herein has been described, a comparison of the invention ~ith the prior-art switching amplifier will be made to reveal the superior characteristics of the invention.
The new switching amplifier is based on the new switching DC-to-DC
CQnverter disclosed in a paper titled "A New Optimum Topology Switching DC-to-PG Gonverter" by Slobodan Cuk and RoD~ Middlebrook published in the Proceedings of the IEEE Power Electronics Specialists Conerence, 1~77~ Record pages 160-179J Palo Alto, California~ June 1~-16, 19770 That optimum topology converter 2Q is here used in a special bidirection implementation to provide a push-pull amplifier configurationO Hence all of the advantages of the new converter are obtained, such as high efficiency, small size and weight, and excellent dynamic performance, together with reduced pulsating for both input and output currents.
rhe m~st important bene~its, however, come ~rom the use o~ the coupled-:inductor technique o~ the new converter for the basic power stage in this special push-pull s~itching amplifier, which results in a high performance an~plifier with complete alimination of t]le switching ripple in the output, one of thc limita-tions in the conventional switching amplifier design. Thus, the new switching ,. -- 1 ~

~.~

l :~583~

amplifier has potential for a wide range of applications from a high efficiency, small size and weight, and fast response servo power amplifier to a low-cost high-performance audio amplifier.
OBJECTS AND SUMMARY OF T~IE INVENTION
In accordance with the present invention, there is provided a DC-to-DC converter capc~ble of bidirectional current flow comprising first and second inductances in series with storage capacitance between the inductances, and bidirectional symmetrical switching means for alternately connecting the junc-tion between said first inductance and said storage capacitance and the junction between said storage capacitance and said second inductance, to a return cur-rent path to a source connected to either of said fi~st and second inductances, said bidirectional symmetrical switching means of said converter being comprised of an npn transistor connecting the junction between said first inductance and said storage capacitance to said return current path to said source, and a first diode connecting tha junction between said second inductance and said storage capacitance to said return current path to said source, a pnp transistor connecting the junction between said second inductance and said storage capaci-tance to said return current path to said source, and a second diode connecting the junction between said first inductance and said storage capacitance to said return current path, and means for alternately turning said npn and pnp transis-tors on in a complementary manner for bidirectional current flow from said source to said load, whereby said first and second inductances can be arbitrar-ily connected, one to a source of power and the other to a load.
The novel features that are considered characteristic of this inven-tion are set forth with particularity in the appended claims. The invention will best be understood from the following description when read in connection with the accompanying drawings.

3 ~ 7 BRIEF DESCRIPTION OF T}IE DRAWINGS
Figure 1 is a schematic diagxam of a conventional buck converter with ou-tput voltage of either polarity.
Figure 2 is a graph of the DC voltage gain of the power stage in Figure 1.
Figure 3 is a schematic diagram of a practical implementation of the converter in Figure 1.
Figure ~ is a schematic diagram of the switching power amplifier of Figure 3 operated in open loop.
Figure 5 is a schematic diagram of the switching power amplifier of Figure 3 operated in closed loop.
Figure 6 is a schema-tic diagram of a new converter capable of bidirectional current flow.
Figure 7 is a schematic diagram of two new converters ~Figure 6) operated in tandem (parallel) from a single power supply.
Figure 8 is a graph of the voltage gain V/V of the power stage of Figure 7.
Figure 9 is a schematic diagram of a new push-pull power stage.
Figure 10 is a schematic diagram of an implementation of the new power stage of Figure 9.
Figures lla and llb are graphs showing input currents and source currents for the power stage of Figure l0.
Figure 12 is a schematic diagram of the new power stage of Figure 10, with coupled inductors, in a closed loop to provide a new push-pull power amplifier.
Figure 13a is a schematic diagram of a boost converter in a new push-pull power stage, and Figure 13b is a block diagram of a closed loop amplifier using such a push-pull power stage, or other equivalent push-pull 1 15~330'7 power stage.
Figure 1~ is a graph illustrating the optimum and ideal DC gain trans-fer characteristic of the power stage of Figure 10.
Figure 15 illustrates a push-pull power stage from an audio ampli-fier designed in the arrangement of Figure 12.
Figure 16 illustrates the open-loop DC gain characteristic of ~he power stage of Figure 15.
Figure 17 is a graph illustrating the effect of input resistance upon loop gain frequency response of the push-pull power amplifier of Figure 12 with the power stage of Figure 15.
Figure 18 is a graph illustrating the experimental loop gain char-acteristic of the push-pull power amplifier of Figure 12 with the power stage of Figure 15.
Figure 19 is a graph illustrating the closed-loop gain of the push-pull power amplifier of Figure 12 with the power stage of Figure 15.
DESCRIPTION OF PRIOR ART
In the conventional buck converter utilizing a series inductor L and a storage capacitor C~ periodic switching between +V and ground (for interval DTs at +V , and interval D'T = (l-D) T at gro~nd), results in the duty ratio controlled output DC voltage V=DVg, where D is the switch duty ratio and fs =
l/Ts is the constant clocked switching frequency. This results in a power stage whose output to a load R can have only one polarity.
A power stage whose output voltage can have either polarity (positive or negative with respect to ground), depending on the value of the duty ratio of the switch, can be provided with such a conventional buck converter b~
connecting a second power supply -Vg to the switch in place of ground as shown in Figure 1.
By use of the customary Volt-sec balance condition on the inductor L
. - 4 -~L ~L 5~307 in the steady-state, we obtain:
(Vg-V)DTs = (Vg+V)D'Ts (1) or V = D - D' = 2D - 1 (2) Thus, the DC voltage gain is a linear function of duty ratio D as sho~ in Figure 2, and for D > 0.5 the output voltage is of positive polarity, while for D < 0.5 it is of negative polarity.
While the actual hardware implementation of the ideal switch S in a conventional buck converter of only one output polarity by use of a bipolar transistor and diode is rather obviousJ the reversal of the output voltage in the converter of ~igure 1 makes the hardware realization of its ideal switch S
less apparent, and necessitates reexamination of the requirements imposed on it.
Namely, since the average inductor current generates the ou~put DC voltage, re-versal of the output voltage polarity is accompanied by reversal of the inductor current direction, as shown by full and dotted line arrows in Figure 1. Hence, the hardware implementation of the switch S has to permit this bidirectional current flow. This is readily accomplished by the two-transistor, two diode circuit of Figure 3.
Transistors Ql and Q2 in Figure 3 are alternatively turned on and off by their drives (when Ql is turned on for interval DTs, Q2 is turned off, and vice versa~, while diodes Dl and D2 work in synchronism with them. Namely, for D > 0.5 (positive output voltage polarity) when Ql is turned on Vl~ Vg (satura~-tion voltage neglected), the average DC current I is positive. When Ql is switch~
ed off, the inductor forces Dl to conduct and Vl ~ - Vg (diode drop neglected).
If Q2 is switched on at this moment, its base-collector junction is forward biased, but the net effect on the circuit operation and diode Dl conduction is negligible. When transistor Ql switches on again Vi = Vg and diode Dl turns off. Transistor Q2 and diode D2 operate similarly for the other current direc-- tion (shown by the dotted arrow in Figure 3) for D ~ 0.5.

3 ~ 7 The conceptual block diagram of a switching power ampli:fier operated in an open-loop manner, and incorporating the power stage of Figure 3 is shown in Figure 4. It includes a comparator 10 and a driver 11.
The diagram is the same as that for the open-loop switching DC-to-~C
converter of Figure 3 operated at constant switching frequency f = l/Ts (clocked type), with the only difference that a time varying ~sinusoidal, for example) input signal is used at the comparator input instead of a DC reference voltage. Thus, the need for a power stage with output voltage of either polar-ity, now becomes evident: for the positive half-cycle of a sinusoidal audio signal, the comparator generates a duty ratio D > 0.5 and output voltage of positive polarity, while for the negative half-cycle D < 0.5, a negative output voltage is generated. In fact, compari.son of the low frequency input signal and the high frequency sawtooth (clocked ramp), generates a pulse width modulated (PWM) signal, whose low frequency spectrum is recovered by low-pass filtering.
Hence a close replica of the input signal but now at high power level is generated at the output.
The comparison of this switching power amplifier approach with the customary conventional linear power amplifier design with respect to the two foremost constrains in the power amplifier design, that is the efficiency and distortion, becomes now apparent. In terms of efficiency, this app:roach boasts the usual advantages of switching power supplies over linear, that is, signifi-cantly lower power dissipation. Namely, its theoretical 100% efficiency is usually only slightly degraded (very often efEiciency is above 90%), owing to the most efficient use of semi-conductor devices as power processing elemcnts, that is as switches. Power dissipation problems are thus minimized, and become Elmctions of the transistor saturation voltage, its switching time and parasitic resistances of storage elements in the power path. Distortion, however, is a function of switching frequency in this switching amplifier approach, rather :~ ~5~3i)~

than depend0nt on the linearity of transistor I-V characteristics. Specifically, for low distortion switching fre~uency f has to be an order of magnitude or so higher than the signal frequency f to avoid overlapping sidebands in the PWM
signal~ even when the clocked ramp i5 of ideal linearity.
On the other hand, one would like to avoid an excessively high s~itching frequency for several reasons. Linearity of the sawtooth waveform may be hard to realize at higher switching fre~uencies. The storage time of the transistor switch then may represent a significant portion of the switching period thus further introducing distortlon, and degrading the efficiency as well.
~andwidth VSD output ripple constitutes another trade off. A general rule of thumb used by designe~s of switching power supplies is that for low ripple~ the switching frequency must be at least two decades above the corner frequency fc ~ 1/2~ of the L-C averaging filter. Thus~ to obtain flat amplitude fre ~uency response out to 20 kH~ in audio power amplifier applications, the aver~
aging filter corner frequency in the open-loop configuration of Figure ~ must be at least 20 kH~. Therefore~ one must either switch at ~ MHz ~too high a fre-quency to be practical) or sacrifice low output swi-tching ripple. In addition, several other drawbacks originate from this open-loop approach. Any nonlinear-ity of the sawtooth wave~orm ~clocked ramp) and of the DC galn characteristic

2~ of the power stage, shows up as additional distortion in the output. Thus, the linear DC gain characteristic ~Figure 2) of the buck converter in Figure 3 be-co~es mandatory in this open-loop approachO Finally, both power supplies ~posi-tive and negative), have to be well regulated to avoid yet another source of distortion. rrhe solution to these problems lles, of course, in the use of nega-tive feedback as shown by the block diagram of the closed-loop buck-type switch-ing power amplifier in Figure 5. It employes a loop comparator 12 to provide to -the comparator 1~ the difference between the output wave form and the signal inputO

5~3~7 Several beneits generally associated with the use of negative feed-back are obtained. The corner frequency of the L-C averaging filter may now be placed at a lower frequency of 2 kl-l~, for example, and then negative feedback us.ed to extend the closed-loop gain bandwidth out to ~ kllz as desired for a good audio power amplifier frequenc~ response. A switching frequency of 200 k~z or higher would then pro~ide low switching ripple. Also a significant il~provement in accuracy and DC s~abiliæation is obtained. Furthermore, a cer-tain degree of nonlinearity in both the sawtooth waveform as well as DC gain of the power stage could be -ctolerated, and overall distortion of the amplifierreduced by the amount of feedback loop gain introducedO In addi~ion, the amp-lifier becomes less sensitive to noise intro~uced by the power supply, transis-tQx switching delay times and other nonidealitiesO Of course, the price one has to pay for these improvements i5 increased comple~ity and possible stabilizationproblems. However, this does not seem to pose any serious limitations. As seen in Figure 4, the block diagram of the switching mode power amplifier is the sameas for the switching mode regulator, and thus, all the techniques for analysis of the closed loop-gain stability and regulator performance developed, as well a~ measurement technique, are equally applicable to the switching audio power ampliier.
2U The analysis of the operational principles of switching power ampli-fiers., e~en though based on the buck power stage as the only thus far known con-figuration, demonstrates that in principle any switching regulator ~based on other switching po~er stages) or even open-loop driven~switching converter can be macle into a power amplifier, provided its power stage is appropriately modi-fied to result in an appropriate two quadrant V--I characteristicO ~`he fact that the buck power stage is the only one used 50 far may be quite misleading.

_ ~ _

3 0 7 This is probably caused by the ailure of lnltial attempts ~o appropriately modif~ boost or buck-boost power stages for s~itching amplifier applications.
Despite t~e negative ~eedback and constant ~clocked~ swi~ching fre-quRncy ~s~ the closed-loop ~witching amplieier of Figure 4 still has several drawbacks ~hiCh originate direc~ly from the buck power stage itself. In parti-cular, the current drawn from the power supplies is pulsating and can generate tremendous amo~mts of noise. This is a serious problem if left uncorrec-ted.
For example, trying to listen to the radio in the noise contaminated environ-ment caused hy this amplifier ~uld probably result in frustration. Thus, a lQ properly designed input ilter ~ust be added to each power supply preferably ~ith little effect upon the loop-gain. AnQther drawback is that there is need for two power supplies o~ o~posite polarity. Also, a quite elaborate scheme ~or drivlng the trans~stors of the buck-power stage in Figure 3 is required, since neither of the transistors is referred to gound. Therefore either float-~ng isolated drives are necessary, or a push-pull nonlsolated drive scheme C~hich requires two additional power supplies, above -~Vg and below -Vg~ to turn on and of the transistors Ql and Q2~ would have to be implemented. In additionJ
very~careful precautions have to be taken to prevent simultaneous turn on of transistors Ql and Q2~ thus shorting the two power supplies and resulting in transistor destruction. Finally, a relatively high switching frequency ~300 kHz or so~ is still necessary to reduce switching ripple.
Thus, we have come to th~ conclusion that a new switching converter (power stage~ with properties superior ta those of a buck converter ~Figure 1 c~nd l~igure 3~ is nceded to replace the buck-power stage in the feedback arrange-~ent of I'igure 5. An object of this invention is therefore to find a s~itching con~erter which will re~ove all of tlle above deficiencies. Such a converter arld 9 _ its properties> and various, us,eful extens,lons,, are disclosed in the aforesaid paper titled l'A New Optimum Topology Switching DC-to-DC Converter"O Thus, only the highlights, of the new opti~um topology switching converter and its coupled-inductor extension as related to the s~itching po~er amplifier applica~ion will be included here.
~SCRIPTION OF PREF~R~D ~MBODIM~NTS
The original configuration of the new conver~er described in the aforesaid paper is capable only of unidirectional current (and po~er) flow.
Ilo~ever, symmetrical implemen-tation of the transistor Ql and diode Dl switch 1~ combination by addition of a single pnp trans,istor ~2 and diode D~ removes this constraint and results in a bidirectional current and power flow as shown in Figure 60 The same reference numerals for the transistor-diode switch combina-tions are being used here as ln the prior ar~ converters of Figures 3, ~ and 5 s,ince they perform the same function,, although not in the same converter circuit.
~ere t~o inductors Ll and L~ are used with a s-torage capacitor Cl in accordance ~ith the teachings of the aforesaid paper. What is new is the addition of the transistor Q2 and diode D2, as just noted for symmetry in switching.
The entire converter is thus s~nmetrical, and the input and output terminal~ can be arbitrarily designated. In addition, each of the terminals can behave either as a current source or as a current sink, owing to the bidir-ectional current implementation of the switch. Thus the configuration of Figure 6 becomes ideal for the battery charger/discharger application where both functions are reali~ed by this single converter structureO The direction of current flo~y through the converter is determined by wllether the duty ratio is greater or les,s than the value that just matches the conversion ratio to the ratio of the bus to battery voltagesO Also, the 'bidirectional current feature - 1() -of the converter reali~a-tion of Figure ~, results in the "continuous conductionmode" of operation even when there is a zero power throughput. Thus the dynamics of the converter does not change between "continuous" and "discontin-uous~' conduction mode and the dynamic models for continuous conduction mode are equally applicable for this transitional region between two power flow directions. Note also that this bidirectional current switch implementation is, equally applicable -to the coupled inductor extension oE the new switching converter described in a paper ~itled "Coupled-Inductor ~nd Other Extensions of a New Optimum Topology Switching ~C-to-DC Converter~' by Slobodan Cuk and R.D.
~iddlebrook published in the Proceedings o the IEEE Industry Applications 50ciety Annual ~eeting, 1~77 Record, pages 1110-1126, Los Angeles, California, actober 2-6~ 1~77, The converter configuration of Figure 6 does have some very ilnpor-tant advantagesO, For example, both transis,tors are referenced to groun~ and are eas;ier to drive than those of Figure 3u Moreover use of the single drive source for the complem~ntary npn and pnp switches, as shown in Figure 6, not only tremendously simplifies the driving scheme, but also automatically preventssimultaneous turn-on of both transistors, Ql and Q2 (and thus pre-vents shortingcapacitance Cl), in spite of the pres,ence of transistor switch storage time.
2Q Therefore all of the problcms associated with the buck converter s,tage of Figure 3 mentioned earlier have been resolved with the converter con-figuration of Figure 6. It now remains to describe how this configuration can be included in a switching power amplifier scheme.
A power stage based on the new converter of Pigure 6 with the cap-ability oE producing an output voltage of either polarity will now be described with reference to Figure 7u Although there are probably several ways to accomp-11 ~ 5~3~7 lish this, only -the simplest and most suitable way, which will preserve all the good properties of the new converter, and add some more, such as a single power supply, will be d~scribedO In this arran~ement of Figure 7, two new switching converters as shown in Figure 6 are operated in tandem (parallel).
Let US now assume that $he two converters are operated out of phase3 that i5 with complementary switch drive ratios~ Namely, when switch Sl is in position Al for interval DT , switch S2 is in position B2 for the same interval.
~uppose also that the two loads Rl and R2 and the operating conditions are such that both converters are operating in the continuous conduction modeO Then the output voltages V1 and V2 across the two loads are ideally (no parasitic resis-tances taken into account):

ID ) V

V2 = ~D ~ Vg (~) As seen from these equations, the two output voltages are equal only ~or D - 0.5 while one or the other becomes greater for other duty ratios. ~hus, evaluating their differences V = Vl - V2 leads to:

V = ~ ~5) which is sketched as a function of dllty ratio D in heavy line in Flgure 8. The individual converter gains Vl/Vg and -V2/Vg are shown in dotted line.
2a As seen in Flgure 8, the di~Eerential gain of equation ~5) is j~st the one needed for switching power amplifier applications~ since it has the same re~luired polarity change pr~perty as the D~ valtage gain shown in Figure 2 Eor ~ li 5~3~7 modified buck power stageO The only trouble is that there is not yet a load between two converter outputs to draw any power from the stage. Thus an inter-esting question arises: Is it possible to connect a load between the outputs of the two converters running in parallel without violating some basic laws or disturbing the individual proper operation of the converters~
The answer to this question is affirmative and is a key to the suc-cess of the new push-pull switching power amplifier designO Thus, with the two loads in the converter of Figure 7 replaced by a differential ~"floating") load R, the new push-pull power stage of Figure ~ is obtainedO Comparison with the power stage of Figure 7 from which it originated now seems in orderO
In the power stage of Figure 7 the two switching converters do not affect each others operation, and both havP a unidirectional current ~and power) flow as shownO However, this is not so in the push-pull power stage of Figure Namely, owing to the differential ~"floating") connection of the load, be-t~een the two individual converter stages, its load current i is sourcing at one converter output and sinking at other converter output, resulting in the opposite current flow in the two constituent convertersO For example, for the direction of current i in heavy line on Figure 9, the lower conver-ter behav~s as a current source, while the upper becomes current sink~ With the opposite pol-arity of the output current i ~dotted line), the role of the two converters isreversedO Thus, switches Sl and S2 have to pe.rmit this bidirectional flow of current (and power) depending on the duty ratio D. In other words, a part of the energy delivered by the lower converter is consumed by the load, and the re-mainder returned via the upper converter to the sourceO The ~ctual hardware implementation of the bidirectional current (and power) flow is, however, easily accomplished by use of the transistor/diode pairs Of Figure 6, as shown in ~igure 10. It may now become evident why the new amplifier power stage is called a true push-pull power stageO Namely~ while the lower converter pushes the current i ~and energy) through the load, the upper converter pulls it from the load, and vice versaO
A convenient feature of this hardware implementation of the switch-ing scheme is that all four transistors are referred to ground ~grounded emit-ter), making them easy to driveO In addition, the npn and pnp ~ransistor of each stage can be driven with the same PWM drive source, but in phase opposi-tion as shown. Thereore, the overlap of the transistor on times is automati-cally prevented, even in the presence of significant transistor storage times.
It may also be noticed that this bidirectional current implementation avoids the transition to discontinuous conduction mode ~i.eO~ the power stage always operates in continuous conduction mode), justifying the assumptions of equations ~3) and ~) made aboveO
An additional very desirable eature is sti].l derived from the push-pull connection itselfO Namely the current i drawn from the souTce V at any time is ig ~ il - i2 ~6) where currents il and i2 are both positive ~directions as in Figure 10), and their slopes are inversely proportional to their induc-tance values.
As seen in Pigure llb~ an interesting situation is obta:ined when input inductors are the same as in Figure 10, iOeo3 when Ll = Ll o:E both inver-ters, the current i drawn by the power supply is DC only with no ripple at allO
Namely~ while the inductor current il is increasing at some rate ~:Eor interval DTS), the other inductor current i2 is returning at the same rate, as shown in Pigure lla thus supplying the rate increase of il. ~ence, overall only DC

3 ~ ~

current is drawn from the power supply. This very desirable extra feature re-sults from the true push-pull configuration itselE.
This novel technique of the push-pull like topology~ differential load, and bidirec~ional current switch implementation, which has been used to obtain the new power stage of Figure 10 from the original new converter, can be applied to obtain a closed-loop amplifier as in Figure 12. Two-phase control is achieved through a driver 20 comprised of inverting amplifiers translating the true (Q) and complementary ~Q) outputs of a flip-flop 21 into A and B control signals applied to the bases of the switching transistors Ql and Q2 of each switching D~-to-~C converter, The two transistors of each converter may themselves be driven by the same signal in a complementary manner because one is an npn type and the other is a pnp type. Other equivalent, but more complex arrangements may be used to implement this bidirectional current capability achieved in each converter with the transistor-diode pairs comprised of transistor Ql and diode Dl and transistor Q2 and diode D2. A pulse width modulated signal is used to switch the flip-flop 21~ The pulse width modulated signal is produced using a comparator 22 to compare a control signal and a sawtooth waveform. For a closed loop amplifier, a loop comparator with a differential input is implemented with a differential amplifier 23 connected to amplify the voltage across the load and a comparator 2~o This is similar to the loop comparator of Figure 5, but is with the new power stage in which the load R is floating between the output voltage levels of the two power stage converters operated in a true push-pull modeO This same novel technique of the push-pull like topology may also be applied as well to other known converter types, such as boost, or buck-boost converter. As an example, a power stage hased on the boost converter and suit-ahle for use in a switching power amplifier is shown in Figure 13a. Figure 13b ~ 1 5830~

lllustrates in a block diagram the general form of a closed loop power ampli-fier using any known converter types for the power stage comprised of two switching D~-to-DC converters 31 and 32, each with bidirectional current capa-bility, and a single power supply, ~g. The converters outputs are connected to opposite ends of a load, R, and operated in a push--pull mode by a two-phase control unit 33 through a driver 330 A pulse width modulator 35 receives a signal to be amplified from a loop comparator 36 having a differential input stage to compare an input signal with ~he voltage across the load. ~he di~fer-ential input stage is designed to provide a total gain of substantially less than one $or comparison with a small signal input. That is preferably imple-mented with a poten~iometer in a voltage dividing network at the input of the differential input stage in order to control the loop gain. A buck power stage similarly modified would result in a single power supply configuration as com-pared to the two po~er supply strategy of Figure 1. However, either design still has all the draw~acks mentioned earlier wh0n compared to the power stage in Figure 10 based on the new converterO
ln practicing the present invention, the most advantageous configura--tion is obtained when the coupled-inductor extension of the power stage in Figure lO is usedf as shown in Figure 12, which represents a closed-loop dia-2~ g~a~ of the new push~pull s~itching power amplifier connected to drive a speaker25. Briefly, inductors Ll and L2 of each o~ the two converters are coupled as sho~n ~ith a matching condition n=k where n is the square root of the ratio of self-inductances Ll and L2 of the respecti~e input and output inductors, and k i~ the coupling coefficientu IJnder those matching conditions, the output c~r-rent ripple is rcduced to zero, thereby tremendously improvlng the amplifier per-formance because there is no longer any need for excessively high switching fre-~ 1 5~3~7 quencies to reduce the a~plifier switching ripple at the outputO The ripplewill all be shifted to the input currents il and i2 but~ as shown before, the current drawn from the power source will also be DC only, thus approaching the ideal DC-to-DC power stage characteristic in having DC currents at both input and output.
When the two transfor~ers ~coupled-inductors Ll and L~) are designed to satis~y the ]natching condition, zero current ripple is obtalned at the out-put, as just noted, and the need or output ilter capacitors C~ is completely eliminated. The elimination of output filter capacitors results in further simplified and extremely favorable loop-gain dynamics ~effectively single pole frequency response~ as will be shown later) which permits closing the feedback loop directly, even without any co~pensation network, and yet resulting in a high degree of stabilityO Also there is no longer any need for an excessively high switching requency to reduce the amplifier ripple, thus resulting in fur-~her improvementO Therefore, the closed-loop switching ampliEier configura-tion of Figure 1~ has a number of advantages which will become even more evi-dent when a comparison of the conventiona] buck-type design of Figure 5 and the new push-pull switching power amplifier of Figure 12, is made.
Quite low open-loop harmonic distortion ~less than 1%) for an ampli-tude of duty-ratio excursions lass than Q.l has been achieved with the new power stage of Figure 10, suggesting a very linear DC gain characteristic for a duty ~atio D around ~.5, as seen on Figure 8. However, when the parasitic resis-tances of ~he two inductances are accounted for to model more correctly the finite voltage gain of the power stage, the DC gain characteristic appears to be still further linearized arouncl D = O. 5.

~o assess the nonlinearity of the differential DC gain characteristic _ 17 -~ 11 5~3~7 (Figu-re 8) and its efect upon distortion~ assume that the duty ratio D varies $inusoidally around its ~ero-input operating point D = 005, that is D = Q05 ~ A sin~t ~7) where amplitude A is limited to IAI ~ 0050 Substitution of equation ~7) into equation (5) results in V~A sin~t) = 2 A sinwt V (8) 0.25 A sin ~t g This is a~periodical function o t, and since it is also an odd function, it can be decomposed into odd Fourier series. There~ore, tlle output voltage will contain, besides ~he fundamental Al sin~t, odd ~umbered harmonics.
Thi~ is as should be expected since the push-pull connection, if considered ideally symmetrical, as here, results in the cancellation of even order harmonics.
~y finding the rms value o~ equation ~8) as well as of the first harmonic, the t~tal harmonic distortion can be obtained. Quite complex integrals, however, can be evaluated in the closed form to get the total harmonic distortion analytically as:

Ad = A1 A2 ~1 - 4A2 ~ 9) ~1-4A2)3/4 ~ _ 2A2 ~ ~ ~

Equation ~9) demonstrates that the total harmonic distortion increases very rapidly with increase of amplitude Ao Even though the harmonic distortion will be reduced by an order of magnitude9 or so, when the feedback loop is closed as 2~ shown in Figure 12, it would still be desirable to keep the open-loop distortion fo~ the power stage alone as low as possible. That may be accomplished in prac-tice b~ keeping the amplitude of duty-ratio excursions ~Asin~t) to less than ~olo The open-l~op total harn~onic distortion will then be less than 1%, which - 18 _ by itself i5 considered quite low distortion in an open-loop application. Even with a duty-ratio excursion as high as 002, a total harmonic distortion of

4.36~ may be quite acceptable for some applications.
Although a limitation in amplitude variation to a duty-ratio excur-sions of A less than 0.1 ~or extended to 0.2 as shown later by proper optimiza-tion)~ may at irst look to be quite restrictive, it is not at all so. Namely, ~or duty-ratio excursions~of A equal to ~ol~ a differential DC gain of V/Vg =
Q.~3 is obtained, while for duty-ratio excursions of A equal to 0.12, the DC
gain becomes V/V = 1JO2~ Thus for input power supply voltage Vg = 24 ~,and for dut~-ratio excursions of A equal to 0012, a sinusoidal output voltage of a~plitude slightly over 24 V is obtainedO The comparable switching power ampli-fier based on the buck power stage (Figures 4 and 5) and with the same source ~g = 2~ ~, would have to undergo the full range of the duty ratio excursions of A equal to 0O5 to develop a sinusoidal output voltage of the same magnitude.
Thus, the restricted range of varia*ion of duty-ratio excursions of A due to nonlinear DC gain characteristic of the new power stage (Figures 9 and 10) is largely offset by its higher galn. For example, the slope of ~C gain character-istic evaluated at D = 0O5 is 8 in a new power stage ~Figure 10~ while for the prior art ~Figure 3) it is only ZO Therefore, a 4:1 increase in gain allows pro-2~ portional reduction in duty-ratio excursions needed for a given power levelo ~n fact, the power stage developed has the advantage that it is capable of step-up of i~put voltage for duty-ratio excursions of A greater than ~.12, while the buck power stage Figure 3 has only the stcp-dawn property. Consecluently, the now power stage 1~ can work satisfactorily from lower power supply voltages than the prior art ~Figure 3) for the same load power requirement~
To get a quick estimate for the limited low distortion range defined ~ 19 -3 ~ '7 by duty-ratio excursions of A less than Oo27 equation ~9) is very well approxi-mated by a quadratic ~parabolic) dependence as:
Ad Z
- ~ A (10~

~ he relatively low clistortion ~C4%) given by equation ~10), gives motivation to investigate closer the linearity of the DC gain characteristic and ~ossible means for its further improvementO
Quite low (<1%) harmonic distortion is thus demonstrated for limited duty-ratio excursions ~A~O.l). ~hat suggests a very linear DC gain characte~-i~tic around D - 0.5, as seen on Figure 80 However, when the parasitic resis-tances of the two inductances are~.accounted for to model mvre correctly thefinite voltage gain of the power stage, the DC gain characteristic appear to be still further linearized around D = 0~50 The effect of parasitic resistances RLl and RL2 for coupled inductors Ll and L2 of a power stage converter (Figure 12~ upon the DC voltage gain and efficiency i5 given by V D' ~ - 2 -, g 1 ~ D/D') ~ ~2 D 2 1 ~11) , 1 ~ D'/D) ~ ~2J
~here ~1 R ' '~2 ~~~ C12) and ~ i$ tho load resistance. To optimize the circuit o~' Figure 12, it is only necessary to fincl the parameters al and CY,21 s,uch that the differential DC voltage gain characteristic gi~en by equation ~11) i5 maximally linearized around the - 2~ -3 a ~

operating point D = 0.5. That leads to tne optimality criterion:
~ 7~ 3~ 2~ ~13) Thus, from equation ~13?, for a given ~2~ the optimal value for ~1' can be chosen. ilowever, ~or efficiency reasons ~2 is usually very small ~a2 <~1~, which makes ~1 almos~ insensitive to ~2 and equal to 0.0718 for ~2 '' 1. For an 8-ohm load, ~he optimum vlaue of the parasitic resistance R
of the input inductor Ll is ound to be 0.58 ohms.
~hen ~1 and ~2 are chosel1 to satisfy the optimality criteria just described, the DC gain transfer curve i5 maximally linearized over the widest range of amplitude A as seen on the plot of Figure 1~. The comparison with the ideal DC gain curve ~no parasitics included~, shows almost perfect linearity of the optimal DC gain curve for A ~ 0~2.
A push-pull switching audio amplifier has been optimally designed in the closed-laop arrangement of Figure 12, but in the configu~ation of Figure 15 with parasitic resistors R = 0.53Q, with the capacitor value of 180~F~ and with coupled inductor parameters Ll = 138.S~H and Le Q L2-Ll = 37.5~H.
The npn transistors were GE D~H10 and the pnp transistors were GE D45H10. All 2Q of the switching diodes were IN3883, and additional diodes D3-D6 f type IN91~
were used to couple the output of type D20026 drivers through 11~ resis~ors ~1 and ~2 to the swi~ching transistors and diodes, as shown, in a modification of the Baker clamp to improve the transistor switching times. The circuit was tested with an 8Q resistance for the load R. For the chosen power supply volt-age Vg - 25 V,iand with duty-radio excursions limited to less than 0.1 ~A < 0.1 to keep the open-loop distortion very low~, the maximum output voltage was approximately 25 ~, and roughl~ ~0 ~atts of sinusoidal audio power was obtained.

1 î5~3~7 The ~witching frequency used was f5 - ~0 kHz.
First, several experiments and measurement were performed on the po~-er stage itself, followed by some open-loop DC as well as AC gain measurements.
~he first experiment verified the DC gain characteristic of Figure 14 by direct measurements of the differential output DC voltage vs. the duty-ratio of the power switch. The parasitic resistances of the coupled-inductors were RQl =
RQ2 ~ 0.04 Q, and a characteristic very closely approaching the ideal gain characteristic of Figure 1~ was measured. Then, the resistances of Rp = 0.53~
were added in series with t~e input inductors ~i.e. J added to the parasitic re-sistance of the input inductor~, resulting in the total optimal input resistanceOf Q.57~ very near the theoretical ~ideal) of 0058~ ~or an 8~ load. The lin-earity of the measured DC gain characteristic tremendously improved as was pre-dicted by Figure 14. However, for lower power supply voltage ~Vg = 10 V or smaller~, a deviation from the linear characteristic was observed for low outputVoltages (duty ratios close to 0.5). This has been attributed to transistor saturation voltage and diode forward drops, which were not accounted for in Fig~re 14. At higher output voltages and for higher input supply voltages, their effect ~ecomes negligible, and approaches the optimal linearity curve of Flgure 14.
2U The next experiment measured the overall open-loop DC gain linearity chence including the nonlinearity of the ramp and any other source of non-linear-ity). Still operating in an open-loop 3 a small DC signal input was injected as the audio signal input and the output voltage across the load was measured, re-sulting in the open-loop DC gain characteristi~ of ~igure 16. As seen in Figure lG, relatively good overall linearity was observed. This measurement was~ of course, done with an optimum DC gain characteristic of the power stage, hence ~ = 0.53~ was included.

3 ~ 7 The measurement of the dynamic CAC) small signal frequency res-ponse ~loop-gain) at the steady-state CDC) operating point D = 0O5 was under-taken next. Although a more sophisticated and general signal i.njection method could have been used $or loop gain measurement without breaking the feedback 1OOPJ the relatively low value of the DC loop-gain designed (28 db~ and negli-gible loading effect of the feedback network at the power stage ou-tput per-mitted breaking the feedback loop at th~ outputO The loop-gain T was then measured by injecting an AC signal at the input of the amplifier 23, and mea-suring the AC output differential voltage of the power stage For the first measurement, the externally added resistances Rp =
Q.53 ~ ~ere removed ~shorted)O The measured loop-gain frequency respons0 shown by dotted lines in Figure 17 agreed ~ery well with the theoretically predicted oneO Note from the corresponding minimum phase response in Figure 17 that even with just the small inherent parasitic resistances of the inductorsJ the real zero was indeed in left-half planeO When the same measurement was repeated with near optimum values of input resistances ~0.57 ~), the frequency shown in heavy llne in Figure 17:was measuredO Again, this ~requency response is as predicted . theoretically, namely that an input resistance of RQl = 0.58 ~ leads to a cal-: culated r~al zero fz = 933 Hzo Since the complex poles are no~ appreciably 2Q a$fected by.~inclusion o~ the parasitic resistances Rpl they are approximately at $c M 50Q Hz Therefore, a near cancellation o~ one pole and this zero results, and effectively a single-pole frequency was measured as shown in ~:igure 17 in heavy line Note that the high-frequency pole fp = 34 kHz is close to f5/2 (40 kHz) and has negligible effect upon the.-fr~uency respon~e.
~ hen finally the input voltage Vg was increased to Vg = 25 V again, a slight inc~ease of~the DC loop-gain resulted. The measured loop-gain shown in - 23~--3 ~ 7 Figure 18 had a 0 d~ crossover at exactly 2Q k~lz. ~hus, ~hen the feedbac~-loop ~as closed, the closed-loop gain of 2Q kHz band~idth was measured as shown in Pigure 19. Note that even though the feedback loop is closed without any compensation, a high stability and phase margin of 73 is achieved. The closed-loop gain roll-oXf at low frequencies (2~ Hz) was due to a l~F coupling capaci-tor at the audio signal input ~not sho~n in Figure 12)o In summary, some of the more important advantages of the new switch-ing power amplifier are:
1) A need for a single power supply onlyO
2) Wide range of po~er supply vol-tages from low ~10-lSV) to high CllQ V~ ma~ be used owing to the basic power stageO ~It may therefore ~e oper-ated from lower po~er supply voltages than buck-type for the same output power).
3) No need for an input filter. ~In fact, the current dra~Yn Erom the power source has no ripple for a specified DC reference voltage.) ~ All the transistors in the push-pull arrangement are referenced to ground ~grounded emitter), thus permitting the simplest and easiest ~ay to dri~e them.

5) Use o~` the complementary npn and pnp transistors driven from a single source results in automatic prevention of any overlap in the on state of ~Q the transistors.

6) Very good DC gain linearity ~for optimal design) results in low open-loop distortionO

7) DC isolation feature, although not demonstrated, may be easily introduced, if necessary for certain applications, by direct use of techniques discl~sed in the aEoresaid paper titled ~'Coupled-Inductor and Other ~xtensions o~ a ne~ Optimum ropology S~itching DC-to-DC Converter~'O

~ 15~3~7 ~ hile all these advantages are present with the new converter imple-mentation of Figure 10, the additional ad~antages are gained by the coupled-inductor extension of Figure 12 as follows:
l~ Low output current ripple Cand hence low output voltage ripple), when approaching the matching condition ~n q ~), completely eliminates the need for the output capacitors, thus further reducing complexity and size and weight of the amplifierO Even zero output current ripple may be achieved.
2) Significantly improved loop-gain frequency response permits closing the feedback loop directly with no compensation.
3~ Further reduced complexity ~y use of coupled inductors oll a single core, instead of two cores for two inductors.
4) Nide amplifier bandwidth is achieved without excessive require-ment on switching frequency fs Although particular embodiments of the inventlon have been described and illustrated herein, it is recognized that modifications and equivalents may readily occur to those skilled in this art, particwlarly in the selection of materials. For example VMOS switches may be emplo~ed. Still other alternatives for the implementation of the switches will occur to those s~illed in the art, such as the use of quasi-complementary transistors, npn transistors on both 2Q sides of the storage capacitor with floating drive circuits, or any other arrangement for achieving bidirectional electronic switches, io e~, switches that will allow power flow in both directionsO Conséquently, i* is intended that the claims be interpreted to cover such modifications and equivalents.

, - 25 -

Claims (4)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A DC-to-DC converter capable of bidirectional current flow comprising first and second inductances in series with storage capacitance between the inductances, and bidirectional symmetrical switching means for alternately con-necting the junction between said first inductance and said storage capacitance and the junction between said storage capacitance and said second inductance, to a return current path to a source connected to either of said first and second inductances, said bidirectional symmetrical switching means of said converter being comprised of an npn transistor connecting the junction between said first inductance and said storage capacitance to said return current path to said source, and a first diode connecting the junction between said second inductance and said storage capacitance to said return current path to said source, a pnp transistor connecting the junction between said second inductance and said stor-age capacitance to said return current path to said source, and a second diode connecting the junction between said first inductance and said storage capaci-tance to said return current path, and means for alternately turning said npn and pnp transistors on in a complementary manner-for bidirectional current flow from said source to said load, whereby said first and second inductances can be arbitrarily connected, one to a source of power and the other to a load.

2. A DC-to-DC converter as defined in claim 1 wherein each transistor is connected in a grounded emitter configuration, with their bases connected dir-ectly whereby drive for said transistors of a converter is from a single voltage drive source through a current limiting resistor.

3. A DC-to-DC converter as defined in claim 2 wherein said first and second inductances are coupled on a core, whereby current ripples are reduced in at least one of two currents consisting of a current through said first induc-tor and current through said second inductor.

4. A DC-to-DC converter as. defined in claim 2 wherein said first induc-tor is connected to said source and said second inductor is connected to said load, and said first and second inductors are coupled on a core to form a transformer designed for the condition n = k, where k is the coupling coeffi-cient and n is equal to the square root of the ratio of the self inductances L
and L2 of said first and second inductors, respectively, for zero current ripple through said second inductor.