CA1143858A - Memory refresh for high speed compact digital computer system - Google Patents

Abstract

ABSTRACT

Therein is disclosed high speed, compact computer system architecture. System architecture includes a processor for processing machine language data, a memory for storing at least machine language instructions for use by processor, microinstruc-tion logic for storing and providing sequences of frequently used instructions, and busses for transmitting at least instructions between processor and memory. Microinstruction memory circuitry is disclosed for efficient storage of microinstructions in available microinstruction memory space. Also disclosed is microinstruction selection circuitry for high speed selection of successive micro-instructions of a sequence. Memory control circuitry is disclosed for providing memory refresh during battery back-up operation, preventing loss of user program and data stored in memory.

Description

33~si~3 BACKGR3UND OF I~ rNVENTION
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1. Cross Reference to Related Applications . .
~ he present applica-tion is related, in part, to Canadian Application Serial No. 339,190, "High Speed Digital Computer System", filed November 5, 1979 of common assignee.
m is applica-tion also is a division of Canadian Patent Application Serial No. 340,691 filed November 27, 1979, "High Speed Compact Digi-tal Computer System", of com~on assignee.

2. Field of the Invention mis invention relates to architecture for a high speed, co~pact digital computer system and, more particularly, to d rcuitry used therein to enhance operating speed and efficiency of such a system.

3. escription of Prior Art Basic elements of a digital computer include a prooessor, for processing machine language digital data, and a memory. In genercil, machine language in-structions for controlling prooessing operations of the pro oessor are stored in memory. M~mory may also contain at least portions of data to be processed~ In-structions and data are transmitted between pro oessor and mem~ry by processor output and memory output busses. Frequently used sequen oes of instructions, referred to as microinstruction sequen oes, are stored in a separate microin-struction memory. Certain instructions, referred to as macroinstructions, cause microinstruction menory to provide a oorresponding sequence of microinstructions to prooessor. A co~lputer further includes input~output (I/O) apparatus for transmitting instructions and data between oomputer and external devices. External devi oe s may include, e.g. a control console or a tape storage unit.

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Capability of such a.digital computer is defined, and limited, by its speed and efficiency in processing data and executing instructions. In general, efficient use of available physical hardware space is required to provide maximum computer capability. Computer system capability and hardware efficiency are particularly important in several areas. Among these arleas are computer micro-instruction memory; circuitry for selecting pg/,~

~1 143858 successive microinstructions of microinstruction sequences;
circuitry for periodically re~reshing computer memory; and instruction prefetch circuitry for fetcbi~g a next instruction to be executed from computer memory while a current instruction is being executed. .
Physical hardware space required by microinstruction memory i5 determined by efficiency with which microinstructions are stored therein. ~icroinstruction organlzation is det~rmined by computer function while microinstruction memory physical structure is determined by currently available hardware, E.g.
a micrQinstruction set may comprise two or more separate pages of microinstructions; each page containing 256 48-bit micro-instructions. Prese ffl ly available read only memoxies ~ROMs) ~or storing microinstructions may be structured as 512 word long by 8-bit wide memories. A sinyle page o microinstructions could be implemented with six 512 word by 8-bit ROMs. Storage efficiency, however, would be only 50 percent; microinstruction memory would require twice the physical space re~uired to store an equivalent number o~ bits.
Another limitation of computer capability is time required to select successive microinstructions of a sequence. Circuitxy requixed for such selection should therefore require minimum -hardwara implamentation,and delay,to provide maximum speed of selection.
Yet another limltation of computer capability is circuitry required to refresh computer memory while operating in battery back-up mode~ Although a critical function, this circuitry does not contribute directly to computer capability and should therefore reguire minimum hardware implementation.
Computer operating speed may be enhanced by use of prefetch circuitry to fetch a next instruction to be executed from memory while a c~rrent instruction i5 bein~ executed. Again, this circuitry should require minimum hardware implementation while pro~iding the desired function.

. ..... .. , ' . ' ~ 3~8 The present invention provides computex system improvements which bear upon the above noted computer capability/
hardware eEficiency factors, thus improving speed and efficiency of operation oE the system, and also provides a solution for the aforementioned problems and limitations of prior art as will be discussed in detail hereinbelow.
SUMMARY OF THE INVENTION
The present invention relates to computer system archi-tecture providing increased computer capability and hardware ef-ficiency. The architecture includes a processor for processing machine language data, a memory for storing at least machine languaye instructions for use by processor, microinstruction logic - for storing and providing sequences of frequentl~.used instructions, and busses for transmitting at least instructi.ons between processor and memory. The architecture includes the feature of memory control circuitry providing memory refresh during battery ~ack-up operation.
The parent application of which this is a division describes architecture relating to microinstruction selection circuitry for high speed selection of successive microins-tructions in sequence, thereby increasing speed with which successive micro-instructions may be selected and executed. Thus the invention according to the parent application may be seen as providing a digital computer system-comprising processor means for processing digital data signals and memory means for storing at least in-structions employed by the processor means in controlling the system, microinstruction logic means for controlling the processor means, comprising: microinstruction memory means for storing seg-ments of microinstructions, at least one sequence of the micro-instructions being associated with each one of first certain of the instruction, and means responsive to the each one of the first . .

1438~8 certain of the instructions for sequentially se].ectiny each one of the segments of the each one of the microinstructions of the at least one of the sequences associated with the each one of the first certain of the instructions; and means for (1) se-quentially receiving and storing the each one of the segments of one of the each one of the microinstructions at a time, and (2) providing corresponding control signals for controlling the processor means.
The present invention improves on the prior art by allowing the efficient use of available hardware space in pro-viding computer memory refresh. Thus this invention provides a digital computer system comprising memory means for storing at least instructions for controlling the system, main power supply means for providing electrical power to the memory means, and back-up power supply means for providing power to at least the memory means when a failure occurs in the main power supply means, memory refresh means, comprising: means for measuring successive refresh time intervals; means responsive to operation of the main power supply means and to operation of the measuring means for indicating each one of first certain the time intervals wherein the failure has occurred; and means responsive to operation of the measuring means for providing successive second certain the memory input signals representing refresh addresses, memory address means re-sponsi.ve to operation of the measuring means and to operation of the indicating means (1) during each one of the time intervals other than the first certain the time intervals for (a) receiving and providing the second certain the memory input signals to the memory means, and (2) during the sequence of the first certain the time intervals.for (a) receiving and storing a representation of the second certain the memory input signals occurring during the first ~ . .
~ jr/ ~ - 4 -~3858 and E.irs-t certain the time intervals, (b) successively incrementing the stored representation of the second ce:rtain the memory input signal during successive the first certain the time intervals, and (c) providing the stored and incremented representation of the second certain memory inpu-t signals to the memory means.
Other features and advan1:ages of the presenk invention will be understood by those of ordinary skill in the art, after referring to detailed description of preferred embodiments and drawings wherein:
BRIEF DESCRIPTION OF DRAWINGS
Fig. 1 is a detailed block diagram of a computer in-corporating the present invention;
Fig. 2 is a schematic of computer microinstruction memory;

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Fig. 2A is a schematic of computer microinstruction logic includin~ sequence control circuitry;
Fig. 2B is a schematic of circuitry generating clock signals for use by microinstruction memory and logic circuitry shown in Figs. 2 and 2A;
Fig. 3 is a schematic of computer memory address circuitry;
Fig. 3A is a schematic of computer memory;
Fig. 3B-is a schematic of computer memory control circuitry;
Fig. 4 is a partial block diagram of part of com-puter processor; and, - Fig. 4A is a schematic of instruction prefetch address circuitry.

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1 ¦ DESCRIPTION OF THE PREFERRED EMBODIMENT
¦ The following discussion presents architecture and ¦ operation of a computer incorporating the present invention.
¦ Architecture and operation of the present computer will be 5 ¦ described first on block diagram level. Next, selected portions ¦ o~ the present computex, e.g., microinstruction memory circu-itry memory refresh circuitry, and instruction prefetch circuitry will be described individually, in that order. Finally, certain l features of the present invention will be summarized.
10 ¦ Certain conventions are used throughout the following dis-cussion to enhance clarity of presentation. Where related eircuitry is shown is two or more figures, the figures will share a common figure number with a letter designature, e.g., Fig. 2, 2A_ Common electrical points between such circuitry will be indicated by a bracket enclosing a lead to such a point and a designation "A-b"; ~A" indicates other figures having the same eommon point and ~b~ is a letter designation applied to a particular eommon electrical point. Reference number5 will comprise a two-digit number ~00-99) preceded by the number of the figure in which they appear, e.g., 100 through 199 in Fig.
1, or 400 through 499 in Fig. 4. In the case of related circuitry shown in two or more figures, the figure num~er used vill be that o* first igure of the related group Reference numbers will be assigned in sequence through the related group of figures.
Detailed structure and operation of circuitry presented in the prese~t application will be described only where neces-sary to illustrate operation Conventional circuit symbols are used throughout and structure and operation of circuitry will - 30 be under~tood by one ordinarily skilled in the art~ Only those component-~ necessary to illustrate operation of circuitry will . .
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1 be designated ~y a reference numeral. All components drawn in same manner as thos~ referenced are to be considered identical to, and operating same as, those re~erenced.
1. Computer Architecture and Operation ~Fig. 1) A. Structure Referring to Fig. 1, there is a disclosed a detailed block diagram of computer 110, whose arc~i~ecture incorporates the present invention. Major elements of computer 110 are central processing unit ~CPU) 114, including microinstruction logic 144, memory 124, and input/output ~I/O) interface cir-cuitry 130.
Arithmetic and logic unit (ALU) 112 output in central processin~ t~it ~CPU) 114 is connected to ALU output (ALUOUT) bus 116. ALUOUT bus 116 is connected to scratch pad memory ~SPMEM) 118 data input in CPU 114, and to inputs of data register ~DREG) 120 and address register (AREG) 122 of memory 124. ALUOUT
bus 116 is connected to inputs of universal asynchronous receiver t transmitter ~UART) 126 and data input~output ~DI/O) buffer 128A
in I/O interface circuitry 130.
AREG 122 output is connected to address inputs o~
SPMEM 118 and Console Read Only Memory (ROM) 132 in CPU 114, and to memory multiplexor ~ME~MUX) 134 input. Outputs of DREG 120 and ~æM~UX 134 are connected to, respectively, data and address inputs of memory 124. Memory 124 output is connected to memory output ~MEMOUT) bus 136. Console ROM 132 output is also connect-ed to MEMOUT bus 136. ME~OUT bus 136 is connected to inputs of MEMOUT register ~MEMREG) 138 and instruction register ~IR) 140 - in CPU 114. MEMOUT bus 136 is also connected to start address generator tSAGE) circuit 142 in microinstruction logic 144 of CPU 114.
A first output of I~R 140 ia connected to ME~OUT bus 136, . and to Decode ~OM 146 addre~s input in microinstFuction logic . -6-. . ... ..

~ 858 1 144. A second IR 140 output is connected to microinstruction memory output ~MEMOUT) bus 148 in microinstruction logic 144. A
third output i9 connected to an input of instruction MUX ~INST~UX
150 in CPU 114. Outputs of INSTMUX 150,KEMREG 138, and 5 SPMEM 118 are connected to ALU input ~ALUIN) bus 152. ALUIN
bus 152 in turn is connected to ALU.112 input.
I~ ~icroinst.~uction.logic 144, outputs of SAGE 142, Decode ROM 146, and Microinstruction ~ump ~INSTJ) Buffer 154 are con-nected to microinstruction memory input (F~ENIN) bus 156. ~lMENIN
10 bus 156 is connected to microprogram counter U4~C) register 158 input. ~PC 158 output is connected to microinstruction meMory 160 address input, and microinstruction memory 160 output is connected to p~EMOUT bus 148. ~ME~OUT bus 148 i5 connected to .
inputs of microinstruction register A U~IRA) 162, microinstruc-15 tion register B tp~RB) 164, and ~INSTJ buffer 154. p~RB 164 output is connected to sequence control ~SEQCNTL).166 input.
SEQCNTL 166 outputs are connected to control inputs of SAGE 142, Decode ROM 146, ~NSTJ buffer 154, and PPC 158. ~¢RA 162 output is connected to another input of INSTMUX 150~
In I/O inter~ace circuitry 130, ASCII I/O channel 168 - . is connected between an external ASCII interface device ~not shown for clarity of presentation) and UART 126. UART 126 data ~ . output is connected to ALUIN bus 152. As previously stated, : UART 126 data input is connected from ALUOUT bus 116. Similarly, Data I/O bus 170 is connected from an external data source, ~not shown for clarity of presentation) and Data I/O ~DI/O) buffer 128B input. ~I/O buffer 128B output is connected to ALUIN bus 152. As previously stated, DI/O buffer 128A input is .
: connected Erom ALUOUT bus 116;DIJO buffer 128A output is connect-: 30 ed to Data I/O bus 170.
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; 1 ~43858 1 ¦ ~omputer 110 further includes a main power supply and ¦ a battery b~ckup power supply, neither of which is shown for ¦ clarity of presentation.
¦ B. Operation 5 ¦ Referring ag~in to Fig. 1, a user's program, e.g., data ¦ and microinstructions, are storecl in memory 124 and transferred ¦ to CPU 114 through ~E~OUT bus 136 upon request by CPU 114.
¦ Transfer o~ data/macroinstructions out of memory 124, and the ¦ writing of such into memory 124, are accomplished through ALVOUT
10 ¦ bus 116. Memory 124 read and write addresses are provided from ¦ ALU 112 through ALUOUT bus 116 and stored in AREG 122. Data/
¦ macroinstructions to be written into memory 124 are likewise ¦ provided by ALU 112 and are stored in DREG 120. Data/macroinst-l ructions are provided to memory 124 directly from DREG 120.
15 ¦ Read/Write addresses from AREG 122 are converted to memory 124 ¦ row and column addresses by MEMMUX 124 and provided to memory 124 ¦ _ _ _Data/macroinstructions appearing on MEMOUT bus 136 may be transferred through MEMREG 138 to ALUIN bus 152 for use by A~U
112. In general, macroinstructions appearing on ME~DUT bus 136 20 ¦ are transferred into IR 140. Certain macroinstructions e.~., data, may then be transferred from IR 140 to ALU 112 through INSTMUX 150 and ALUIN bus 152. Frequently used sequenceso~ instructi ~ns referred to as microinstructions, are stored in microinstruction l logic 144, discussed further below. A macroinstruction corres-25 ¦ ponding to such a sequence of microinstructions comprises, in¦ part, an instruction to microinstruction logic 144. Microinstruc ¦ tion logic 144 responds to such a macroinstruction appearing in ~` ¦ IR 140 by providing the corresponding sequence of microinstruc-¦ tions on ~E~OUT bus 148.
30 ¦ Certain portions of microinstructions, as will be ¦ discu~sed further below, may be transferred into ~IRA 162 and to ALUIN bu~ 152 through INSTMUX 150.

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3~5~3 Computer 110, as discussed further below, includes cir~uitry for providing refresh addresses to memory 124, to refresh data/macxoinstructions stored therein. Refresh circuitry comprises, in part, ALU 112, AREG 122, and MEMMUX
134. Also as discussed further below, CPU 114 includes in-struction pre-fetch circuitry. Instruction pré-fetch cir-cuitry allows the next instruction to be executed by CPU 114 to be fetched from memory 124 while a current instruction is being executed.
SPMEM 118 provides temporary storage, e.g., for contents of ALU 112 during an interrupt operation. Data to be stored in SPMEM 118 is provided to SPMEM 118 dat~ input through ALUOUT bus 116. SPMEM 118 read/write addresses are provided from ALU 112 through AREG 122. Data read out of SPMEM 118 aP~ears on' ALUIN bus 152 where it is available for use bv ALU 112.
. Communication between external devices and CPU 114 or memory 124 is provided throuqh I/O interface circuitry 130.
Parallel digital words may be transferred through Data I/O bus 170. DI/O buffers 128A and 128B allow, respectively, data/
macroinstructions to be transferred between ALUOUT but 116 or ALUIN bus 152 and Data I/O bus 170. Transfer of data/
- macroinstructions between Data I/O bus 170 and memory 124 is accomplished through ALU 112.
Serial alphanumeric characters, e.g., in ASCII code, are communicated between CPU 114 and an external device (not ! shown for clarity of presentation) through ASCII IJo bus 168 I and UART 126. As taught in Canadian Patent Application Serial i Number 339,190, Console ROM 132 is an interface device allowing -- g _ .

~43i~S8 any external device having, e.g., an ASCII interfac~, to operate as a computer control console. Console ~OM 132 replaces a majority of hard console switches and lights normally used to control computer 110; computer 110 thereby requires only a small hard console. Console ROM 132 con-tains console program macroinstructions for computer 110 console operation. These include .

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1 examin~tion and modification oE current computer 110 contents, .. bootstrap lo~ding of programs, and execution of test programs.
In oper~tion, predetermined sequences of ext~rnally provided alphanumeric characters are received by CPU 114 through UART
126. Received sequences are then provided as address inputs to Console ROM 132 through ALUOUT bus 116 and AREG 122. Corres-ponding macroinstruction outputs of Console ROM 132 then appear on M~MOUT bus i36 in same manner as macroinstructions provided from memory 124.
Having described structure and operation of computer 110 on block diagram level, structure ancl operation of microinstruction logic 144 will next be described i.n detail.
2. Microinstruction Logic 144 (Figs. 1, 2, 2A, and 2B) ~s described above, microinstruction logic 144 stores frequently used sequencas of microinstructions. A macroinstruc-tion corresponding to such a sequence of microinstruc~ions operates, in part, as an instruction to microinstruction logic 144. Microinstruction logic 144 responds by sequentially pro-viding each microinstruction of the corresponding sequence.
Microinstructions appeàr on pMEMOUT bus 148 and, in part, are transferred into MIRA 162 to be provided to ALU 112 through I~STMUX 150. Other portions of microinstructions provide random control signals to CPU 114 and microinstruction logic 144.
Microinstruction logic 144 structure has been previousl described in describing computer 110 on block diagram level. The following discussion will begin with a description of microin-struction logic 144 operation on block diagram level. Circuitry ........... . ..... . ,. .
used in a presently preferred embodiment of microinstruction logic 144 will then be presented.
A. _ (Fig. 1) Referring again to FigO 1, microinstruction memory 160 stores sequences of microinstructions. Each such sequence corresponds to one or more macroinstructions s~ored, e.g., in ' '-10- ' ; , .' . . .. ... ...

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~3858 : memory 124. Memory 160 may appear to CPU 114 to comprise a 512-word by 4~-bit wide memory, containing up to 512 48-bit microin-structions. Memory 160 may be internally organized as a ~wo-page memory, wherein each page may be organized as a 51~-word by 24-bit wide memory. A memory 1~0 page thereby has su~ficient bit capacity to store one-half the microinstructions contained in memory 160. Each memory 160 page may be 24 bits wide, i.e., one-half of a microinstruction. Each page may then be 512 words long, i.e., twice the number of microinstructions to be stored therein. Each microinstruction may be divided into a first and a second segment; each segment compri~ing 24 bits. First and second segments o a single microinstruction may be sto~ed in consecutive word locations of memory 160. E.g., first segment of microinstruction 24 in memory 160 location 98 and second 15 segment in memory 160 location 49. A single microinstruction . may then be called from memory 160 in two sequential steps.
Access time rate of memory 160 is preferably no more than ~ a CPU 11~ cycle period (e.~., 0.2 microseconds). A single micro-. instruction may therefore be read out o memory 160 within a single CPU 114 cycle. First segment of a microinstruction istransferred intoJ4IRA 162 and may provide instruction ~its and control signals to CPU 114. Second segment of a microinstruction may be transferred into ~IRB 164 to provide control signals for selecting successive microinstructions of a microinstruction sequence. It is understood that other organizations of memory 160, MIRA 162 and MIRB 164 may be used. E.g., memory 160 page may be ~ microinstruction wide and may contain four times as many words as microinstructions to be stored therein. ~n this case, a single microinstruction would comprise four segments stored in fo~r memory 160 locations. There would be four microinstruction register~. The four segments of a microinstruc-tion would be transferred to corresponding microinstruction . .................... .. ., . . . - - -- - --- - - ''''' ' ' -11- ' . .~

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re~isters durlny a single CPU 114 cycle; memory 160 access time would be less than ~ CPU 114 cycle period. Further individual segments of a microinstruction need not be stored in successive memory 160 locations, but, e.g., may be stored in an interleaved fashion. Also, memory 160 may be organized as a single or multiple page memory.
In operation, a macroinstruction corresponding to a particular microinstruction sequence appears on ME~OUT
bus 136 and is transferred into IR 140. In general, a macroinstruction in IR 140 is decoded by Deco~e ROM 146, which provides memory 160 address of the first microinstruc-tion of the corresponding sequence. As taughk in Canadian Patent Application Serial Number 339,190 SAGE 142 IStart Address Generator) may directly decode certain macro-instructions to directly provide memory 160 address of the first microinstruction. SAGE 142 thereby eliminates delay time through IR 140 and Decode ROM 146 and reduces time required to initiate execution of certain sequences. IR
140 output to Decode ROM 146 is also connected to SAGE 142 input from MEMOUT bus 136. In, e.g., event of an interrupt operation, a current macroinstruction may be stored in IR 140.
At conclusion of interrupt, stored macroinstruction may be transferred from IR 140 to MEMOUT bus 136 and SA~E 142 input, for re-initiation of corresponding microinstruction sequence.
This allows a microinstruction sequence to be reinitiated after interruption without requiring a new read cycle from memory 124.

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3~S8 Flrst memor~ 160 microinstruction address appears on UMEMIN bus 156 and is transferred into UPC register 158.
First address is then provided to microinstructibn memory 160 address input. This address, and all sebsequent addresses, selects two memory 160 stroage locations containing first and second segments of the corresponding microinstruction.
A separate address input, descxibed further below, provides an additional address bit to select between first and second locations, i.e., between first pg/~ ~ - 12A - -.
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1 and second segment3. First segment Is selected first and tran~-ferred through ~E~OUT bu3 1~8 to ~IR~ 162. Second segment i5 then selec~ed and tran3~erred through ~r~EMOUT bus 148 to ~IRs 164.
In regard to operation o~ CPU 114, thereEorc, microinstruction 5 memory 160 appears to providea 4~bit microinstruction in one CPU
114 cycle and thus to be 48-bits wide by 512 words long.
Certain bits of first microinstruction seyment in ~IRA
162 may be provided to ~LU 112 through INS$MUX 150 as an instruc-tion word. Other bits of Eirst microinstruction segment may provide random control signals to ALU 112. IR 140 output to p~æ~OUT bus 148 allows certain macroinstruction bits to be used to modify a first tor second) microinstruction se~ment. In such a case, certain microinstruction bits are "blank" ~e.g., default logie 1) and these bits ~e.g., logic O's)provided from IR 140 Second microins~ruction segment in UIRB 164 may be generally used to control selection of successive microinstructions of the sequence. In this regard, certain bits o second ~icroinstruc _ tion segment may specify a condition to be tested by that micro-instruction. Certain other bits provided to SEQCNTL 166 may specify action to be taken, depending upon test regults. There may be four possible actions to betaken. First, to go to a microinstruction specified by a memory 160 address provided by SAGE 142. Second, to go to a microinstruction specified by a memory 160 address provided by Decode ROM 146 Third, to jump 2 to a microinstruction at a memory 160 address provided by UINSTJ
buf~er 154. Fourth, to continue to next successive memory 160 address. First and second actions may be taken, e.g., at a microinstruction sequence branch or to initiate a new micro-instruction sequence. Again, SAGE 142 may be used where it is desirable to rapidly initiate a next microinstruction. Third action is a standard jump operation. In this case, a memory 160 addres~ to be jumped to may be speci~ied bysecond segment bit~ of a following microinstruction, which are transferred onto ... ... _., . ... _.... , . ..

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~3~3 1 ~EMIN bus 156 through ~NSTJ buffer 154. 'rwo successive micro-instructions are therefore required to execute a jump. Condition to be tested is specified in second se~ment of a first micro-instruction. Address jumped to is specified in second segment of a second microinstruction. Jump then occurs at start o a third successive microinstruction. Fourth action occurs when successive microinstructio~s are stored i~ corresponding successiv memory 160 locations. In this case, PPC register 158 operates a counter and an address therein is incremen~ed as each mic~o-instruction is executed.
In summary, p~C register 158 address selects successivepairs of memory 160 locations containing first and second segments of microinstructions. Selection of successive microinstructions is performed by SEQCNTL 166, which decodes certain second micro-instruction segment bits from ~IR B 164. SEQCNTL 166 providesenabling outputs to SAGE 142, Decode ROM 146, ~INSTJ buffer 154 and ~FC register 158.
~ aving described microinstruction logic 144 operation on block diagram level, circuitry used ina presently preferred embodiment of microinstruction logic 144 will be presented next.
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1 B. Microinstruction Logic 144 Circuitry ~Figs. 2, 2A, 2B) Schematics of circuitry used in a pr~erred embodimen~
o microinstr~ction logic 144 is presented in Figs. 2 through 2~, and related to block diagram Fig. 1.
S Referring to Fig. 2, ~C register 158 and microinstruc-tion memory 163 are shown. PFC register 158 comprises four bit counters 200 and 202, and microinstruction memory 160 comprises read only memories tRO~) 204 to 214. ~
Counters 200 and 202 data inputs are connected from U~EMIN bus 156 and counters 200 and 20Z data outputs are connected to address inputs of RQ~s 204 and 214. Counters 200 and 202 parallel coun~ enable inputs are connected toenable signalCONTINUE
from SEQCNTL 166, described ~urther below. An address appearing on pNEMIN bus L56 is loaded into counters 200 and 202 by olock signal BCLK when CONTINUE is logic 0. ~f CoNT~E is logic 1, counters 200 and 202 operate as serial binary counters and an address stored therein is successively incremented by BCLK. As described further below, BCLK is a squarewave clock signal occurring at CPU 114 cycle rate le.g-, 5MHZ). Counters 200 and 202 reset inputs are connected to reset signal RYSNC, which allows contents of counters 200 and 202 to be reset to 0.
Turning to microinstruction memory 160, ROMs 204, 208, and 212 comprise page one of memory 160 while ROMs 206, 210 and 214 comprise page two. ROMs 204 and 206 contain bits 0 to 7 and bits 24 to 31 of, respectively, ~irst and second microinstruc-tion segments. Similarly, ROMs 208 and 210 contain bits 8 to 15 and 32 to 39 while ROMs 212 and 214 contain bits 16 to 23 and 40 to 47. Data outputs of gates 204 and 206 (p~EMOUT 0/24 to 7/31) are wire ORed and connected to Fh~EMOUT bus 148. Similarly, data - 30 outputs o~ ROMs 208 and 210 ~p~EMOUT 8/32 to lS/39) and ROMs 212 and 214 ~MEMOUT 16/40 to 23/47) are, respecti~ely, wire ORed and connected to ~EMOUT bus 14a~ Selectlon between pages one .~ . . `
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11 . .......... . 1, .~ .

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is inverted by gate 21fi and P~ OE SS~SCT provided to enable inputs of ROMs 204, 208, and 212.
Considering page one ~ROMs 204, 208, and 212) or memory 160, each RO~ comprises a S12 woxd eiyht bit wide by memory. ROMS
204, 209, and 212 thereby comprise a 24-bit wide by 512 word long memory. Page 2 is similar to page 1. Each microinstruction ln is divided into two 24-bit segments, which are stored in succes- :
sive locations of page one, i.e., an even address and an odd address. E.g., first segment of microinstruction~2~ is stored in location 24 and second segment stored in location 25. Selection of a single page one address requires nine address bits (29=512). ~PC
register 158 address outputs comprise eight most significant bits of memory 160 address. ~PC register 158 address output is therefor capable o selecting any signal consecutive pair o~ address locations, i.e., a pair of memory 160 locations containing a single microinstruction. Least significant memory 160 address 2a bit is provided by clock signal ACLK. ACLK selects between consecutive memory 160 locations, i.e., between first and second ~ s seqments of a microinstruction. As described further below, ACLK i a sguarewave clock signal at same frequency as BCLR, but is inverte from BCLX. For first half of BCLK period, ACLK is logic 0 and, during the second half of BCLR period, ACLK is logic 1. During a single BCLK period, therefore, ACLR irst selects even address memory 160 location containing first microinstruction ; segment ~bits 0 to 23). ACLK then selects odd address memory 160 location containing second microinstruction segment (bits 24 to 47). First and second microinstruction segments so selecte are thereby sequentially transferred from memory 160 to F~E~O~T
bu~ 148 during a single BCLK cycle.

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~ 43~3S8 Referring to Fig. 2A, MIRA 162, UIRV 164, SEQCNTL 166, ~INSTJ buffer 154, Decode ROM 146, and SAGE 142 are shown. ~IRA
162 comprises six bit registers 218 to 22~, whose data inputs are connected from ~EMOUT bus 148 (~MEMOUT o~2~ to ~3~47).
S Registers 218 to 224 clock inputs are connected to ACLK. ~IRB
lS4 comprises six bit registers 227 to 230, whose data inputs are also connected from MMEMOUT bus 148 (~MEMOUT 0/24 to 13/37, 22/46, 23/47). Registers 226 to 230 clock inputs are connected to BCLK. A first microinstruction segment ~AMEMOUT 0 to 23) appearing on ~MEMOUT bu$ 148 is thereby loaded into ~IR~ 162 by ACLK. Bits 1 to 8 of first microinstruction segment ~p4RA
1 to 8) are provided from registers 222 and 224 to INSTMUX 150 andALU 112 as instruction bits. Bit O ~IRA0] from register 224 is provided to INSTMUX 150 as an enable signal indicatlny ~IRA 1 to 8 are to be transEerred through INSTUMUX 150 to ALUIN
bus 152. Bits 9 to 23 of irst microinstruction segment (~IRA 9 to 23) are provided to ALU 112 as random control signals.
Registers 218 to 224 reset inputs are connected to reset signal R, which allows contents of ~IRA 162 to be reset to 0.
Second microinstruction segment(~E~OUT 24 to 47) appears on AMEM~UT bus 148 after first microinstruction segment and is transferred into ~IRB 164 by BCLR. Registers 226 to 230 reset inputs are connected to RYSCN, which allows ~IRB 164 contents to be reset to 0.
Second microinstruction segment bits MIRB 24 to 28 and 3 3 to 27, are used as random control signals. In part, these bits define test conditions, referred to above, for controlling sequential selection of microinstructions. Bits ~IRB 29 to 32 are provided to gates 232 and 234 of SEQCNTL 166. These bits select, dependent upon test results, which of four posslble actions, described above, is to be taken. Inputs TEST and TEST .
. .

~ 3~

to gates 232 and 234 are enable signals repre~enting test results Gates 232 and 234'outputs are provided to decoder 236 inputs.
Decoder 236 decodes yate 232 and 234 outputs to provide four ena~le signal outputs. As described above, CONTINUE is provlded to counters 200 and 202 of ~PC re~isl:er 158. CONTINUE determineq whether counters 200 and 202 will be p~rallel loaded with an address from M~EMIN bus 156, or whether an address stored therein is So be incremented. ENBJMP is provided to ~INSTJ buffer 154.
ENBJMP enables buffers 238 and 240 to transfer second microins~ru~ ._ tion segment bits ~ EMOUT 38 to 45 of the next microinstruction t ~ME~IN bus 156. Second segment bits 38 to 45 o the next micro-instruction represent a memory 160 address containing a microin-struction to be jumped to. ENBSAGE and ENBDECODE, respectively, enable SA OE 142 and Decode ~OM 146.
~s stated above, second microinstruction segment bit ~IRB 46 is provided to microinstruction memory 160 as selectio~
signal PA,GE SELECT. Each microinstruction therefore contains information identifying whether the next successive microinstruc-tion is located on page 1 or page 2 of memory 160.
2~ ~e~erring to Fig. 2B, circuitry for generating ACLX
and BCLX is'shown. Flip-flops 242 to 246 comprise a divide by eight counter clocked by 40CLK, a 40MHz clock signal. Flip-flop 246 Q and Q outputs are inverted by gates 248 and 250 to provide symmetric and inverted square wave BCLR and ACLK signals. As stated above, BCLR period is CPU 114 cycle period ~5 MHz). ACLK
i8 logic O during first half of BCLK period and logic one during second half of BCLX period. P (Preset) to flip-flops 242 to 246 set inputs allow initial starting condition o~ flip-flops 242 to 246 to be set.
~aving described structure and operation of microinst-ruction logic 144, memory 124 refresh circuitry will be described next.
'., ' ' , -18- , . - ~

, ~ 51~
3. Memory 124 Refresh Circuitry (Figs. 1, 3, 3A, and 3B) A. Memory 124 ~ (Fiy. l) Memory 124 oper~tion will be described first on block diagram level. Memory 124 operation will then be described with aid of schematics showing a presantly preferred embodiment of memory 124, AREG 122, MEMMUX 134 and CPU 114 memory control cir--cuitry.
Referring to Fig. 1, memory 124 may comprise a 32~ word (~= 1024~ by 16 bit memory. Memory 124 may be internally organiz d as two pages, each page containing 128 rows of words by 128 col-~unns of words. A memory 124 read, wxite, or refresh cycle period ~ay be 400 nanoseconds. It is understood that other memory 124 architectures, parameters, and periods may be used. E.q., memory 124 may ~e 24 or 32 bits wide or have different internal organi zation (256 columns by 128 rows). Similarly, memory 124 address format may differ from that shown herein.
As previously described, ALU 112 provides refresh addresses to memory 124 during normal operation. Each refresh cycle refres es an entire row of both paqes of memory 124. Refxesh address may b 2Q stored in an ALU 112 register, and is incremented and provided to memory 124 at predetermin~d refresh intervals (e.g., 12.8 microseconds).
In event of a computer 110 main power supply failure, com-puter 110 battery back-up supply provides power to memory 124 and CPU 114 memory control circuitry, discussed below. Battery back-up supply thereby prevents loss of user program and data stored in memory 124. When a main pow&r supply failure occurs, refresh address is transferred from ALU 112 register to address register 122 and stored therein. CPU 114 memory control cir-cuitry continues to control memory 124 refresh. Refresh addressin address register 122 is incremented at each reresh interval a d provided to memory 124 to refresh successi~e rows of memory 124.

3~S&i B. Memory 124 Circuitr~ (Figs. 3, 3A and 3B) Schematics of circuitry used in a preferred embodiment of memory 124, AREG 122 and MEMMUX 134, and memory control circuitry are shown in, respectively, Figs. 3A, 3 and 3B, and will be discussed in that order.
Referring to Fig. 3A, memory 124 comprises two similar banks 300 and 302 of dynamic MOS RAMs (random access memories).
Each bank contains one-half of memory 124 storage capacity.
Referring to bank 300, bank 300 comprises 16 identical RAMS
301. Each RAM 301 contains a single bit of each wora stored in bank 300, and is internally oryanized as an array of 128 rows by 128 columns.
As taught in co-pending Canadian Patent Application Serial Number 339,190, memory read and write cycles are performed by providing sequential row and column addressed to bank 300 RAMs. In a read cycle, a seven bit row address is first Pro-vided to bank 300 RAM 301 address inputs (AO-A6), accompanied by a row address strobe (RAS) signal. A seven bit column address is t~en provided to bank 300 RAM 301 address inputs, accompanied by a column address strobe ~CAS) siynal. 16 bits of information, representing the addressed word, then appear at bank 300 RAM 301 outputs (DO0 to DO15). Addressed word is transferred through buffer 304 to MEMOUT bus 136 by buffer 304 enable input ENBM. In a write cycle, a word to be written into memory 124 is provided to bank 300 RAM 301 data inputs from data register 120 ~DATAIN 0 to DATAIN 15). Inputs ~, DATAIN 0 to DATAI~ 15 are accompanied by a write enable ~WE) signal to bank 300 RAM 301 write enable inputs.

pg/ ~ ? - 20 ~9t3B58 Read and write cycles to bank 302 are executed in same manner as to bank 300. Selection between banks 300 and 302 is accomplished by providing RAS to either bank 300 or bank 302. RAS is selectively gated with one bit of memory 12~ address from AREG 122~ Banks 300 and 302 will both, therefore, receive .; ' ' " ' ~ ' ' .

p~ 20A - :

'~

' .
;, identical row and column address inputs and C~S inputs. Only one of bank~ 300 or 302 will, however, receive an ~ input. A
A refresh cycle is similar to a read cycle, except only row address and RAS are provided to bank 300 RAMs 301. Refresh is therefore accomplished by executing a partial read operation.
Banks 300 and 302 both receive RAS inputs when executing a refres 1 .
cycle, so that rows of ~oth banks 300 and 302 are refreshed at same time. -Referring to Pig. 3, AREG 122 and ME~MVX 134 are shown. AREG
122 comprises counters 306, 308, register 310, and flip-flop 312.
Data inputs of counters 306 and 308, register 310 and flip-flop 312 are connected from ALUOUT bus 116. Address bits ALUOUT 9 to ALUOUT 15 from ALUOUT bus lL6 comprised row address bits. Bits ALUOUT 2 to ALUOUT 8 comprise column address bits. Address bit ALUOUT 1 is a bank selection bit for selecting either bank 300 or bank 302.
Counters 306 and 308 each comprise a single flip-flop C~),and a group of three flip-flops (B, C, and D) arranged as a . three bit counter. Flip-flop A is connected from data input A, provides output Q1, and is clocked by clock input CLKl. Flip-flops B, C, and D are, respectively, connected from data inputs B, C, and D, provlde outputs Q2, Q3, and Q4, and are clocked by input CLK2. Counter 306 flip-flops A to D and counter 308 flip-flops B to D are connected as a 7 bit counter clocked by signal 30 PFSTART (Power Failure Start). These seven flip-flops receive row address bits ALUOUT 9 to 15 and provide row address outputs ADR 9 to 15. Counter 308 ~lip-flop A and six bit register 310 comprise a seven bit register for receiving colunn address bits ALUO~T 2 to 8 and pxoviding column address outputs ADR 2 to 8.
Flip-flop 312 receives address bit ALUOUT i and provides outputs ADRl and A-~ for selectively enabling R~S to bank 300 or to ., ' ' . ' ~ 8~1~
bank 302. Reset inputs of counters 306 and 30a and register 310 are provided, respectiv~ly, with reset sign~ls TESTRESET and R.
These reset inputs allow row and column address bits to be reset to 0.
In normal operation, a read, write, or refresh address from ALU 112 is transferred into AREG 122 by load enablc signal ENBMAD
(Enable Memory Address). Row address bits ADR 9 to lS from counters 306 and 308 are provided to inputs of row address gates 314 in MEMMUX 134. Likewise, column address bits ADR 2 to 8 are - 10 provided to inputs of column address gates 316. Bank select bit ADR 1 and ADR r are provided to inputs of, respectively, gates 318 and 320. Gates 314 row enable input signal ROW first becomes active to transfer row address bits ADR 9 to 15 through gates 314 (R0-R6~ and OR gates 322 (A0-A6) to banks 300 and 302 RAM address inputs. RAS to gates 318 and 320 then occurs. Either bank 300 o bank 302 receives RAS input, as d~termined by gates 318 and 320 enable input signals ADRl and A-~r. ROW terminates after RAS
occurs, and gate 316 column enable input signal COL becomes active. Column address bits ADR 2 to 8 are transferred through gates 31~ (C0-C6) and 322 (A0-A6~ to bank 300 and 302 RAM address inputs. CAS to gates 324 and 326 then occurs, and banks 300 and 302 receive CAS inputs. Gates 324 and 326 provide separate CAS
inputs to, respectively, banks 300 and 302 to reduce loading on these gates. COL is terminated ater occurrence of CAS, and memory 124 cycle is completea. WE is provided to ~anks 300 and 302 through gate9 328 and 330 during a write cycle in same ~anner as CAS.
As described above, a re~resh cycle during normal opèration comprises a partial read cycle. Refresh address stored in an ALU
112 register is transferred onto ALUOUT bus 116. Refresh addres , however, comprises only seven bits o~ Row address information, i.e., ALUOUT 9 to 15. ALUOUT 9.to 15 are transferred into counters 306 ancl 308 to appear as ADR 9 to 15. Gate 33~ concur-., ' .
. . ~_..... ... , , ' .
. . - - -- ~
..

. . .

~43~ 3 rently receives input signal REFRESH and provides signal ICAS
(Inhibit Column Address Strobe). ICAS inhibits gates 32~, 326, 328, and 330, thereby inhibiting CAS and WE to banks 300 and 302 of memory 124. ~ is provided to flip-flop 312 set and reset inputs, thereby forcing ADRl and ADRl to logic 1. ROW input to gates 114 then transfers row address bits ADR 9 to 15 through gates 314 (R0-R6) and 322 (A0-A6) to banks 300 and 302 address inputs. RAS input to gates 318 and 320, as enabled by ADRl and ADRr,then provides RAS to both bank 300 and bank 302. ROW is terminated after occurrence of RAS. COL may then be allowed to occur but, as just described, ICAS inhibits banks 300 and 302 CAS inputs. Refresh cycle is then complete and a single row of banks 300 and 302 has been refreshed by executing a partial read cycle.
~5 Memory 124 refresh cycle during battery back-up operation is similar to that jus~ described, except refresh address is not provided from ALU 112. ~emory control circuitry, described further below, senses an impending failure of power from computer 110 main power supply. Refresh address is transferred from ALU 112 register to counters 306 and 308 by ENBMAD. Input signal PWROFF (Power Off) to gate 332 generates ICAS to inhibit CAS and WE, and to force ADRl and ADRl to logic 1, for duration of computer 110 main power failure. Thereafter, memory control circuitry provides signal PFSTART to counters 306 and 308 during each refresh cycle (e.g.; for 400 nanoseconds every 12.8 microseconds). In this mode, counters 306 and 308 a~er~t~. a ..
counters rather than registers, and refresh address is therebY
incremented by PFSTART at end of èach refresh cycle. Durinq PFSTART, ROW and RAS are provided to banks 300 and 302 as de-3a scribed above, as are refresh address bits ADR 9 to 15. CAS 3ndWE are aqain inhibited. Successive rows of memory 124 are thereb r refreshed durinq PFSTART at each s~ccessive refresh interval.

, .
COL input to ~ates 316 is preferably dri~en to logic 1, and input ROW to gates 314 driven to logic 0, excep-t when executing a refresh cycle. Also, register 310, containiny colurnn address information, is preferably provided with power from computer llO
main power supply. Register 310 is thus turned off during batter~ , back-up operation. Resisters 334 then provide logic 1 column address bits ~DR 2 to 7 to gates 316 during battery back-up operation. Except during reresh cycles, therefore, gates 314 outputs are lo~ic 1, gates 316 outputs are logic 0, and - 10 gates 322 outputs are logic 1. This reduces memory 124, ME~NUX
134, and AREG 122 power consumption during battery back-up operation when re~resh cycles are not being executed.
At conclusion of battery back-up operation, computer 110 resumes normal operation. Computer 110 then preferably executes lS a burst refresh subroutine wherein all rows of memory 124 are successively refreshed. Computer llO then resumes normal o~era-tion refresh of memory 124 as described above.
Referring to Fig. 3B, memory control circuitry is sho~n.
Flip-flops 336 to 344 comprise a five bit shift register pro-viding memory control signals ROW, RAS, COL, and CAS.
Gates 346, 348, and 350 provide a logic 1 to flip-flop 336 3 input when a memory read, write, or refresh cycle is to be ex~cuted. Specifically, gate 346 pro~ides a logic 1 when input INSTSAGEALC (Instruction, SAGE, Arithmetic and Logic Class) from ~5 SAGE 142 indicates tha~ instruction on ME~OUT bus 136 calls ~or a memory read or write operation. Gate 348 provides a logic 1 when input signal ~IRB27 from RIRB 164 indicates a microin-struction calling for a memory read or write cycle. Input signal TSTART (Test Start) to gate 350 initiates memory 124 read and 3~ write cycles during computer llO test sequences. In normal operation, memory refresh cycles are initiated as a interrupt operation. A counter (not shown for clarity of presentation) .

~3~
provides ~ re~resh int~rrUpt signal every 12 . E~ microseco~d.s.
corresponding microinstruction sequence provicle5 a corresponding ~IRB27 input to initiate a memory 124 refresh cycle as described above.
At start of a memory cycle, ROW is logic 1 and COL, RAS, and CAS are logic 0. Flip-flop 336 J input is s~mpled by clock input 5CLX (5 MHz clock) so that flip-flop 336 Q and Q outputs provide 200 nanosecond M~MSTART and MEMSTART (Memory Start) pulses at start o~ each memory cycle. Shift register flip-flops 338 to 344 are clocked by 40CLK (40 MHZ clock) and sample flip-flop 336 MEMSTART output~ Appearance of ME~START thereby causes a logic l to propagate from flip-flop 338 to flip-flop 344. RAS
thereby becomes logic l at first 40CLK pulse and remains so until MEMSTART returns to logic 0. Two 40CLK clock pulses later, COL
becomes logic 1 and ROW becomes logic 0. CAS becomes logic 1 one ~OCLX period after COL becomes logic l. MEMSTART then terminates on ne~t SCLK pulse. End of MEMSTART is detected by gate 352.
loc~R (lO MHz,clock) input of gate 352 samples gate 352 ~EMSTART
input. Gate 352 provides K inputs to flip-flops 338, 340, and 342 to insure flip-flops 338, 340, and 342 are reset ~i.e., Q
outputs are logic O) at end of MEMSTART. lOCLR likewise samples ENDMEM (End Memory Cycle) input of gate 354, which providesflip-flop 344 R input. ENDME~ indicates end oE a memory cycle and insures flip-flop 344 Q output is reset to logic O at end of a - 25 memory cycle. Signals P (Preset) and TESTRESET to set and reset inputs of flip-flops 336 to 340, 344, 356, and 360 (discussed b~low) allow memory 124 control circuitry to be set and reset (e.g., on computer 110 start-up~.
Flip-flop 356 and gate 358 comprise circuit~y indicating imminent failure of computer llO power from computer 110 main power supply. Plip-flop 356 data input signal PWROK (Power OK) from computer l:LO main power supply indicates pending occurrence ..., ' ' , " ...

. : .

- ~1~3~
of such a failure. PWRO~ i5 sarnpled by flip-flop 356 cloc~ input signal REFRESH. R~RESil occurs at start of each normal operation refresh cycle and is provided from refresh microinstruction sequence described above. Flip-flop 356 thereby samples computer 110 main power supply condition during each normal operation refresh cycle. If PWROR indicates a main power supply failure is imminent, flip-flop 356 Q output provides PWROFF (Power O~f~
indicating a pending failure. PWROFF is inverted by gate 35~ to provide P~ROFF. PWROFF and PWROFF are provided to, respectively, gates 346 and 348 to inhibit INSTSAGE~LC ,an,d ~IRB27; PWROFF , :
thereby prevents false triggering of memory cycles duirng batter~
back-up operation.
, Generation of memory control signals ROW, RAS, COI., and CAS during battery back-up operation is controlled by flip-flop 360. Flip-flop 360 provides output signals PFSTART and PFSTART.
During normal operation, PWROFF through OR gate 362 to flip-flop 360 reset input forces PFSTART to be logic 1 and PFSTART to be logic 0. During battery back-up operation, flip-flop 360 data inDut ~EM~IGH (Memory ~igh, a logic 1) is sampled by flip-flop 360 clock input signal REFRQ (Refresh Request). REFREQ is pro-v~ded from a clock circuit (not shown for clarity of presenta-tion~ and occurs at memory 124 refresh intervals ~12.8 micro-seconds~. Each REFRQ causes PFSTART to become logic 1 and PFSTART to,become logic 0. P~START is provided, as described 2~ above, to address register 122 counter 306 clock input.
. .. .... ... .... ... . . . ................ ... ....... .
~FSTA~T is,,provided to gate 350 input to initiate generation of memory control sig-nals ROW and RAS dur1ng refresh cy,cle.~LE~START and ROW are conne~ :ed to inputs of gate 364, which provides a flip-flop 360 reset input signal through gate 362. Gate 364 reset signal terminates PFS-TART when ROW goes to logic 0 during refresh cycle; flip-flop 360 is thereby reset in preparation for next reresh cycle. PFSTART

.' '`'~"-''.' "', ' ~3L438SI~

is also provided to an input of gate 366, whose output is con-nected to flip-flop 342 set input. During normal operation, PWROFF to gate 366 forces gate 366 output to logic 1. Flip-~lop 342 may therefore operate as described above to generate memory control signals during normal operation. In battery back-up operation, PFSTART forces gate 366 output to logic 0 except during refresh cycles. Flip-flop 342 is thereby forced to set condition, with COL logic 1 and ROW logic O. As described above, this forces MEMMUX 134 and memary 124 into reduced power state when refresh cycles are not being executed. Flip-flop 342 set input is released by PFSTART at start of a battery back-up refresh cycle. Flip-flop 342 is then reset by R input from gate 35Z, so tha~ COL is logic O and ROW is logic 1, as required at start of refresh cycle.
Description of memory 124 and memory 124 control circuitry structure and operation is hereby completed, and computer 110 prefetch circuitry will be described next.

. -` ~3858

4. C puter 110 Pre-Fetch Circuitry (Figs. 1, 4, and 4A) Referring to Fig. 1, as previously discussed a sequence of maeroinstructions comprising a user's program is generally stored in memory 124. CPU 114, as descri~ed further below, tracks pro-gram execu~ion by storing memory 124 address of theinstruction currently being executed by CPU 114. This address is referred to as current program count ~CPC). CPC is incre-mented as sueeessive macroinstructions are called from memory 124 and executed. CPC may be usad during eurrent instruetion exeeu-tion, e.g., to generate a memory 124 address relative to CPC.
Computer 110 pre-feteh eireuitry allows the next instruetion to be exeeuted by CPU 114 to be ~etehed from memory 124 while a eurrent instruetion is being exeeuted. To aeeomplish this, ALU
112 generates and provides a next program count (NPC) representin lS memory 124 address of next instruction to be exeeuted by CPU 114.
Referring to ~ig. 4, a partial block diagram of ALU 112 bit slice 400 is shown. Each such bit slice 400 may be capable of performing eight arithmetie and logie operations on four binary bits of information. ALU 112 may eomprise four sueh bit sliees 40Q eonnected in parallel. Eaeh bit slice 400 includes random aeeess memory (RAM) 402, which comprises 16 separately address-able registers. Address inputs A0 to A3 and B0 to B3 allow any two of sixteen registers to be selected as, respectively, A and -B registers. Contents of A and B registers so selected appear, respeetively, at data outputs A and B. Souree selector 404 may then select RAM 402 data outputs A and B, or any of three other ~ata sourees, to be eonnected to data inputs R and S of arith-metic and logie unit 406. Other data sources inelude external data input D0 to D3, Logic 0 407,and register 408 output. ALU
3Q 406 may perform any of eight possible arithmetic and logic operations on data inputs R and S to provide output F. Output seleetor 410 may then seleet elther ALU 406 output F or RAM

.
.~

. ..
'` ;.
' . ' , .
.

' ,, 1~ 1143~58 array 402 data output A to appear as bit slice 400 output Y0 t~
Y3. ALU 406 output F may be transferred into RAM 402 register, through RAM shift register 412, or into register 408. Regis-ter 408 output may be bit shifted, by shift register 416, and trans-ferred back into register 408 input. Four bit slices 400 of ALU 112 thereby enable ALU 112 ~o perorm any of eight arithmatic and logic operations on 16 binary bits of information. In parti-cular, ALU 112 thereby contains 16 16-bit registers.
Two ALU 112 registers are dedicated to storing CPC and NPC.
In operation, assuming CPC is stored a first register and NPC in a second register, second register can be selected as register A. NPC then appears on ALUOUT bus 116. NPC may thèn be used to address memory 124 to cause next macroinstruction to appear on MEMOUT bus 136. Next macroinstruction is then trans-ferred into IR 140. At start of execution of next macroinstruc-tion, NPC becomes CPC of that next macroinstruction and a new NPC must be generated. old NPC remains in second register to become new CPC, and is also read from second register into ALU
406 through-source selector 404. Old NPC is then incremented to generate new NPC, which is transferred from ABU 406 output F to first register to be new NPC.
First and second registers thereby alternately contain NPC
and CPC with each successive macroinstruction. In each case, old NPC becomes-new CPC. Amount by which old NPC is incremented to generate new NPC is determined by memory 124 address of next macroinstruction. If macroinstructions are being called from sequen ial memory 124 addresses, each old NPC is incremented by one to generate new NPC. Old NPC may he incremented hy more than one, e.g., where new memory 124 address is determinad by a skip or jump, or is an indirect address.
Referring to Fig. 4A, circuitry for generating address input A0 to A3 and B0 to B3 to bit slices 400 of ALU 112 is shown. .

-29- , ' ... ., ..... .. , ' ' .
.
~. . .

:~ ~ ~

First and second registers are preferably selected so their addresses differ in only one bit. E.g., first register may have binary address 1011 and second register binary address 1111;
their addresses differ then only in bit 2. Circuitry for seIec-ting either of first or second registers is thereby simplified~
RAM 402 address bits A0, B0, Al, B1, A3, and B3 are not a functio of which of first and second registers contains NPC or CPC.
These RAM 402 address inputs are therefore provided by random logic comprising multiplexors 418 and 420 and gates 422 and 424.
This logic is determined by specific bits from IR 140, ~IRA 162, and ~IRB 164 used to address RAMs 402 of ALU 112. This logic is therefore a specific function of a particular microinstruction set and will not be discussed further; design of such logic is well known to those of ordinary skill in the art. Gates 426 to 432 generate RAM 400 address bits A2 and B2 and are similarly a function of specific microinstruction set. Gates 426 and 428, however, have input signal SELPC (Select PC) which indicates whether NPC is în first or second register. As described above, either first or second register may be selected as register A or register B. When first or second register is so selected, SELPC
determines whether register address bit 2 is one or zero. SELPC
is provided from flip-flop 434 Q output. Flip-flop 434 Q output is connected to flip-flop 434 data input, so that SELPC is alternately one and 0 as flip-flop 434 is clocked by input signal CLKIR (Clock Instruction Register). CLRIR is a clock signal to IR 140 to load macroin-~tructions from MEMOUT bus 136 into IR 140. SELPC therefore alternates between logic 1 and logic 0 as successive macroinstructions are loaded into IR 140.
SELPC then represents whether NPC, which is alternately present in first and second registers, is in ~irst register or second register . . .

.

...... .. ........ ~ ...... ' , : ; .

. .

~3~31 Discussion of computer llO pre-fetch circuitry structure and operation is hereby concluded. ~aving described s-tructure and operation of microinstruction logic 144, memory 124 and memory 124 control circuitry, and computer llO pre-fetch circuitry, S certain features of computer 110 will be summarized next.

. :-- '' ' .
- ' .
....

~3~

5. Summary of Computer 110 Features .
Certain features of computer 110, which features and others were described above, are:
Pirst, division of microinstructions into microinstruction segments, storage of such segments in microinstruction memory i60, _ _ _ provision of a separate microinstruc-tion register for eaeh such se~nent of a microinstruction, an~
sequential transfer of mieroinstruction segments into microin-st~uetion registers to effectivel~ assemble a complete microin-struetion. ~icroinstructions may thereby be efficiently packedinto microinstxuction memory 160 physical structure by time multiplexing memory 160 physical address space. Microinstruction organization is thereby tailored to match memory 160 physical structure. In general, eaeh microinstruction may be divided into an integer number N of microinstruetion segments. Width of each segment is equal to or less than width of a single memory 160 storage loeation. Memory 160 length is preferably at least N
times the number of microinstructions to be stored therein.
~ieroinstruction segments are preferably stored in memory 160 in a predetermined order to simplify addressing. There may be a separate microinstruction register for each segment of a micro-instruction. Individual segments eomprising a microinstruction ar~ time sequentially transferred from memory 160 to microin-struction registers in predetermined order. Transfer of microin-struetion segments may preferably be performed within a singleCP~ eyele; memory 160 aecess time is therefore preferably less than 1 ~ time~ CPU eycle perio~.
Seeond, use of eertain mieroinstruction segments to provide eontrol signals for seleeting suceessive microinstructions of a microinstruetion sequence. This simplifies circuitry required ~or selecting successive mieroinstructions. Time required to select successive microinstructions is thereby reduced. This .
__.__ _ _........ .._ __. _ ... ___ __ _ .... .. _.. ..... .
...... .. ................ _ .. .. . .. . . __ .. ___ . __ . .. _.. _ .. . _ .. .. .. . . .
,. ... ..~ --- ~ ' ' ' . ~.

..

- : ~L~4~

allo~s greater flexibility in organizing memory 160 and microin-structions, as described above, and increases speed of microin-struction execution.
Third, use of dual mode (counters/re~isters) storage devices in address register (AREG) 122. Generation of memory 124 refresh addresses may there~y be transferred from ALU 112 to AREG 122 when computer 110 enters battery back-up operation. This simplifies circuitry required to maintain memory 124 refresh during battery back-up operation.
A fourth feature is use of dual ALU 112 registers to con-currently store a current program count (CPC) and a neY.t program count (NPC). A next instruction to be executed may thereby be fetched from memory 124 by NPC, while CPC may be used in execu~
ting a current instruction. Time required to execute successive înstructions is thereby reduced and circuitry required to perform instruction pre-fetch is simplified.
Description of a preferred embodiment of the present inven-tion is hereby concluded. The invention may be embodied in yet other specific forms without departing from the spirit or essen-tial characteristics thereo. E.g., microinstruction memory 160m2y vary in length and width and may have other internal organi-zations. For example, memory 160 may be twelve bits wide and 1,024 words long and organiæed as a single page memoryr Similarly, each microinstruction may contain, e.g., 56 or 16 bits 2 and may be differently segmented. Segments of a single microin struction need not be stored in successive memory 160 locations but, for example, may be stored therein in an interleaved manner. Likewise, memory 124 may be of different capacity and may be differently organized and addressed. Memory 124 may use 3 different control signals and sequences than those shown herein, and other arrangements of memory address register 122 may be used. Further, pre-fetch registers for storing current and new ~ 3~3~8 program counts~may be separate from, rather than part of, ALU 112 Li~ewise, increm~nting. of NPC and CPC may be performed by cir-cuitry other than bit slices 400 of ALU 112. Thus, the present embodiments are to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes ~hich come within the meaning and range of equi-. valency of the claims are therefore intended to be embracedtherein.

Claims (2)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A digital computer system comprising processor means for processing digital data signals; memory means including a plurality of storage locations for storing at least instructions employed by said processor means in controlling said system;
processor output bus means for conducting memory input signals from said processor means to said memory means; main power supply means for providing electrical power to said processor means and said memory means; back-up power supply means for providing power to at least said memory means when a failure occurs in said main power supply means; and memory refresh means comprising:
means for measuring successive refresh time intervals;
means responsive to operation of said main power supply means and to operation of said measuring means for indicating each one of a sequence of first certain said time intervals wherein said failure has occurred in said main power supply means;
means responsive to operation of said measuring means for providing successive second certain said memory input signals re-presenting successive third certain said memory means storage lo-cations at least one said second certain memory input signals oc-curring during each one of said time intervals; and memory address means responsive to operation of said measuring means and to operation of said indicating means (1) during each one of said time intervals other than said first certain said time intervals for (a) receiving and storing representations of said each one of said second certain said memory input signals, and (b) providing said stored representations of said second certain said memory input signals to said memory means for refreshing corresponding said third certain said memory means storage locations, and (2) during said sequence of said first certain said time intervals for (a) receiving and storing a representation of said second certain said memory input signals occurring during the first said first certain said time interval of said sequence, (b) successively incrementing said stored re-presentation of said second certain said memory input signals during each said first certain said time interval following said first said certain time interval of said sequence, and (c) providing said stored and incremented re-presentation of said second certain memory input signals to said memory means for refreshing corresponding said third certain said storage locations.

2. In a digital computer system comprising memory means for storing at least instructions for controlling said system, main power supply means for providing electrical power to said memory means, and back-up power supply means for providing power to at least said memory means when a failure occurs in said main power supply means, memory refresh means, comprising:
means for measuring successive refresh time intervals;
means responsive to operation of said main power supply means and to operation of said measuring means for indicating each one of first certain said time intervals wherein said failure has occurred; and means responsive to operation of said measuring means for providing successive second certain said memory input signals re-presenting refresh addresses, memory address means resposive to operation of said measuring means and to operation of said indicating means (1) during each one of said time intervals other than said first. certain said time intervals for (a) receiving and providing said second certain said memory input signals to said memory means, and (2) during said sequence of said first certain said time intervals for (a) receiving and storing a representation of said second certain said memory input signals occurring during the first said first certain said time interval, (b) successively incrementing said stored representation of said second certain said memory input signal during successive said first certain said time intervals, and (c) providing said stored and incremented representation of said second certain memory input signals to said memory means.