CA1132715A - Electronic counter with non-volatile memory - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

The specification relates to a volatile electronic counter wherein the count is retained over power off periods.
More specifically, the specification describes a memory system comprising a first electronic counter connected to receive input data for producing address and data signals, a memory coupled to receive the address signals and having data terminals, condition responsive means for selectively producing read and write signals for controlling the memory to apply stored data to the data terminals and to store data therein applied to the data terminals. The system further comprises a variable rate clock means connected to be enabled in response to the read and write signals for enabling the first counter to store counts read out of the memory at a first rate and to be enabled in response to the write signals for applying data signals to the data terminals at a second rate substantially slower than the first rate.

Description

~his is a Divisional application of C~nadiarl a~,pl:icati~Jn ~22,463 filed February 28, 1979 Il BACKGROUND OF THE INVENTTON

'l Many indusl,rial systernFJ require counters at various stages therein for retaining a count of operations performed.
Il These counters are often mechanical or electrornechanical in i nature and have the disadvantage of being unreliable, costly, I and bulky. However, they have the advantage of retaining a l count during periods of electrical shutdown or power outages.
!I Electronic counters with optical readouts would often be pref-',¦ erable for the reasons that they are highly reliable, relatively inexpensive, and much smaller in size. Such counters include ,1 a memory and a visual readout display. The memories are ! "volatile" which means that they function only so long as ,I po~er is on and data is lost when power is off. This makes Ii them undesirable for any use in which a count must be maintained j over such power out periods.
It is a primary object of the present invention to ¦ provide a system which combines the advantages of both types of counter but avoids their disadvantages. The manner in which this and other objects are achieved will be more apparent from the foll wing description and appended claims.

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~Z7 ~ t SUM~Y OF T~IE _NVE,NrrION
Apparatus Eor re-taining the count of a vola-tile memory during periocls of power loss. ~ non-volatile memory is provided. There is :Lnc]uded means which is responsive to the onset of a power loss for thereupon transferrlng the count from the volatile to the non-volatile memory. Means are also pxovided which are responsive to power resumption for thereupon retransferring the count from the non-volatile to the volatile memory.
In accordance with the present invention there is provided a memory system comprising a first electronic counter connected ~o receive input data for producing address and data signals, a memory coupled to receive the address signals and having data terminals, condition responsive means for selectively producing read and write signals for controlling the memory to apply stored data to the data terminals and to store data therein applied to the data terminals. The system further comprises a variable rate clock means connected to be enabled in response to the read and write signals for enabling the first counter to store counts read out of the memory at a first rate and to be enabled in response to the write signals for applying data signals to the data terminals at a second rate substantially slower than the first rate.

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'! a co~lnter in accordance ~ h ~he preserl~ invcntion;
I¦ FIG. 2 illustrates the rcla~iollship o~ tt)c various ¦l shects of drawinc~s (1~ ~ lL~ inc]uslvc) comprlsin~3 rI~7~ 1; and ~¦ FIGS~ 3 - 6 arc tlrnin~ d;agrarns i~ilus~ratin~ the 1l operation of the coun-er of the invention.

i! i)EscllrprrIoN OF ~ IE p~EFr:R~ED EMBODII~ENT
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i~ With power on, the circuit of this inventlon operates ~ as a conventional electeonic counter with strobed ~CD output.

Ij However when power is disconnected or 108t, a special detection ¦, and control circuit causes the data contained in the counter ¦! to ~e trans~erred to the memory and therea~ter retained. When j; power is restored, the data is automatically transferred back ,i to the counter.

¦¦ The circuit requires only 95-130 V~C 60 Hz at about !¦ o 1 amp ~or operation. Input count is a 15-20 M~ current i' ' .

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1~3'~715 1 ,I pulse whict-l i5 optica]ly coupled to thc counter circuitry.

2 1I There are clght output lines driverl hy CMOS 40r,0 t)uf~er drlvers.

3 ll ~our lines contain ~CD data and ~hc oth~r four are digit ~tcobe

4 j'lines which indicate ~Ihich digits data is on the ~(-D lines.
! With particular reference to FIG. 1, there is 6 ,lillustrated a circuit in accordance with this invention. The 7 major elements of the circuit comprise a power supply lû
8 ~ which is supplied by a transformer 12 having secondary windings 9 14a, 14b to supply +5, -12, and -28 volts to the remainder of llthe circuit. Other elements of the circuit include: power on 11 circuit 16, 16a, 16b; power down circuit 18; memory enabling 12 circuit 2û; memory circuit 21; mode selector 22, 22a; com-13 Iparator 24; counter and display driver 26; display 28; input 14 l'circuit 30; dual frequency oscillator 32; manual set control 34;
!Idivider and distributor 36; test circuits 38a, 38b; and out-16 Iput 40. It is believed that the circuit can be best understood 17 ll by reference to the drawings coupled with an explanation of its 18 ,actual functioning. For a complete understanding of the inven-19 i tion, the various circuit elements have been assigned reference ldesiqnations and are described in the following table:
21 ~ Reference Designation Description 22 ;i U101 4 Digit Ctr/Display Driver 23 !; (General Instrument AY 4007A) 24 ' U102 CMOS Quad 2-in NAND schmitt Triggers 25 li E3203, U214 CMOS Dual-D Fl-Fl 26 l, U104 Hi Volt/Current Darlington Drivers 2 !¦U105 CMOS 4-Bit Mag Comparator !¦U106, U216 CMOS Quad Bilateral SW
!i Ul03~ u2ol~ u2o2~
29 1 U204, U215, U217 CMO7 Quaù 2-in NAND Gate .~ I . ., 1~
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' : ' 1~L3~715 ¦IReference Desl~lnation Desc-r-l)t--o-rl 2 ~!U206 CMOS ll-3X Invert:er 3 1¦U208, U207 CMOS ~uzld 2-in O~ Gate 11U209 CMOS Quad 2-in NOR Gate ~¦U210 CMOS Trip]e 3-ir NAND Gate 6 !lU211, ll213 CMOS Decade Ctr/Driver 7 U212 CMOS Quad 2-in AND Gate U218 MNOS 512 Bit Alterable ~ead Only Memory 9 1U219, U220 CMOS Hex Buffer 10 ' The operation of the circuit of the invention in its 11 ~I various modes will now be described.
12 ~~ COUNT MODE
13 ll In this mode, the counter functions in the usual 14 li manner to keep and display a count.
15 1i The non-volatile memory counter is incremented by 16 l a 20 milliamp current pulse to input circuit 30. An optical 17 il coupler 42 transmits this pulse to gate 44 and, if enabled by 18 ~I signal CS over line 46, this gate passes the count pulse to 19 I gate 48. The enabling signal CS will be present provided no 20 1I mode other than "count" is present. Gate 48 acts as an "OR"
21 il gate so that a "0" on any one of its three normally high inputs 22 ~ will cause a count to pass to the counter 50. Counter and 23 ll display driver 26, which includes counter 50, provides all the 24 `I necessary logic and drive to present four decades of digital 25 1i data to the display 28 which includes four seven segment 26 ,, numerical elements 52a-d. The outputs of counter 50, supplied 27 i through resistors 54a g~ provide segment drive to the display 28 1 28, slhile the outputs of counter 50 which connect to the 29 Darlington drivcrs 56 provide diglt drive.

113~i''15 1 l In the COUNq~ mo~e an internal oscillator in counter 2 l, sn causes data to be strobcd to the display at a rate of from 3 ,1 1 Kll~ to 4 K~l~. This strobillg sequencr-s from the most signif-4 Il icant to the least significant d~git. ~rhut is, strohc ]ir,e ]o3 goeis to a "1" (1o2, lol, and ~U0 at "o") which turns on its 6 ' associated D~rlington driver which~ in turn, enables rlumerical 7 element 52d. The data on the seven segment lines from counter ,. .
8 50 are now displayed by element 52d for a time of about 500 9 microseconds. During this time the other three digits are "OFF".
1 Next, strobe line 102 goes to a "1" (103, lol, 10 at "o")~ the 11 seven segment data has changed to reflect the value of the 12 hundreds count in counter 50, nurnerical element 52c is enabled, 13 ' and the other three digits are off. This sequence of strobing 14 continues with 101, then 10 and back to 103 etc. at the 1-4 KHz rate as long as the COUNT mode is in operation.
16 , In addition to seven segment data being strobed to 17 ', the display, BCD data (2, 1, 22, 23) is also strobed to the 18 output 40, which may be connected to an external device such 19 ; as a printer or data collection device.
WRITE MODE
21 In this mode, a loss of power causes a displayed 22 count to be rapidly "written" into a non-volatile memory.
23 This mode is initiated by a loss of AC line power for 24 ; a period in excess of about 30 milliseconds. nence, either a i momentary power loss or complete loss will trigger the control 26 circuitry. Power down circuit 18, detects a powet loss directly 27 li at the secondary 14a of the transformer 12 via diodes 58a and 28 1 58b, divider resistors 60 and 62, and capacitor 64. The 29 j;

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i 'I capacitor ci~alge i5 maintained at a level above ~ "0" ~,uch 2 1l that when currcnt cecl~;es to flow i.nto it ~rorn the secorldary of 3 1l transforrner 12 through diodes 58a, 58~, and resistor 60, capac-4 1¦ itor 64 discharges through resistor 62, hs a re.sult of the KC
1I time constant, a "0~l is applied to gate 66 after about 30

6 li milliseconds o~ power loss. The output of gate 66 goes to

7 ll a "1" which turns on transistor 68, very quickl~ discharging

8 ! capacitor 7û and thereby conditioning the "power on" circuit

9 ,, 16 in the event that power loss is momentary.
1, The "1" from gate 66 is also applied to gate 72 11 enabling that gate so that at the next 1û2 digit strobe signal 12 ~i it receives, its output to gate 74 will go to a "0". Since 13 , the other pin of gate 74 is at a "1'l (controlled by the time 14 jl constant of a resistor 76 - capacitor 78 combination) this 1 will cause the output of gate 74 to go from a "0" to a "1".
16 ,I This transition is differentiated by capacitor 8û and a "1"
17 iI pulse is generated, which is coupled through gates 82, 84, 86, 18 .l 88 to reset pins of flip flops 90, 92 in the mode select 19 ij circuit 22. This causes the two "Q" outputs of the flip flops .j , . I
2û !~ to go to "0". These are connected to the Cl, C2 inputs of a 21 ~I memory chip 94. "0's" on both these inputs condition the 22 i~ memory for a "write data" operation. In addition, the Q
23 ,l outputs of flip flops 90, 92, through gates 95 and 114 and 24 ,I transistor 97, disable the display 28 to conserve power.
25 , CS is the "chip select" input of the mernory 94 and 26 jl it must be high to enable the device for any data transfer, 27 l' CS is high at this time since it is derived from fl.ip flops 28 ,1 90, and 92 via gates 95, 96, 98, lû0, and 102 (in Memory 29 Ij Enable Circui.t 20). One pin of gate 102 receives a "1" frorn 30 j output "Ol- of a flip flop 104 set at "power on". This allows ."

~' 1' 113;~715 1 ~! the output of gatc 102 to go to a "1" when a "1" is receivcd 2 ~¦ from 9ate 100.
3 1¦ The normal output rom counter 50 has a freguen(y ~
4 ¦1 approximately lKII~. This is much faster than memory 94 car ll handle. Accordingly, the CS output of gate U206 a]so enables 6 i¦ the dual frequency oscillator 32 via line 46 and gate 106 while 7 ll disabling the input circuit 30 through gate 44. Tn addition, 8 ll a switch 108 in oscillator 32 is put into its low impedance 9 ,~ state in either the WRITE or ER~SE mode as decoded by gate 1l 114 ~in Mode Select 22) and switched by gate 116. This causes 11 1l a capacitor 110 to become part of the active oscillator cir-12 ¦I cuitry in parallel with a capacitor 112, resulting in low 13 iI frequency (about 200 llz) oscillations. The CS signal also 14 ¦ causes a switch 118 in divider 36 to become low impedance I which stops the internal oscillator of counter 50 through its 16 I "DSC" pin allowing the external oscillator to override the 17 ~ internal one.
18 ` A counter 120 in divider and distribution circuit 19 1l 36 divideg the osciltator frequency by 10 and provides ¦! separation of control signals. The "0" pin of counter 120 21 ¦' is the ~n~ count and it is used to clock the digit select 22 ¦~, clock (DSC) pin of counter 50. After thus selecting the next 23 ¦¦ digit, the "2" pin output of counter 120, twhich in the READ
24 ll mode causes counter 50 to count via gate 122 and gate 48), is inhibited by a switch 124 controlled through a gate 126.
26 ii The BCD data present at the output of counter 50 is 27 ! now switched to the B inputs of a comparator 128 in comparator 28 ¦ circuit 24 and to the inputs of memory 94 through switches 29 ! 130 a-d which are "on" in either the WRITE or ERASE modes.
11 _7_ i' Since idcntical data i:; then pr~scnt at the A and B inputs of 2 ¦ comparator 128, the compari~orl is true and the "equal" output 3 ll qoes to a "1". This enabl~s a courltet 134.
4 I When the count in counter l20 reachc~ 4, th~ "4"
output goes to a "1", but this signal is only functional in the ., 6 PEAL) mode. It is inhibited by gate 132 and melllory 94 during 7 ~ WRITE and ERASE.
8 When the count in counter 120 reaches 6, the "6"
9 output goes to a "1" and is gated via gate 132 to counter 134.
. Since the "enable" input of counter 134 is connected to the 11 "equal" output of the comparator 128, via inverter 136, the 12 count is allowed to increment counter 134. As counter 120 13 . continues to cycle, each "0" selects a ne~J digit in counter 14 50 and each "6" advances counter 134. When counter 134 reaches .I the count of 4, its "4" output goes to a "1" which is gated 16 ~~ to the clock inputs of flip flops 90 and 92 thr~ugh a gate 138.
17 I This clocking causes both flip flops 90 and 92 to toggle (since 18 ' Q is connected to D) and each Q goes to a "1".
19 At this time all four digits of data have been written into the memory 94. The four bits of each digit are 21 l located in four memory locations (4 bits per location). The I .
22 ,: memory locations are selected by decodi.ng the digit strobe 23 . outputs 103, 102, 101, lno Of counter 50 througEl gates 140 and 24 142. Thus as the four different digits are selected, four , unique address codes are presented at A0 and A]: on memory 94.
26 ,. The data out of counter 50 which is switched to the B inputs of 27 1l comparator 128 is also connected to the data inputs of memory 28 ¦l 94 and as the digit strobes sequence through the four digits 29 1! (approx 50 milliseconds per digit) each digit change results !
li 113;~715 1 1¦ in a differen~ address for each of the four melr,ory locatiorls.
2 ¦¦ Aft~r flip Llopg 90, 92 tO(J~te, "C'S" return3 to a "0" ~uttir~y 3 j memory 94 in standby, a "saLe" statc in wtlic:h to remairl while 4 !¦ power is 9Oing down, t l¦ READ MOD~ f ~I In this mode, power resumption causcs the count stored 7 l~ in the non-volatile memory to be "read" back into the display.
8 When power is reapplied to the primary of transforrner 9 " 12, capacitor 70 in the "power on" circuit 16, begins to charge. ¦
l When the Zener voltage of diode 144 is reached, transistor 146 11 ,I begins conduction which turns off transistor 148. The "1"
12 jj which then appears on the collector of transistor 148 is dif-13 Ij ferentiated by capacitor 150, and the resulting "1" pulse 14 ~ is the "power on" pulse. This pulse occurs some 30n-40n milli-¦I seconds after the primary circuit is energized.
16 ll To be sure that no transition states affect memory 94 17 ! as voltage is being established, flip flop 104 (in Memory 18 l' Enable Circuit 20) is held reset by circuit 16b. This insures 19 li a "n" CS signal to memory 94 until subsequently, the "power il on" pulse changes it to a "1". Power on also causes the "~"
21 output of flip flop 92 to go to a "1" by a direct set through 22 gates 152 and 154. Similarly, the "Q" output of flip flop 90 23 1 goes to a "0" by a direct reset through gate 86. Thus Cl 24 i and C2 of memory 94 are at "1" and "0" respectively, which is the read mode for memory 94.
26 l, The oscillator 32 is enabled through gate 106 and, 27 1¦ since this is the READ mode, switch 108 is "off" or in its 28 1I high impedance state which establishes the high frequency 29 , 30 ~ _9_ !
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113;~715 1 ¦l oscillation mo(1e of the otici~la-or. ~.lso, switches ]30 a--(7 are 2 l~ "off" so that thc A and U inputs to c~m~)ar.ltor ~28 are connected 3 I to the count~r 50 and Lt)e memor~ 94 reopectiJely. 1'hc 4 1, functioning of the counter 120 in divider circuit 36, the , oscillator 32, counter 134, and counter 50 is now similar to 6 that o[ the WI~TE mode, except that comparaLor 128 has dif-7 ' ferent inputs, the oscillator is fastcr (50K-lOOK l~z) anc1 the 8 "2" count whictl was inhibited in Wl?I~I~E is now gated throuqh gate 9 122 which also has an input connected to the 10 output of counter 50. Thus, the "2" count incrementci counter 50 at 11 ~ every 10 strobe time. In this manner, four digit strobes 12 occur or every count up pulse to counter 50. This arrangement 13 allows a digit or digit comparison between the counter 50 14 and memory 94. Counter 134 is reset each 10 strobe titne i' and is incremented at each equality of A's and B's in comparator 16 ,I 128, at the count of "6" from the counter 120 in divider 36.
17 , Since counter 134 is reset at every 10 strobe time, it must 18 , "see" four consecutive equalities from eomparator 128 before ¦ !
19 1 its "4" output goes to a "1". This will only occur when the , four digit number present in eounter 50 is equal to the four 21 ~ digit number stored in memory 94 from the previous WRITE cycle.
22 When there is such an equality, both of the flip flops 90, 23 , 92 are toggled by this "1" through gate 138. This causes the 24 'I l~n~ outputs of flip flops 92 and 90 to change to ~In~
i respectively, which eonditions the memory for an ERASE eyele. .
26 il ERASE MODE
27 ll During the ERASE time counter 134 is inhibited feom 28 ¦¦ reset via gate 9fi, inverter 156, gate 132, inverter 158, and 2g ~1 - 10 -1l1 ' ", . . '~p.
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1 ,~gate 160, hence thc count o~ ~our is retuined (from thc preceding 2 ¦! RE~D). Th~ oscillator 32 i5 set to its ~ow freguancy modo 3 ¦las it was Eot WRI~l'l'. Counter 50 is inhibite~d f:r~"~l counting, 4 1l and switchcs 130 a-d are turned on so that thc "A" inputs are !I connected to the "B" inputs of comparatvr l28, as in WRIq'E.
6 1l Thus the memory 9~ will now be cycled through its four addresses 7 i (by ttle decoding of strohe lines with gates 140, 142). 8ecause 8 ,of the "on" condition of switches 130, each of the four strobe 9 times will result in an equality in comparator 128 and counter . 10 , 134 will continue to count up from four through the same 11 j qating as in WRITE. After the fourth strobe time counter 134 12 will reach the count of eight which puts a "1" on gate 152 13 ;'and on the "S" input of flip flop 92, changing its "Q" output 14 ~(Cl) to a "1". Since the "Q" output of flip flop 90 (C2) was jlalready at a "1" the system is now returned to the COUNT mode, 16 ,11 ready to function as a normal counter.
17 ! IEST MODE
lB The purpose of this mode is to enable a service 19 , person to check the system in a static mode; it has no affect ;on any of the operating modes.
21 When switch 162 in test circuit 38b is changed from 22 , "RUN" to "TEST", switch 118 in divider circuit 36 is turned on 23 , through gate 164. This stops the internal oscillator of counter 24 , 50 and, since ttle external oscillator is off (assuming the COUNT
mode), the display strobing ceases at whatever digit was on when 26 'I the switch was changed. Thus a single digit is displayed and 27 1 static BCD and strobe data appears at the output 40. To change 28 ~j the static data, the digit select switch 166 in test circuit 38a 29 It is actuated. This causes the next digit to be displayed and li !l -11 .

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¦ ncw ~lCD (1clta appcclrs on thc output. 'l~his mar)~ l digit 2 I selcct is accomplishcd through rJate ]6f3 and switch llB, 3 I to the digit select clocl; Ir)sc) input of cour)ter S().
4 ~I ~IANUAL SE'I'_MODE
~¦ The display 28 may be sct ~narlually to a E~articu1ar 6 number hy means of our push button s,litci)es in ~hc manual 7 set circuit 34. The direction of count is normally up. ~low-8 ever, actuation of DOWN switch 170 will cause thc count g ! Airection to be reversed. This is useful during initial setting. ¦
l A FAST switch 172 will cause counter 50 to operate at a high ll ~, rate by overriding its internal oscillator. A SLOW switch 12 .~ 174 causes counter 50 to count at a slow rate and will normally 13 I be utili~ed after the fast switch or if the count is to be 14 ,~ changed by relatively few numbers. A SINGIE switch 176 will jl advance or decrement counter 50, one count by each actuation.

17 ~ As a further aid in understanding the operation of 18 ; this invention, reference is made to the timing charts of 19 FIGS. 3 ~ 6. These illustrate, respectively, the wave forms ,' and timing of the COUNT, WRITE, R~AD, and ERASE modes. As 21 thesc charts merely illustrate functions already described in 22 detai], it is believed that they will be self explanatory to 23 1, those skilled in the art.
24 'I It is believed that it will be obvious to those 'i skilled in the art that all the objectives of this invention 26 l~ have been achieved by the circuitry dcscribed above. It 27 I will also be apparent that a number of variations and modi~i-28 ,I cations may be made therein without departing from the spirit 30 ll - 12 -il I .

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1 ~i and scope o~ the invcntion. Accordingly, the foregoing is 2 j, to be construed as illustrativc on].y, rathcr th~n limiting.
3 I! This invcntion is limited only by the scope of the following 4 1¦ claims.
Certain aspects,of the invention disclosed herein are also dlsclosed and claimed in Canadian application Serial Number 322,463.

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Claims (5)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A memory system comprising a first electronic counter connected to receive input data for producing address and data signals, a memory coupled to receive said address signals and having data terminals, condition responsive means for selectively producing read and write signals for controlling said memory to apply stored data to said data terminals and to store data therein applied to said data terminals, a variable rate clock means connected to be enabled in response to said read and write signals for enabling said first counter to store counts read out of said memory at a first rate and to be enabled in response to said write signals for applying data signals to said data terminals at a second rate substantially slower than said first rate.

2. The memory system of claim 1 further including a multi-digit display coupled to receive address and data signals from said first counter, said first counter having an internal clock for stepping said address signals at a third rate different than said first and second rates for effecting display of data on said display means.

3. The memory system of claim 1 further comprising a second counter, means stepping said second counter at rates determined by said clock means, and means responsive to determined counts of said second counter for resetting said condition responsive means.

4. The memory system of claim 3 further comprising means responsive to equality of the count of said first electronic counter and data stored in determined addresses of said memory for stepping said second counter in response to said write signals.

5. The memory system of claim 1 where in said first counter is a volatile counter and said memory is a non-volatile memory, said condition responsive means being coupled to be responsive to operating voltages applied to said system.