CA1130409A - Half-duplex/simplex digital signal converter - Google Patents
Half-duplex/simplex digital signal converterInfo
- Publication number
- CA1130409A CA1130409A CA365,432A CA365432A CA1130409A CA 1130409 A CA1130409 A CA 1130409A CA 365432 A CA365432 A CA 365432A CA 1130409 A CA1130409 A CA 1130409A
- Authority
- CA
- Canada
- Prior art keywords
- simplex
- line
- duplex
- signal
- nand gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
- H04L5/16—Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/20—Repeater circuits; Relay circuits
- H04L25/22—Repeaters for converting two wires to four wires; Repeaters for converting single current to double current
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Power Engineering (AREA)
- Bidirectional Digital Transmission (AREA)
Abstract
HALF-DUPLEX/SIMPLEX DIGITAL SIGNAL CONVERTER
Abstract A solid state circuit, which serves as a twin simplex/
half-duplex converter, includes a triple input NAND gate.
The output of the NAND gate is connected directly to the outgoing simplex conductor. Signals on the incoming simplex conductor are applied to the three inputs of the NAND gate through separate signal paths which introduce different delays. One signal path introduces an interme-diate delay before applying the incoming signal to the NAND gate in an inverted form. The half-duplex line is connected to this signal path. While incoming signals are applied at all three inputs to the NAND gate as well as to the half-duplex line, a lack of coincidence at the inputs prevents any incoming signal from passing through the converter to the outgoing simplex line.
Abstract A solid state circuit, which serves as a twin simplex/
half-duplex converter, includes a triple input NAND gate.
The output of the NAND gate is connected directly to the outgoing simplex conductor. Signals on the incoming simplex conductor are applied to the three inputs of the NAND gate through separate signal paths which introduce different delays. One signal path introduces an interme-diate delay before applying the incoming signal to the NAND gate in an inverted form. The half-duplex line is connected to this signal path. While incoming signals are applied at all three inputs to the NAND gate as well as to the half-duplex line, a lack of coincidence at the inputs prevents any incoming signal from passing through the converter to the outgoing simplex line.
Description
~:~3~ 9 HALF-DUPLEX/SIMPLEX DIGITAL SIGNAL CONVERTER
Technical Field The present invention relates to signal converters and more particularly to a circuit which provides an interface between a half-duplex data path and a simplex data path.
Prior Art Digital data is commonly transmitted within data communication systems or data processing systems over cables or conductor pairs in a half-duplex mode of opera-tion. In a half-duplex mode, data can be transmitted in either direction over a cable but only at different times. Where the data is to be transmitted via optical fibers or where repeater amplifiers are required, the digital signals are normally converted to simplex sig-nals. In a simplex mode of operation, the data is trans-mitted over one conductor and is received over another independent conductor.
Where the signals are being transmitted in elec-trical form, the conversion between half-duplex and simplex modes of operation is conventionally carried out with special transformers known as hybrid trans-formers. There are a number of drawbacks to hybrid ~13~`~C~
transformers. They are relatively expensive and require special mounting and circuit connections. Moreover, they have a limited bandwidth which causes any signal transmitted through them to be degraded or distorted. Finally, they basically perform a signal-splitting function in which 50%
of the power o an incoming signal is lost.
Where data is being transmitted in optical form, a beam splitter is normally used to convert the signals between half-duplex and simplex modes. Beam splitters are open to the same types of objections as hybrid transformers. Beam splitters are expensive, must be specially mounted and aligned and cause a 50% loss in signal strength.
Summary of the Invention The present invention is a simple, inexpensive cir-cuit which serves as an interface between a pair of conductors over which data is transmitted and received in a simplex mode and a single conductor over which data is transmitted and received in a half-duplex mode.
The circuit includes a multiple input coincidence gate which has a first input connected directly to a receiving simplex line and its output connected to a transmitting simplex line. The receiving simplex line is also connected to the coincidence gate through parallel first and second time delay circuits. The first time delay circuit causes a received simplex signal to be applied to the gate after a first delay period. The second time delay causes a received simplex signal to be applied to the gate in an inverted form after a second, shorter delay. The half-duplex line is connec-ted to the second time delay circuit at a point at whichany received simplex signal appears in its normal form.
1~3~40~
Brief Description of the Drawings While the Specification concludes with Claims particularly pointing out and distinctly claiming that which is regarded as the present invention, details of a preferred embodiment of the invention may be more readily ascertained from the following detailed description when read in conjunction with the accompanying drawings, wherein:
Figure 1 is a schematic diagram of a data com-munications system including a half-duplex/simplex digital signal converter circuit constructed in accordance with the present invention;
Figure 2 illustrates the waveforms which are generated at various points or nodes when a single data pulse is received at the converter circuit from an incoming simplex line; and Figure 3 illustrates waveforms which are generated at the same nodes when a single data pulse is applied to the converter circuit over the half-duplex line from an associated unit.
Detailed Description Figure 1 represents a generalized data communication system including first and second data transmitting and receiving units 10 and 12 at opposite ends of a data channel 14 including a pair of conventional optical fibers 50 and 56. No particular type of device is intended to be represented by units 10 and 12. Each unit may be any elec-tronic device capable of transmitting and receiving digital data in a half-duplex mode over one or more input/output conductors. At unit 10, data is transmitted and received in a half-duplex mode over a conductor 16. At unit 12, conductor 18 carries digital data in a half-duplex mode.
~13~4~1~
Data unit 10 is connected to the channel 14 through a half-duplex/simplex digital signal converter circuit 20 and an electrical/optical signal converter circuit 22. Data unit 12 is similarly connected to the channel 14 through a half-duplex/simplex signal converter circuit 24 and an electrical/optical signal converter system 26, each of which is identical to its counterpart circuit 20 or 22.
The signal converter circuit 20 includes a triple input NAND gate 28 having an output simplex line 30 which carries outgoing signals originating within data unit 10. A first input 32 to the NAND gate 28 is connected directly to an input or receiving simplex line 34. A
second input 36 is connected to the input line 34 through a first time delay circuit consisting of four serially-connected inverters 38A, 38B, 38C and 38D. The third input 40 to NAND gate 28 is connected to the input line 34 through a second time delay circuit which includes inverters 42A, 42B and 42C. The half-duplex line 16 is connected to the second time delay circuit at a point between the output of inverter 42B and the input of inverter 42C.
Where the channel 14 consists of optical fibers, the simplex lines 30 and 34 must be connected to electro op-tical transducers. Suitable transducer circuits are shown within the dotted outline 22. For purposes of illustration, it is arbitrarily assumed that an incoming light pulse pro-duces a negative-going electrical signal on line 34 while an outgoing negative signal on line 30 produces a light pulse on optical fiber 50.
The output line 30 may be connected directly to the base terminal of a transistor 46 which serves as 41~
a switch for a light emitting diode or LED 48. If line 30 carries a low level signal, transistor 46 conducts, causing the energized LED 48 to emit light which is directed to the optical fiber 50 in the channel 14. Correspondingly, when line 30 carries a high logic level signal, transistor 46 is switched off to de-energize the LED 48.
The incoming simplex line 34 is connected at the collector junction of a phototransistor 52. When the incoming optical signal is high (i.e., light is being transmitted, phototransistor 52 conducts to pull the line 34 toward ground. When no optical signal is presented over the incoming optical fiber 56, phototran-sistor 52 is non-conductive, allowing line 34 to rise toward the voltage provided by a positive voltage source.
Generally speaking, the circuit described above operates in the following manner to provide half-duplex/
simplex digital signal conversion. While incoming digital signals received on line 34 are applied to all three inputs of the NAND gate 28, different delays are in-troduced at the three inputs. Also, an inverted form of the signal is applied at one of the inputs. As a result, there is a lack of coincidence which prevents any incoming signal from being transferred through the gate 28 to the output line 30. On the other hand, when data unit 10 is transmitting, any signal provided over half-duplex line 16 is isolated from the incoming simplex line 34 by the high reverse impedance of the inverter 42B. Any signal appearing on half-duplex line 16 is transmitted through the inverter 42C and the NAND gate 28 so as to appear in its normal, but delayed, form at line 30.
While data unit 10 is transmitting, the other two inputs to NAND gate 28 will be at high logic levels, causing the NAND
gate output to follow the signals appearing on line 16.
il~r4~
Figure 2 shows the voltages which exist at various points or nodes in the clrcuit 20. Each of the nodes is identified by an upper case alphabetic character in Figure 1. More specifically, node A is the incoming simplex line 34, node B is input 36 to NAND gate 28, node C is input line 40, node D is half-duplex line 16 and node E is the output line 30 from NAND gate 28. Prior to an arbitrarily se-lected time To~ it is assumed that the receiving optical fiber 56 is transmitting no light; that is, no optical signal.
If a light pulse arrives at time To~ phototransistor 52 is driven into its conductive state causing the voltage at node A to drop from a positive potential to or near ground level. The negative going pulse is applied directly to NAND
gate 28 over line 32.
The inverter 42A delays and inverts the negative going signal on node A. The inverter 42B further delays and re-inverts the incoming signal so that it appears at node D in its normal form at a time Tl. The same signal is also propa-gated through inverter 42C where it is further delayed andagain inverted. Because an odd number of inversion operations are performed, the signal which appears on node C at a time T2 is high or inverted relative to the signal appearing on node A. The low-level signal on node A prevents any switch in NAND gate output when node C
goes high.
The incoming negative-going signal which is propagated through the time delay circuit including inverters 38A, 38B, 30 38C and 38D finally reaches node B at a time T3. The out-put of the NAND gate 28 remains high since both nodes A and B are then low.
When the incoming negative going pulse ends at a time T4, the signals on nodes A, B and C switch in the same time sequence but in opposite directions That is, the signal at node A immediately goes high, the signal at node 4~)~
C goes low at a time T6 after being delayed by each of the three inverters 42A, 42s, 42C in the siynal chain, and the signal at node B finally goes high at time T7 after being inverted by each of the four serially-connected inverters 38A-38D.
The output of NAND gate is held at its high level be-tween times T4 and T6 by the low level signal at node B.
The signal on node C returns to its normal low level at time T6 to hold the NAND gate output at the high level even when nodes A and B are both high after time T7.
Referring to Figure 3, when data unit 10 is trans-mitting, a negative going pulse is applied to the circuit 20 over the half-duplex line 16. This pulse is inverted by inverter 42B before being applied to the NAND gate 28. The high reverse impedances of NAND gate 44 and 42A isolates the incoming line 34 during transmission. Since the signals at nodes A and B remain at their normal high levels, the output of the NAND gate 28 is switched as a function of the signals appearing at the output of inverter 42B. NAND
gate 28 also acts as an inverter causing a delayed nega-tive-going pulse to be applied to the base of transistor 46. Thus, the only difference between signals appearing at nodes D and E is that the latter signals are delayed relative to the former.
It should be apparent that the electro optical converter circuit 22 is required only because communica-tions link 14 utilizes optical fibers. If the communicationslink were an electrical one, the incoming and outgoing sim-plex lines 34 and 30, respectively, would be tied directly or through repeater amplifiers to the half-duplex/simplex signal converter circuit.
While there has been described what is considered to be a preferred embodiment of the invention, variations and modifications therein will occur to those skilled in ~3~4(19 the art once they become acquainted with the basic con-cepts of the invention. Therefore, it is intended that the appended claims shall be construed to include both the preferred embodiment and all such variations and modifications as fall within the true spirit and scope of the invention.
Technical Field The present invention relates to signal converters and more particularly to a circuit which provides an interface between a half-duplex data path and a simplex data path.
Prior Art Digital data is commonly transmitted within data communication systems or data processing systems over cables or conductor pairs in a half-duplex mode of opera-tion. In a half-duplex mode, data can be transmitted in either direction over a cable but only at different times. Where the data is to be transmitted via optical fibers or where repeater amplifiers are required, the digital signals are normally converted to simplex sig-nals. In a simplex mode of operation, the data is trans-mitted over one conductor and is received over another independent conductor.
Where the signals are being transmitted in elec-trical form, the conversion between half-duplex and simplex modes of operation is conventionally carried out with special transformers known as hybrid trans-formers. There are a number of drawbacks to hybrid ~13~`~C~
transformers. They are relatively expensive and require special mounting and circuit connections. Moreover, they have a limited bandwidth which causes any signal transmitted through them to be degraded or distorted. Finally, they basically perform a signal-splitting function in which 50%
of the power o an incoming signal is lost.
Where data is being transmitted in optical form, a beam splitter is normally used to convert the signals between half-duplex and simplex modes. Beam splitters are open to the same types of objections as hybrid transformers. Beam splitters are expensive, must be specially mounted and aligned and cause a 50% loss in signal strength.
Summary of the Invention The present invention is a simple, inexpensive cir-cuit which serves as an interface between a pair of conductors over which data is transmitted and received in a simplex mode and a single conductor over which data is transmitted and received in a half-duplex mode.
The circuit includes a multiple input coincidence gate which has a first input connected directly to a receiving simplex line and its output connected to a transmitting simplex line. The receiving simplex line is also connected to the coincidence gate through parallel first and second time delay circuits. The first time delay circuit causes a received simplex signal to be applied to the gate after a first delay period. The second time delay causes a received simplex signal to be applied to the gate in an inverted form after a second, shorter delay. The half-duplex line is connec-ted to the second time delay circuit at a point at whichany received simplex signal appears in its normal form.
1~3~40~
Brief Description of the Drawings While the Specification concludes with Claims particularly pointing out and distinctly claiming that which is regarded as the present invention, details of a preferred embodiment of the invention may be more readily ascertained from the following detailed description when read in conjunction with the accompanying drawings, wherein:
Figure 1 is a schematic diagram of a data com-munications system including a half-duplex/simplex digital signal converter circuit constructed in accordance with the present invention;
Figure 2 illustrates the waveforms which are generated at various points or nodes when a single data pulse is received at the converter circuit from an incoming simplex line; and Figure 3 illustrates waveforms which are generated at the same nodes when a single data pulse is applied to the converter circuit over the half-duplex line from an associated unit.
Detailed Description Figure 1 represents a generalized data communication system including first and second data transmitting and receiving units 10 and 12 at opposite ends of a data channel 14 including a pair of conventional optical fibers 50 and 56. No particular type of device is intended to be represented by units 10 and 12. Each unit may be any elec-tronic device capable of transmitting and receiving digital data in a half-duplex mode over one or more input/output conductors. At unit 10, data is transmitted and received in a half-duplex mode over a conductor 16. At unit 12, conductor 18 carries digital data in a half-duplex mode.
~13~4~1~
Data unit 10 is connected to the channel 14 through a half-duplex/simplex digital signal converter circuit 20 and an electrical/optical signal converter circuit 22. Data unit 12 is similarly connected to the channel 14 through a half-duplex/simplex signal converter circuit 24 and an electrical/optical signal converter system 26, each of which is identical to its counterpart circuit 20 or 22.
The signal converter circuit 20 includes a triple input NAND gate 28 having an output simplex line 30 which carries outgoing signals originating within data unit 10. A first input 32 to the NAND gate 28 is connected directly to an input or receiving simplex line 34. A
second input 36 is connected to the input line 34 through a first time delay circuit consisting of four serially-connected inverters 38A, 38B, 38C and 38D. The third input 40 to NAND gate 28 is connected to the input line 34 through a second time delay circuit which includes inverters 42A, 42B and 42C. The half-duplex line 16 is connected to the second time delay circuit at a point between the output of inverter 42B and the input of inverter 42C.
Where the channel 14 consists of optical fibers, the simplex lines 30 and 34 must be connected to electro op-tical transducers. Suitable transducer circuits are shown within the dotted outline 22. For purposes of illustration, it is arbitrarily assumed that an incoming light pulse pro-duces a negative-going electrical signal on line 34 while an outgoing negative signal on line 30 produces a light pulse on optical fiber 50.
The output line 30 may be connected directly to the base terminal of a transistor 46 which serves as 41~
a switch for a light emitting diode or LED 48. If line 30 carries a low level signal, transistor 46 conducts, causing the energized LED 48 to emit light which is directed to the optical fiber 50 in the channel 14. Correspondingly, when line 30 carries a high logic level signal, transistor 46 is switched off to de-energize the LED 48.
The incoming simplex line 34 is connected at the collector junction of a phototransistor 52. When the incoming optical signal is high (i.e., light is being transmitted, phototransistor 52 conducts to pull the line 34 toward ground. When no optical signal is presented over the incoming optical fiber 56, phototran-sistor 52 is non-conductive, allowing line 34 to rise toward the voltage provided by a positive voltage source.
Generally speaking, the circuit described above operates in the following manner to provide half-duplex/
simplex digital signal conversion. While incoming digital signals received on line 34 are applied to all three inputs of the NAND gate 28, different delays are in-troduced at the three inputs. Also, an inverted form of the signal is applied at one of the inputs. As a result, there is a lack of coincidence which prevents any incoming signal from being transferred through the gate 28 to the output line 30. On the other hand, when data unit 10 is transmitting, any signal provided over half-duplex line 16 is isolated from the incoming simplex line 34 by the high reverse impedance of the inverter 42B. Any signal appearing on half-duplex line 16 is transmitted through the inverter 42C and the NAND gate 28 so as to appear in its normal, but delayed, form at line 30.
While data unit 10 is transmitting, the other two inputs to NAND gate 28 will be at high logic levels, causing the NAND
gate output to follow the signals appearing on line 16.
il~r4~
Figure 2 shows the voltages which exist at various points or nodes in the clrcuit 20. Each of the nodes is identified by an upper case alphabetic character in Figure 1. More specifically, node A is the incoming simplex line 34, node B is input 36 to NAND gate 28, node C is input line 40, node D is half-duplex line 16 and node E is the output line 30 from NAND gate 28. Prior to an arbitrarily se-lected time To~ it is assumed that the receiving optical fiber 56 is transmitting no light; that is, no optical signal.
If a light pulse arrives at time To~ phototransistor 52 is driven into its conductive state causing the voltage at node A to drop from a positive potential to or near ground level. The negative going pulse is applied directly to NAND
gate 28 over line 32.
The inverter 42A delays and inverts the negative going signal on node A. The inverter 42B further delays and re-inverts the incoming signal so that it appears at node D in its normal form at a time Tl. The same signal is also propa-gated through inverter 42C where it is further delayed andagain inverted. Because an odd number of inversion operations are performed, the signal which appears on node C at a time T2 is high or inverted relative to the signal appearing on node A. The low-level signal on node A prevents any switch in NAND gate output when node C
goes high.
The incoming negative-going signal which is propagated through the time delay circuit including inverters 38A, 38B, 30 38C and 38D finally reaches node B at a time T3. The out-put of the NAND gate 28 remains high since both nodes A and B are then low.
When the incoming negative going pulse ends at a time T4, the signals on nodes A, B and C switch in the same time sequence but in opposite directions That is, the signal at node A immediately goes high, the signal at node 4~)~
C goes low at a time T6 after being delayed by each of the three inverters 42A, 42s, 42C in the siynal chain, and the signal at node B finally goes high at time T7 after being inverted by each of the four serially-connected inverters 38A-38D.
The output of NAND gate is held at its high level be-tween times T4 and T6 by the low level signal at node B.
The signal on node C returns to its normal low level at time T6 to hold the NAND gate output at the high level even when nodes A and B are both high after time T7.
Referring to Figure 3, when data unit 10 is trans-mitting, a negative going pulse is applied to the circuit 20 over the half-duplex line 16. This pulse is inverted by inverter 42B before being applied to the NAND gate 28. The high reverse impedances of NAND gate 44 and 42A isolates the incoming line 34 during transmission. Since the signals at nodes A and B remain at their normal high levels, the output of the NAND gate 28 is switched as a function of the signals appearing at the output of inverter 42B. NAND
gate 28 also acts as an inverter causing a delayed nega-tive-going pulse to be applied to the base of transistor 46. Thus, the only difference between signals appearing at nodes D and E is that the latter signals are delayed relative to the former.
It should be apparent that the electro optical converter circuit 22 is required only because communica-tions link 14 utilizes optical fibers. If the communicationslink were an electrical one, the incoming and outgoing sim-plex lines 34 and 30, respectively, would be tied directly or through repeater amplifiers to the half-duplex/simplex signal converter circuit.
While there has been described what is considered to be a preferred embodiment of the invention, variations and modifications therein will occur to those skilled in ~3~4(19 the art once they become acquainted with the basic con-cepts of the invention. Therefore, it is intended that the appended claims shall be construed to include both the preferred embodiment and all such variations and modifications as fall within the true spirit and scope of the invention.
Claims (4)
1. A half-duplex/simplex digital signal converter circuit comprising:
a multiple input coincidence gate having a first input connected directly to a receiving simplex line and its output connected to a transmitting simplex line;
a first time delay circuit connecting a second input of said gate to said receiving simplex line for causing a received simplex signal to be applied to said gate after a first delay period;
a second time delay circuit connecting a third input of said gate to said receiving simplex line for causing an inverted form of a received simplex signal to be applied to said gate after a second delay period shorter than said first delay period, said second time delay circuit being connected to the half-duplex line.
a multiple input coincidence gate having a first input connected directly to a receiving simplex line and its output connected to a transmitting simplex line;
a first time delay circuit connecting a second input of said gate to said receiving simplex line for causing a received simplex signal to be applied to said gate after a first delay period;
a second time delay circuit connecting a third input of said gate to said receiving simplex line for causing an inverted form of a received simplex signal to be applied to said gate after a second delay period shorter than said first delay period, said second time delay circuit being connected to the half-duplex line.
2. A circuit as defined in Claim 1 wherein said second time delay circuit includes at least two time delay elements connected in series and wherein the half-duplex line is connected at a point intermediate two of said elements.
3. A circuit as defined in Claim 2 wherein said first time delay circuit includes a plurality of time delay elements for establishing a delay period of 4T
where T is a base delay time while said second time delay circuit includes elements for establishing a delay period of 3T.
where T is a base delay time while said second time delay circuit includes elements for establishing a delay period of 3T.
4. A circuit as defined in Claim 2 wherein the time delay elements connecting the receiving simplex line to the half-duplex line provide a 2T delay period.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US114,525 | 1980-01-23 | ||
| US06/114,525 US4288869A (en) | 1980-01-23 | 1980-01-23 | Half-duplex/simplex digital signal converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1130409A true CA1130409A (en) | 1982-08-24 |
Family
ID=22355752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA365,432A Expired CA1130409A (en) | 1980-01-23 | 1980-11-25 | Half-duplex/simplex digital signal converter |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4288869A (en) |
| EP (1) | EP0032992B1 (en) |
| CA (1) | CA1130409A (en) |
| DE (1) | DE3066773D1 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2517147A1 (en) * | 1981-11-25 | 1983-05-27 | Telecommunications Sa | DIGITAL OPTICAL PLURAL OPTICAL INFORMATION TRANSMISSION SYSTEM |
| JP2548693B2 (en) * | 1985-03-13 | 1996-10-30 | キヤノン株式会社 | Serial data communication system and device |
| JPS62225096A (en) * | 1986-03-26 | 1987-10-03 | Nec Corp | Radiotelephony system |
| CA2000582C (en) * | 1988-10-13 | 1998-08-11 | Tsuyoshi Yamashita | Optical transmission device |
| JPH0817393B2 (en) * | 1988-11-25 | 1996-02-21 | トヨタ自動車株式会社 | Transmission line branching device |
| US5149190A (en) * | 1989-05-24 | 1992-09-22 | Bay Industrial And Mine Tech Inc. | Portable safety device |
| US5212685A (en) * | 1991-03-21 | 1993-05-18 | International Business Machines Corporation | Control circuit for half-duplex/simplex interface in communication system |
| DE59307745D1 (en) * | 1993-03-19 | 1998-01-08 | Siemens Ag | Transceiver circuit in a passive optical telecommunication system |
| FR2731532A1 (en) * | 1995-06-08 | 1996-09-13 | France Telecom | Cable connection for transmission of music or video signals |
| EP1722488A1 (en) * | 2005-05-13 | 2006-11-15 | Siemens Schweiz AG | SHDSL data transmission line |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CH495666A (en) * | 1968-06-20 | 1970-08-31 | Siemens Ag | Circuit arrangement for the transmission of direct current signals in both directions via a line |
| BE788764A (en) * | 1971-09-13 | 1973-03-13 | Siemens Ag | CONVERTER ASSEMBLY FOR THE TRANSITION FROM THE OPERATION OF TWO-WIRE TELESCRIPTION TO FOUR-WIRE TELESCRIPTION |
| US3967059A (en) * | 1975-02-05 | 1976-06-29 | Sperry Rand Corporation | Bi-directional logic system |
| US3999013A (en) * | 1976-02-23 | 1976-12-21 | Rockwell International Corporation | Bi-directional signaling apparatus |
| US4154978A (en) * | 1977-12-08 | 1979-05-15 | Operating Systems, Inc. | Self-contained bidirectional amplifying repeater |
-
1980
- 1980-01-23 US US06/114,525 patent/US4288869A/en not_active Expired - Lifetime
- 1980-11-25 CA CA365,432A patent/CA1130409A/en not_active Expired
- 1980-12-04 EP EP80107629A patent/EP0032992B1/en not_active Expired
- 1980-12-04 DE DE8080107629T patent/DE3066773D1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| EP0032992A1 (en) | 1981-08-05 |
| DE3066773D1 (en) | 1984-04-05 |
| US4288869A (en) | 1981-09-08 |
| EP0032992B1 (en) | 1984-02-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR910004403B1 (en) | Optical backplane | |
| US4616358A (en) | Switching matrix network | |
| CA1130409A (en) | Half-duplex/simplex digital signal converter | |
| US6208621B1 (en) | Apparatus and method for testing the ability of a pair of serial data transceivers to transmit serial data at one frequency and to receive serial data at another frequency | |
| US4775210A (en) | Voice and data distribution system with fiber optic multinode star network | |
| US4234970A (en) | Fiber optic communication system | |
| KR20230133173A (en) | Parallel receiver module | |
| US5202940A (en) | Modular electro-optic bus coupler system | |
| RU2121230C1 (en) | Optical switching device for connecting optical data locations | |
| US4805234A (en) | Low cost fiber optic network node | |
| JPS6189735A (en) | Time division direction control transmission system of optical communication system | |
| JPH07506468A (en) | Optical processing in asynchronous transmission mode networks | |
| CN111953419B (en) | Optical module | |
| US5513369A (en) | Star coupler device including means for connecting multiple star couplers together in a cascaded relationship | |
| US4864650A (en) | Expansion network for increasing the number of subscriber terminations at a passive optical bus system comprising optical mixers | |
| CN217037192U (en) | Optical network capacity expansion equipment | |
| JP2827501B2 (en) | Optical self-routing circuit | |
| JPS58172039A (en) | Optical transmission system | |
| KR970008299B1 (en) | RZ / NRZ optical converter | |
| JPH0514283A (en) | Light wavelength multiplex transmitting system and node device for light local area network system | |
| KR200314153Y1 (en) | Data parallel transmission device of ATM system | |
| JPS62269595A (en) | light exchange element | |
| SU1690207A1 (en) | Device for control of busy channels of tonal frequency | |
| JPH01229545A (en) | Optical packet switch | |
| JPS58200644A (en) | Optical bus system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |