CA1125392A - Filter circuit utilizing charge transfer device - Google Patents
Filter circuit utilizing charge transfer deviceInfo
- Publication number
- CA1125392A CA1125392A CA344,111A CA344111A CA1125392A CA 1125392 A CA1125392 A CA 1125392A CA 344111 A CA344111 A CA 344111A CA 1125392 A CA1125392 A CA 1125392A
- Authority
- CA
- Canada
- Prior art keywords
- electrodes
- transistors
- capacitive
- filter circuit
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H15/00—Transversal filters
- H03H15/02—Transversal filters using analogue shift registers
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- Networks Using Active Elements (AREA)
- Filters That Use Time-Delay Elements (AREA)
- Dc-Dc Converters (AREA)
- Processing Of Color Television Signals (AREA)
- Amplifiers (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A non-recursive transversal filter circuit employs a charge transfer device in which certain of the capacitive storage elements are divided into first and second capaci-tive portions having predetermined capacitance relation-ships. The charge in the second capacitive storage elements is sensed at predetermined times to produce an output signal. The relative capacitances of the second capacitance portions provide weighting factors to the filter. Embodiments include bucket brigade devices with bipolar and FET transistors as well as charge coupled devices.
A non-recursive transversal filter circuit employs a charge transfer device in which certain of the capacitive storage elements are divided into first and second capaci-tive portions having predetermined capacitance relation-ships. The charge in the second capacitive storage elements is sensed at predetermined times to produce an output signal. The relative capacitances of the second capacitance portions provide weighting factors to the filter. Embodiments include bucket brigade devices with bipolar and FET transistors as well as charge coupled devices.
Description
3~
.. . . . ..... . ~ . . . . . . .
BACKGRO~ND OF THE INVENTION
ield of the Invention ~ he present invcntion relates generally to a Pllter circult utilizing Æ charg~ transfer de~ice such a~
a bucket brigade device or a charge coupled device, and i9 d~rected more particularly to a non-recursive trans-versal fil~er.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 ~8 a ~chematic diagram of a filter circuit according to the prlor Art.
Figs. 2A to 2D are waveforms ~o which reference will be made in explaining the operation of filter circuit~ in the prior art and ~he present invention; and Fig~. 3 to 15 are schematic diagr~m~ of filter~
according to a number of cmbodiments of the present invention.
De~cription of ths Prlor Ar~
I~ general, a prior art fll~er circuit using a bucke~ brigade device may be 8~ ~hown ln Fig. 1. ln ~implest ~erm~, a bucke~ brigade devlce periodicall~
store~ an inpu~ analog or digital ~ignal from an ~nput ~erminal 1 in a cap~citor CO, ~hen pa85e8 the s~ored charge a 8tep at a ~ime from l~f~ ~o righ~ ~hrough capacltors Cl, C2, .... At each st~p, a new input si~nal ~alu~ tored ~n GO, T~U8, a moving s~rea~ of stored charge~ are moved along ~he bucke~ brigade d~ice.
Inpu~ terminai 1 applies a sign~l ~oltage v~;
to the ba~e of a PNP ran~istor 2 who~e collector i~
; grounded and who~ emitter i~ connec~ed through a resi~tor 3 to a power ~upply terminal maineain~d ~t a supply volt~ +~CC snd also through the cathode terminal of .,~ ~
~ 5 3 ~ ~ -A diode 5 to a hot ~ide of capaci~or CO. The o~her or cold side of capacitor CO i8 connected to a clock term~al 6. The hot~.side of capacitor CO i~ also connected ~o the emitter of an NPN transistor Ql whose collector i~ connec~ed to the emitter of an NPN tran3-istor Q2 of the next stage. Similarly, the collectors and emitters of NPN transistors Q2, Q3, ... are connected together, and capacitor~ Cl, C2, ... are connected ii,;,p,, ~
~2~;i3~2 between the bases and collector~ of ehe respective transistors Ql, Q2, ..., respectively. The capacitance of capacitors C0, Cl, C2, ... are 811 equal to the same eapacitance value C. The bases of odd numbered tran9i8tor8 Ql, Q3, ... are connected-through a clock terminal 7 to a clock driver 8. The bases o even numbered transistors Q2, Q4, ... are connected throu~h ~lock ~erminal 6 to olock driver 8~ respec~ively.
Clock termlnal3 S and 7 are 3upplied w$~h clock slgnals ~1 and ~2 (Flgs. 2A and 2B respectlvely) which have potentials or levels VDc and VDc + Vp, at a 50%
duty cycle. Clock signals ~1 and ~2 are 180 out of phase. The voltage Vp sa~isfies condition ~1) with respect to supply voltage Vcc at power supply terminal 4.
Vcc > VDC + 2Vp .... (1~
Further, signal voltage Vs at input termin~l 1 satisfies condition (2).
VDC + Vp < Vs VD~ ~ 2Vp .... ~23 The voltage VD~ applied ~co ~he ba~es of tran~fs-or~ Ql, Q2, Q3, ... i8 lnsufficient to turn ~hem on but the voltage VDc + Vp i8 sufficien~ o bias ~he~ into their active regions.
A~ an ~nitial condition, as~ume that all capaeitors are charged to voltage Vp and that ~ignal voltage Vs applied to inpu~ terminal 1 i~ a first DC value V51. ~ignal voltage Vsl -i~ t~U8 applied to the cathode of diode 5O A~ time to ~F~g. 2A), ~he eloc~ Rignal ~l changes to VDc ~ Vp and clock signal
.. . . . ..... . ~ . . . . . . .
BACKGRO~ND OF THE INVENTION
ield of the Invention ~ he present invcntion relates generally to a Pllter circult utilizing Æ charg~ transfer de~ice such a~
a bucket brigade device or a charge coupled device, and i9 d~rected more particularly to a non-recursive trans-versal fil~er.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 ~8 a ~chematic diagram of a filter circuit according to the prlor Art.
Figs. 2A to 2D are waveforms ~o which reference will be made in explaining the operation of filter circuit~ in the prior art and ~he present invention; and Fig~. 3 to 15 are schematic diagr~m~ of filter~
according to a number of cmbodiments of the present invention.
De~cription of ths Prlor Ar~
I~ general, a prior art fll~er circuit using a bucke~ brigade device may be 8~ ~hown ln Fig. 1. ln ~implest ~erm~, a bucke~ brigade devlce periodicall~
store~ an inpu~ analog or digital ~ignal from an ~nput ~erminal 1 in a cap~citor CO, ~hen pa85e8 the s~ored charge a 8tep at a ~ime from l~f~ ~o righ~ ~hrough capacltors Cl, C2, .... At each st~p, a new input si~nal ~alu~ tored ~n GO, T~U8, a moving s~rea~ of stored charge~ are moved along ~he bucke~ brigade d~ice.
Inpu~ terminai 1 applies a sign~l ~oltage v~;
to the ba~e of a PNP ran~istor 2 who~e collector i~
; grounded and who~ emitter i~ connec~ed through a resi~tor 3 to a power ~upply terminal maineain~d ~t a supply volt~ +~CC snd also through the cathode terminal of .,~ ~
~ 5 3 ~ ~ -A diode 5 to a hot ~ide of capaci~or CO. The o~her or cold side of capacitor CO i8 connected to a clock term~al 6. The hot~.side of capacitor CO i~ also connected ~o the emitter of an NPN transistor Ql whose collector i~ connec~ed to the emitter of an NPN tran3-istor Q2 of the next stage. Similarly, the collectors and emitters of NPN transistors Q2, Q3, ... are connected together, and capacitor~ Cl, C2, ... are connected ii,;,p,, ~
~2~;i3~2 between the bases and collector~ of ehe respective transistors Ql, Q2, ..., respectively. The capacitance of capacitors C0, Cl, C2, ... are 811 equal to the same eapacitance value C. The bases of odd numbered tran9i8tor8 Ql, Q3, ... are connected-through a clock terminal 7 to a clock driver 8. The bases o even numbered transistors Q2, Q4, ... are connected throu~h ~lock ~erminal 6 to olock driver 8~ respec~ively.
Clock termlnal3 S and 7 are 3upplied w$~h clock slgnals ~1 and ~2 (Flgs. 2A and 2B respectlvely) which have potentials or levels VDc and VDc + Vp, at a 50%
duty cycle. Clock signals ~1 and ~2 are 180 out of phase. The voltage Vp sa~isfies condition ~1) with respect to supply voltage Vcc at power supply terminal 4.
Vcc > VDC + 2Vp .... (1~
Further, signal voltage Vs at input termin~l 1 satisfies condition (2).
VDC + Vp < Vs VD~ ~ 2Vp .... ~23 The voltage VD~ applied ~co ~he ba~es of tran~fs-or~ Ql, Q2, Q3, ... i8 lnsufficient to turn ~hem on but the voltage VDc + Vp i8 sufficien~ o bias ~he~ into their active regions.
A~ an ~nitial condition, as~ume that all capaeitors are charged to voltage Vp and that ~ignal voltage Vs applied to inpu~ terminal 1 i~ a first DC value V51. ~ignal voltage Vsl -i~ t~U8 applied to the cathode of diode 5O A~ time to ~F~g. 2A), ~he eloc~ Rignal ~l changes to VDc ~ Vp and clock signal
2 changes to VDc. The ~oltage VDc at the base o transistor Ql cuts off tbi~ tran~mission. The voltage ~.
."~
~253~2 . . , . . ... . .. . .. . . . ... . .. ... .. ~. .. ....... .. ... .. ...........
VDc ~ Yp at the uppqr or cold side of capacitor C0 produces a voltage of VDc + .2~1p (Fig. 2C) a~c the lower or hot side o capscitor C0. According to ~quation (2), this volta~e at the hot side of capacitor C0 and at the anode of diode 5 exce2d~ the signal ~oltage Vsl at the cathode of dioe 5. Thus the charge in c~pacitor J
C0 bleeds off through dioda 5 until the voltage at khe hot side of capacitor C0 equals the ~ignal ~Toltage YSl.
The charge remaining in capacitor C0 at this tima i~ ~, ,0 ~
LVSl ~ (VDc + Vp)} ~- I
At time tl (Fig. 2A~, clock signal ~1 decreases to voltag~ VD~. The voltage at the hot side of capacitor C0 i8 changed to Vsl - Vp (Fig. 2C). At the same time, clock signal ~2 (Flg. 2B) i~ increased to voltage YDC + Yp.
Thi8 voltage, applied to the base of transistor Ql, biases ~cran i8'cor Ql into its active reglon. The ~ame ~roltags appl1 ed to th~ cold side of capacitor Cl produces a voltage VDc + 2Vp (Fig. 2D) at ~he ~ot side of r-apacitor C~. Transis~cor Q2 is cut off by elock 5ignal ~l at it8 ba~e. An smount of charge i3 fQd fFom capaeitor Cl through the collec~or-emitter path of ~ransis~cor el to lncrease the ~rol~age at the hot side of capacitor C0 ~o VDc ~ Vp. This occurs due to ~he voltag~ VDc ~ ~p at the base of transistor Ql. Since ~che voltage at the hot ~ide of capac~or C0 changes from Vsl ~ Vp ~o VDc ~ Vp, the charge transferred~from the hot Ride of capacieor Cl ~o th~ hot ~ide of capaei~or C0 is expressed by equation (3~.
DC P) (VSl ~ Vp)~ C ~ ~VDc + 2Vp - Vsl~ C
....(3 Slnc~ a charge o Vp ~ C was initially s~ored in the capacltor Cl, it8 final ch~rge i8 given a~ follows ~53~32 .. , . ~ . . . . .
Vp C - (VDc + 2Vp - Vs~ VS~ DC ~ Vp)~
.... (~) That i8, during the period to to tl, a voltage is s~ored in capacitor CO which is equal to Vsl-(V~c + Vp).
Thi8 voltage i5 tran~ferred to capacitor Cl during the period ~1 to t2 BO that the volt~ge on capacitor CO
returns to VDc ~ Vp. Since tranSis~or Q2 is OFF at this ~e, capacitor-Q C2, C3, .... are not ~ffected.
Further, during period t2 to ~3, signal voltage Vs may assume a value Vs2. Capacitor CO is d to VS2 ~ (VDC ~ Vp) w~ile capacitor Cl i5 returned to VDc + Vp by thic vol~age at ~he base of transistor Q2. By the process previously described, capacltor C2 is charged to VSl-(vDc + Vp)- Since the transistor Q3 is OFF, capacitors C3, ,.. are not affected.
The above operation is repeated and the slRnal i~
transferred from left to ri~ht on Fi~. 1 in synchronism with clock signals ~1 and ~2.
When a ~ransversal filter of, for example, a non-recurs~ve type is formed using he above bucket brigade device, a plurali y of ~n~ermediate tap~ are provided at appropria~e points in the ~equence. Thls has ~he effe t of providing ~ign~ls with d~fferent telay times whieh may be weight~d ln a predetermined way and added succecsively to produc~ ~n su~put:~ignal.
_ Th~ hot sides of capac~ors CO, C2 and C4, from whieh ~ignals are derived, are connec~ed to the bases of emitter follower trflnsistors 91, 92 and 93, respee~ively.
The emi~tex of the transi~tor~ 91, 92 and 93 are eDnnec~ed to input tPrminals of differential amplifiers 94, 95 and 96, respecti~ely, The o~her input t~rminals _5_ t~.. ~ .~ :
253~2 , . . . . . . .
of differential ampl.ifiers 94, 95 and 96 are connected to a constant ~olta~e source represented by a battery.
Outputs of differentlal ampliflers ~4, 95 and 96 are commonly connec~ed through an l~mitter follower eransis-tor 98 to an output ~erminal 10.
The Rignals from the intermediste tap8 are delivered through emitter follower transistors 91, 92 and 93 and added in ~n analog manner in differential amplifiers 94, 95 and 96. The voltages may be wei~hted by ad~usting the gains of ~he differential amplifiers to desired values.
Analog adding by differential amplifier~ as in the prior ar~ requires an ex~essive number of components with a resultant high power dissipation, Also, sli~ht imbalance in the ~ain ad~ustment of the differential amplifier~ may upset the balance of the circuit and produce scat~ering in the DC level. As a cvnsequence, the correct relationships between input and oueput may not be achieved or the ou~put DC level may ~ecome uns~able.
Further, due ~o the presence of the collector-ba~e capaci~ance CcB o emitter follower tran~i~tor~ 91, 92 and 93, the effective pulse height of ~he clock~ng signal is xeduced by a factor of ~ and the dynamic range of the signal is proportionately lowered. Also, the signal is affected by the base current of em~t~er follower tran~istors 91, 92 and 93. Therefore, a non-recursive transversal fllter utiliz~n~ the circuit shown in Fi~. 1 is not sa~isfactory.
OBJECTS AND SI~MMARY OF THE INVF.NTIt)N
. ~
Accordingly, it i~ an ob3ect of ~he prQ~ent invention to provide a novel filter circult utilizing A .
~ 3 a charge transfer device, It 1~ another ob~ect of the invention to provide a non-recurslve tran~versal filter circuit utilizing a charge transfer devicc free of the defects of the prior art.
Ac~ording to an a~p~ct of the invention, there i9 provided a filter eir~uit comprising a charge ~ran3fer device, a clock signal drive circult including ~eans for supplylng a clock signal to the charge tran~fer device, ~he charge transfer device including a plurality of successive capacitive s~orage meAn~ for sequentially holding a charge level representing a time sampled inpu~
signal, each of the capacitive s~orage means having a cloc~ing electrode for receiving the clock signal so that the charge level i~ transferred from one to anol:her of the capacitive qtorage means in ~ucce3sion in respon~e to the clock signal, a pradetermi~ed plurality of th~
plurality of ~apacitive ~tora8~ ~eans bein~ dlvided into first and second capacitive por~lon~ connectet in parallel for the trans~er and ha~ring a selected capacitive ratio~ th~ fir~ cap~citiv~ portion~ having ~chQ respecti~re fir~ mentioned clocking ~lectrode~ for receiving the clock 8ign81 and lthe second capacitive portions havin$
re~pectiv~ second clocking elec~rodes, ~L first connection point corme~ted to at pr~deeermined number t of the ~econt cloeking ~lectrode~, a second cormec'cion .~
poin~ connectet to the rem3ining num~er of th@ ~cond clocking el~ctrode~, th~ clock signal drive circui~
fur~h~r lncluding firqt and 3econd clock driver clrcuit~
operated in synchronism wi~h the clo~k sign~l and connected to th~ firs~ and 3econt connectlon point~, : . .
respectively, current deteeting ~ean~ ~or detecting :
curren~ flowing through the first ~nd second clock driver circuits, respect~vely, and output means for compounding the detected currents and deriving an output signal. `!
The above, and other o~ects, features and advantage~ of the pre~ent invention, will become apparent from the following description read in con~unctlon with the accompanylng arawings, in which like reference numerals designate the ~ame elemen~s.
I
DESCRIPTION OF THE PREFERRED EMBODIMENTS
_ Referr$n~g now to Fig. 3, a bu~ket brigade device according to the presen~c invention include~ a plurality of even numbered capacitors CO, C2, ...~ which are divided into capacitors portions CO', CO'9; CZ', C2";
..~. The capacita~ces o~ the capacitor portion~ are aQC, (l-aO)C; a2C, (l-a2)C; .... 80 that the 8U~ of ~he pairs of corresponding port~ons is C. The cold ~lde~
of even numbered primed dividet capacitors CO', C2~....
are connected together, ~nd the cold sides of even numbered double primed divided capacitors CO", C2", ....
~'~
5~3~3%
are connected to clock terminal 6.
Complement~ry ~rsnsistors 11 and 12 ha~e their emitter~ connected together and to a common point of the cold sides ~f even numbered divided capac~tor3 CO', C2', ... and their bases connected together to the output ~ide of a clock ~ignal generator 13. Clock slgnal generator 13 delivers a clock signal ~l'.wh$ch has the same pha~e a~ clock ~ignal ~1 and provide~ voltageQ of DC BE and VDC ~ Vp ~ VBE (where VBE ig ~he ba~e-emitter voltage of tran~i~tors 11 and 12). The collector of PNP transistor 12 i~ grounded and the collector of NPN tran~i~tor 11 iB connected to an ou~put terminal 14.
With no input signal, the voltages at the hot side~ of ~11 of capacitor CO', CO", C2', C2", ... are Vp.
During the fir~t period from to to tl when clock signal i8 at ~he level of VDc + Vp (Fig. 2A), if a firs~
input signal YSl i~ applied eo input terminal 1, the voltage acros~ capacitor CO' i8 chsnged from Vp to V
-(VDC ~ ~p~, During this period, a charge of .
p a~ ~VSl (~DC + Vp~ OC {(VDc ~ 2Vp)-Vsl}
..... (53 i5 di~charged through the collec~or of tran istor ll.. One clock period TtT ~ ~ where fc i8 the clock frequency), later from T2 to ~3 during ~he clock s~gnal ~1, the capacitor C2' i8 discharged ~hrough tran~ or ll. A~
this time, the charge~ i8 expre~sed as follow~:
p C ~Vsl ~(VDc + Vp~} ~ a2C ~VD~ ~ 2Vp~ - Vsl}
o~-~-(6) At the ~me ~ime a ~econd lnput 3ignal Vs2 may be accep~ed in capacitor portion CO'.
_9_
."~
~253~2 . . , . . ... . .. . .. . . . ... . .. ... .. ~. .. ....... .. ... .. ...........
VDc ~ Yp at the uppqr or cold side of capacitor C0 produces a voltage of VDc + .2~1p (Fig. 2C) a~c the lower or hot side o capscitor C0. According to ~quation (2), this volta~e at the hot side of capacitor C0 and at the anode of diode 5 exce2d~ the signal ~oltage Vsl at the cathode of dioe 5. Thus the charge in c~pacitor J
C0 bleeds off through dioda 5 until the voltage at khe hot side of capacitor C0 equals the ~ignal ~Toltage YSl.
The charge remaining in capacitor C0 at this tima i~ ~, ,0 ~
LVSl ~ (VDc + Vp)} ~- I
At time tl (Fig. 2A~, clock signal ~1 decreases to voltag~ VD~. The voltage at the hot side of capacitor C0 i8 changed to Vsl - Vp (Fig. 2C). At the same time, clock signal ~2 (Flg. 2B) i~ increased to voltage YDC + Yp.
Thi8 voltage, applied to the base of transistor Ql, biases ~cran i8'cor Ql into its active reglon. The ~ame ~roltags appl1 ed to th~ cold side of capacitor Cl produces a voltage VDc + 2Vp (Fig. 2D) at ~he ~ot side of r-apacitor C~. Transis~cor Q2 is cut off by elock 5ignal ~l at it8 ba~e. An smount of charge i3 fQd fFom capaeitor Cl through the collec~or-emitter path of ~ransis~cor el to lncrease the ~rol~age at the hot side of capacitor C0 ~o VDc ~ Vp. This occurs due to ~he voltag~ VDc ~ ~p at the base of transistor Ql. Since ~che voltage at the hot ~ide of capac~or C0 changes from Vsl ~ Vp ~o VDc ~ Vp, the charge transferred~from the hot Ride of capacieor Cl ~o th~ hot ~ide of capaei~or C0 is expressed by equation (3~.
DC P) (VSl ~ Vp)~ C ~ ~VDc + 2Vp - Vsl~ C
....(3 Slnc~ a charge o Vp ~ C was initially s~ored in the capacltor Cl, it8 final ch~rge i8 given a~ follows ~53~32 .. , . ~ . . . . .
Vp C - (VDc + 2Vp - Vs~ VS~ DC ~ Vp)~
.... (~) That i8, during the period to to tl, a voltage is s~ored in capacitor CO which is equal to Vsl-(V~c + Vp).
Thi8 voltage i5 tran~ferred to capacitor Cl during the period ~1 to t2 BO that the volt~ge on capacitor CO
returns to VDc ~ Vp. Since tranSis~or Q2 is OFF at this ~e, capacitor-Q C2, C3, .... are not ~ffected.
Further, during period t2 to ~3, signal voltage Vs may assume a value Vs2. Capacitor CO is d to VS2 ~ (VDC ~ Vp) w~ile capacitor Cl i5 returned to VDc + Vp by thic vol~age at ~he base of transistor Q2. By the process previously described, capacltor C2 is charged to VSl-(vDc + Vp)- Since the transistor Q3 is OFF, capacitors C3, ,.. are not affected.
The above operation is repeated and the slRnal i~
transferred from left to ri~ht on Fi~. 1 in synchronism with clock signals ~1 and ~2.
When a ~ransversal filter of, for example, a non-recurs~ve type is formed using he above bucket brigade device, a plurali y of ~n~ermediate tap~ are provided at appropria~e points in the ~equence. Thls has ~he effe t of providing ~ign~ls with d~fferent telay times whieh may be weight~d ln a predetermined way and added succecsively to produc~ ~n su~put:~ignal.
_ Th~ hot sides of capac~ors CO, C2 and C4, from whieh ~ignals are derived, are connec~ed to the bases of emitter follower trflnsistors 91, 92 and 93, respee~ively.
The emi~tex of the transi~tor~ 91, 92 and 93 are eDnnec~ed to input tPrminals of differential amplifiers 94, 95 and 96, respecti~ely, The o~her input t~rminals _5_ t~.. ~ .~ :
253~2 , . . . . . . .
of differential ampl.ifiers 94, 95 and 96 are connected to a constant ~olta~e source represented by a battery.
Outputs of differentlal ampliflers ~4, 95 and 96 are commonly connec~ed through an l~mitter follower eransis-tor 98 to an output ~erminal 10.
The Rignals from the intermediste tap8 are delivered through emitter follower transistors 91, 92 and 93 and added in ~n analog manner in differential amplifiers 94, 95 and 96. The voltages may be wei~hted by ad~usting the gains of ~he differential amplifiers to desired values.
Analog adding by differential amplifier~ as in the prior ar~ requires an ex~essive number of components with a resultant high power dissipation, Also, sli~ht imbalance in the ~ain ad~ustment of the differential amplifier~ may upset the balance of the circuit and produce scat~ering in the DC level. As a cvnsequence, the correct relationships between input and oueput may not be achieved or the ou~put DC level may ~ecome uns~able.
Further, due ~o the presence of the collector-ba~e capaci~ance CcB o emitter follower tran~i~tor~ 91, 92 and 93, the effective pulse height of ~he clock~ng signal is xeduced by a factor of ~ and the dynamic range of the signal is proportionately lowered. Also, the signal is affected by the base current of em~t~er follower tran~istors 91, 92 and 93. Therefore, a non-recursive transversal fllter utiliz~n~ the circuit shown in Fi~. 1 is not sa~isfactory.
OBJECTS AND SI~MMARY OF THE INVF.NTIt)N
. ~
Accordingly, it i~ an ob3ect of ~he prQ~ent invention to provide a novel filter circult utilizing A .
~ 3 a charge transfer device, It 1~ another ob~ect of the invention to provide a non-recurslve tran~versal filter circuit utilizing a charge transfer devicc free of the defects of the prior art.
Ac~ording to an a~p~ct of the invention, there i9 provided a filter eir~uit comprising a charge ~ran3fer device, a clock signal drive circult including ~eans for supplylng a clock signal to the charge tran~fer device, ~he charge transfer device including a plurality of successive capacitive s~orage meAn~ for sequentially holding a charge level representing a time sampled inpu~
signal, each of the capacitive s~orage means having a cloc~ing electrode for receiving the clock signal so that the charge level i~ transferred from one to anol:her of the capacitive qtorage means in ~ucce3sion in respon~e to the clock signal, a pradetermi~ed plurality of th~
plurality of ~apacitive ~tora8~ ~eans bein~ dlvided into first and second capacitive por~lon~ connectet in parallel for the trans~er and ha~ring a selected capacitive ratio~ th~ fir~ cap~citiv~ portion~ having ~chQ respecti~re fir~ mentioned clocking ~lectrode~ for receiving the clock 8ign81 and lthe second capacitive portions havin$
re~pectiv~ second clocking elec~rodes, ~L first connection point corme~ted to at pr~deeermined number t of the ~econt cloeking ~lectrode~, a second cormec'cion .~
poin~ connectet to the rem3ining num~er of th@ ~cond clocking el~ctrode~, th~ clock signal drive circui~
fur~h~r lncluding firqt and 3econd clock driver clrcuit~
operated in synchronism wi~h the clo~k sign~l and connected to th~ firs~ and 3econt connectlon point~, : . .
respectively, current deteeting ~ean~ ~or detecting :
curren~ flowing through the first ~nd second clock driver circuits, respect~vely, and output means for compounding the detected currents and deriving an output signal. `!
The above, and other o~ects, features and advantage~ of the pre~ent invention, will become apparent from the following description read in con~unctlon with the accompanylng arawings, in which like reference numerals designate the ~ame elemen~s.
I
DESCRIPTION OF THE PREFERRED EMBODIMENTS
_ Referr$n~g now to Fig. 3, a bu~ket brigade device according to the presen~c invention include~ a plurality of even numbered capacitors CO, C2, ...~ which are divided into capacitors portions CO', CO'9; CZ', C2";
..~. The capacita~ces o~ the capacitor portion~ are aQC, (l-aO)C; a2C, (l-a2)C; .... 80 that the 8U~ of ~he pairs of corresponding port~ons is C. The cold ~lde~
of even numbered primed dividet capacitors CO', C2~....
are connected together, ~nd the cold sides of even numbered double primed divided capacitors CO", C2", ....
~'~
5~3~3%
are connected to clock terminal 6.
Complement~ry ~rsnsistors 11 and 12 ha~e their emitter~ connected together and to a common point of the cold sides ~f even numbered divided capac~tor3 CO', C2', ... and their bases connected together to the output ~ide of a clock ~ignal generator 13. Clock slgnal generator 13 delivers a clock signal ~l'.wh$ch has the same pha~e a~ clock ~ignal ~1 and provide~ voltageQ of DC BE and VDC ~ Vp ~ VBE (where VBE ig ~he ba~e-emitter voltage of tran~i~tors 11 and 12). The collector of PNP transistor 12 i~ grounded and the collector of NPN tran~i~tor 11 iB connected to an ou~put terminal 14.
With no input signal, the voltages at the hot side~ of ~11 of capacitor CO', CO", C2', C2", ... are Vp.
During the fir~t period from to to tl when clock signal i8 at ~he level of VDc + Vp (Fig. 2A), if a firs~
input signal YSl i~ applied eo input terminal 1, the voltage acros~ capacitor CO' i8 chsnged from Vp to V
-(VDC ~ ~p~, During this period, a charge of .
p a~ ~VSl (~DC + Vp~ OC {(VDc ~ 2Vp)-Vsl}
..... (53 i5 di~charged through the collec~or of tran istor ll.. One clock period TtT ~ ~ where fc i8 the clock frequency), later from T2 to ~3 during ~he clock s~gnal ~1, the capacitor C2' i8 discharged ~hrough tran~ or ll. A~
this time, the charge~ i8 expre~sed as follow~:
p C ~Vsl ~(VDc + Vp~} ~ a2C ~VD~ ~ 2Vp~ - Vsl}
o~-~-(6) At the ~me ~ime a ~econd lnput 3ignal Vs2 may be accep~ed in capacitor portion CO'.
_9_
3~2 . . . , . . , . . ., ., . , . ~ .. . . . .. . . . . .... .. . .. .. .. .... .. .
An additional cloclc period later from t4 to t5 of clock ~ignal ~l, a charge ex:pre~sed by the following equ~tion (7) is discharged Prom capacitor C4' through the collector of tran~i~tor ll~
p C {Vsl (VDc ~ Vp)~ ~ a4C ~(VDC + 2Vp)_YSl3 Since all discharging charge~ rom all of capacitor portions CO', ~2', C4'... flow throu~,h the collec~or of transistor 11, ~he total charge QOUT flowing ~hrough ~he collector of transistor 11 i~ expres~ed as follows:
QO~T ~ ~(VDC + 2Vp) ~ Vs~ C(aO + a2Z 1 + a4Z 2 -~where Z - e~T, S - ~w - ~2rrf and f i~ the frequency oP the input signal.
A ~ummed signal is thu~ derived at the collector of transistor 11 which corrcqponds to the ~uecessive sample~ of the inpu~c signal Vs succe~ively delayed by 0, T, 21, ..., weighted by aO, a2~ a4, .... and then added. Thu8, with selected values of aO, a2, ..., a fil~r having a prede~ermined transfer function i8 formed~
The average or mean ~lu~ IAV o~ the collector current of tran~istor ll is ea~pr~ssed a~ follows:
IAY ~ T ~ QOUT C
The em~odimellt o~ the invention in Fig. 3 produces an ~utput in the form oP a currerlt ~O. The embotiment of Fig. 4 produces a voltage output ~îgnal. Th~
collector of transistor ll l~ connected through the collector~emi~ter path o an NP~ transistor 31 to power supply termfnal 4 an~ the base of transi~tor 31 i8 cormected ~o clork termin~l 7. At the same time, ~, 3~2 a capacitor 32 wit~ a capacitance of CA i~ connected at one te~minal to the ~unction of the collector and emitter transistors 11 snd 31 respecti~ely and a~ the other terminal to clock terminal 6~ An output term~nal 33 i8 connec~ed to the connection point betwe~n the collector of transistor 11 and the ~mitter -of ~ransi~tor 31. The initial ~harge on capac~or 32 iY Vp CA.
A charge ~OUT i8 ~ran~ferred through tran~istor 11 as in the previou~ ~mbodiment; The charge on capacitor 32 become~ Vp CA - ~(VDc + Vp) S7 z-l + ....) during the hi~h periods ~VDc + Vp) of clock ~ignal ~1 and hence ~he po~ential of the signal voltage i3 added ~t inpu~ terminal 1. Thug, the outpu~ 'I
~oltage VOuT is expressed a~ follo~s: ¦
VPCA ~ ~(~ C+2Vp)~Vs} C(aO ~ a2Z 1 + .,.,) ¦
V ~ ~
OUT C~, ~VDc + Vp - ~ (aO + a2Z ~ ~ )Vs VP~A (VDc ~ 2Vp) C (aO + a2Z~l + .O..) +
; ~A
+ VDC + Vp ......................... (10) ~ + VSDC + ~SAC ~where ~SDC ' the DC ~ignal component and Vs~c ~ the AC ~ignal component~3 the VO1eage V~uT can be rewr~t~c~n a~ fO11OW~
~T ~ a ~ a2Z 1 + ~--)YSAC
VPCA tVD~ + ~VP - ~SDe) C (aO ~ 82Z 1 ~ , . ) ,~
~A
~DC + Yp .... ~11) ,J
'', '1~
~i2539Z
In the above formula, the fir~t term ~8 the AC signal term and all other terms are DC componen~
terms. Since f ~ O in tha DC component terms, Z
z-2 ~ 1. Therefore, the voltage ~OUT i8 expre88ed as ollows:
V ~ C (aO ~ a2Z 1 ~ ~vsAc PcA -tVDc ~ 2Vp - V5DC)C(aO + a2 + .,.
C
+vDc ~ Vp ....~12 That is, in the circuit shown in Fig. 4, an 1 of C (aO + a2Z~l + ~ )VSAC 18 P
response~to the AC signal component. At thi~ time, the DC signal component in the outpu~ is as follow~:
VPCA -(VDC +_2Vp - VSDc)C(aO + a2 ~
Thus, a DC level shift of ~ CA -~VDc ~ 2Vr - V~G)CI-O+~-+ . 3 +VDC ~ Vp - VsDc 19 produced.
Transistor 2 and diode 5 a~ the input side of the bucket brigade d~vic¢, increa~es the DC potential by 2V8E. The DC potential may be reduced u~ing a two,~tag~
cascad~d emitter follower circuit u~ing trans~stQr~ 34 and 35 ro produce an output at ~lternate ou~put tPrminal 33'. Th~ emit~er fcllowers have the additioaal advantage of reducing the current required from the circui~ to produce the output.
Alternatlv~ly, on~ ~nt o capacitor 32 may be connected to clock slgnal genera~or 13 as indicated by the broken line rather than to clock terminal 6. When connected this way, ~he output voltage VOuT become~ a~
~ol~ws:
t,~ - ~ 2 3~
VouT ~ VSl ~ 2VBE .... (13) Fig. 5 shows a~ embodiment of a ~ucket bxigade device in which the ~ignsl i8 passed beyond the input capacitor CO before it is called upon to produce an output signal. Odd numbered capacitors Cl, C3, .~. sre divided into capacitor portlons Cl', Cl"; C3', G3"; ,..
who~e capacitances are alC, (l-al3C; a3C, (l-a3)C;...
The cold ~ide~ ofthe odd numbered primed capacitor por~ion~ Cl', C3', ... are connected tog~ther, and the cold qides of the odd numbered double pr~med capacitor portion~ Cl", C3", ... are connected to clock ter~inal 7.
Complementary transistors 15 and 16 have their emitters connected together to the connection poi~t of th~ cold side~ o~ divided capacitors Cl', C3', ... ~nd their ba3e~ connected together to the oueput ~ide of ~
clock signal 8enerator 17. Clock signal gen~rator 17 ::
deli~er~ a clock s~gnal ~2' which ha~ the 3am~ ph~e as the clock ~ignal ~2 and which ass~mes voltage~ of VD~ ~ VB~
and ~ ~ + Yp ~ VBE (w~ere YBE i~ the ba~e-emitter voltage of transistor 15 aad 16). The collec~or of NP~ transistor 15 i~ connect~d to power supply terminal 4 and ehe collector of PNP transi3eor 16 i8 connected to a~ output terminal 18.
When no input ~ignal voltage is supplled, ~h~
te~rminal ~oltages~of all divided capacitor por~ions Cl', Cl", C3', C3", ... are Vp. Between to and tl (Fig. 2A) of clock signal ~1 i a 3ignal Yol~age Sl i~ applied ~o input term~nal 1, capaci~or CQ i8 charged up to a ~erminal of Vsl -(VDG + Vp). During ~he period ~1 ~ t~
clock signal ~2 enable~ a charge of alC ~DC + 2Vp) - Vsl~ :
to flow to capacitor portion Cl' from transistor 15 in the direction of an arrow Il. During the period t2 to t3, clock signal ~1 transfers the same charge through tran~s-tor 16 in ~he d~rection of an arrow I0.
During th2 period t3 eo t4, a charge of a3C {(VDc + 2Vp) - Vsl~ 10ws rom capacitor C3' through tr~nsi~tor 16 in ~tle direct$on of the arrow I0.
During the period t4 to t5, a charge of aSC
~(VDc + 2Vp) - Vsl} flows from c.apacitor C5 through ehe collector of transistor 16.
Th~ total amount of charge Q0UT~ which flow~
through th~ collector of tran~istor 16 at ~his ti~e, iA
expressed as follows: ;
QOUT ' ~(VD~ ~ 2Vp) ~ Vs~ C (alZ 1 ~ a3z~2 + ...) - ~(VDc + 2Vp3 - Vs} C Z l ~al ~ a3Zl ~ ...)...(14) That is a signal current Io i~ derlved ~rom the collector of tran3~stor 16 which corre~pond~ ~o the succe~ive samples of the inpue ~ignal delayed by 0, t, 2~, ..., weighted by al; a33 a5, ~.~ and then added. Since the ~ormula for the output ~ignal ~ multlplied b~ z 1, th~ fil~er delays the st reeen~ ~ample by T befor~
providing an ou~put. However, 3inC~ the character$~tic of the fil~er i8 deeermined by the eerm (al + a3Z 1 1 ..~, a filter having ~ charaeteristic ~imilar eo th~ on~ ln Fig. 3 can be for~ed by proper ad~us~ment of th~ valu~s o the constant~ al, a3, ...
The a~erage or m~a~ v~lue IAV of ehe colleotor current of transi~tor 16 i~ expressed ~ follow~:
I ~ QOUT ~ Q f ....(15) ~ 3~ 2 Fig. 6 i~ an embodiment of the invention otherwi~e ~imilar to that shown on Fig. 5, excep~ thae the output i8 a volta~e rather than a current. The collector of transistor 16 i~ grounded through the collector-emitter path of an NPN transi~tor 36 which, ~ogether wlth an NPN
~ransi~tor 37, form3 a current mirror circuit. The emitter of transistor 37 i8 grounded and i~3 collec~or i8 connec~ed to the emitter of t~an~i~tor 31 and to capacitor 32. The base of transistor 31 ~8 connected to ehe connectlon point of the emitters of tran~is~or~ 15 and 16 at which 8 ~ignal equ~valent to clock signal ~2 i~ obt~ined. Outpue terminal 33 i8 connected to the connection polnt of transistor~ 31 and 37.
The base o transi tor 31 receive~ a slgnal equiv-alent to clock ~ignal ~2. Capacitor 32 is driven by clock s~gnal ~1, and during ~he periods when clock signal ~1 as~ume~ the voltage VDc + Yp, tran~istor~ 16 and 37 are turned ON to d~charge capacltor 32~ Thu8, an outpu~
voltage VOu~ is produced in a msn~er similar so circuit of Fig. 4 a~ follows:
~OUT ~ ~ ~al + a3Z 1 + ~3z 1 ~ V~Ac ,~, V~
- CA
~ ~DC + Vp .. ~.(16) E~Oltter followers 34 and 35 ~ay b~ u~ed to r~mov~
th~ DC offset ~ in th~ circu~t of Fig o 4 ~
The ba~e of tr~n~l~tor 31 m~y alternatively be connected to clocki~ 3ignal g~nera~or 17 E19 shown by th~
broken line, In thls ca~e, ~he oueput vol~age ~OUT i~
expre~sed as ~ollows:
YOUT ~ VSl ~ VBE ...(17) F~g. 7 shows an embodiment of a non-recursive transversal f~lter according to the present i~vention using the circuit of Fig. 4 including the broken line connection, but also includlng an arrangemen~ for using both positive and negative factor~ or cons~ants. Transis-tors llp and 12p form a posi~ive output circuit. The cold s~des of selected capacitor por~on~ CO', C4',....
who~e factors aO, a4, ... are positive, are connected together to the connection point between the emitter~ of i transistors llp and 12p Transistora llm and l~m form a negative output circuit. The cold side~ of capaci~or3 C2', C6', ...,whose factors a2, a6, ~.. are nega~i~e, are connected together to the connection point between the emitters of tr~nsi~tor~ llm and 12 The collector of ~ranslstor llm i~ connected to the collector and baYe of a PNP ~ransistor 42 which, ~ogether wi~h a P~IP transistor 44 form~ a current mirror circuit 41. T~e emitterc of tran~istors 42 and 44 are -- connected ~hrough resi~tors 43 and 45 re~pectively to power ~upply terminal 4. The bases of transi~or 42 ~nd 44 are connected together. Resis~ors 43 and 45 balance curreat mirror circuit 41 and generally are selected for equal re~is~ance which may include zero. The collector~
of transis~ors llp ~nd 44 are connected together to ~h~
emitter of ~ransi~tor~31 and ~o capaci~or 32.
When clock ~ignal ~l as~umes the value o V~c ~ Vp, a charge of {(VD~ + 2Vp) - V5} C(aO + a4Z ~ ~ ...) flow~ from capaci~or 32 through transistor llp to capacitor ~ i ' ~
~2~3~
.
portlon~ CO', C4', ... During the same periods, a charge of.
~(VD~ + 2~p) ~ Vs} C(a2Z 1 + a6Z~3 + ...) flow~ through transistor llm rom capacitor portions C2', C6~o~ to current mirror ~ircuit 41. A like charge from current mirror circuit 41 i~ added to capacitor 32~ i The final charge ~A on capacitor 32 i~ expr~sed as follows: ~
Q~ 8 Vp CA ~ {(V~ + 2Vp) Ys} C(a~ ¦
+ {(VDc + 2Vp~ - V~} C~a2Z 1 + a6% 3 ~ ...) ....(18) Thu~, t~e output voltage VOuT is added to the potential of clock ~ignal ~1 and hence i~ expres~ed as ~ollow~:
VOUT ~ [VpcA ~ {(VDc -~ 2Vp) - Vs~ C(aO + a4A 2 ~ ...
{(VDc + 2Vp) - V5} C(a2Z 1 + a~A 3 + O..)]
DC ~ YP
~ ~ I(aO + a4z~2 + ...)-(a2Z~~ + a6Z~3 + ...)~ V~
+ ~ 1trPCA ~ : 1¦
- ~VDc + 2Vp)C ~aO ~ ~4Z
-1 + a6Z~3 ~ )}1+ VDC P
If lt i~ assumed in formula (19) that Vs ~ VsDC * VsAC
and z-l ~ z-2 ~ .,. 1, tha output voltag~ VOuT can b~
expre~sed a~ follows.
Y~UT ~ ~ (aO ~ a2Z~1 + ~4z-2 _ a6Z~3 ~ )V
~SDC
(VDC ~ 2Vp - V5Dc~{ 1 - ~ ~aO-a2+a4-a~..)}
,o,.~20 I~ formula (2~ he fir t torm i8 the AC ~i~nal ~erm ~d the ~Qcond and ollowin~ ~r~ are th~ DC ~ignal - ~2~
~erm~.
Thu8, accordin~ to the present invention, a very simple non-recurs~ve transversal filter can be provided having a trans~er function H(z) of:
H(z)- ~ (aO _ a2Z~1 ~ a4~~2 - a6Z~3 + ...) ..,. (21) Further, since the capacitor~ are supplied with olock pul~es during normal transfer ~imes, the signal tran~ferred through ~he bucket brigade device i8 no~
affected by the output circuit of F~g. 7.
I~ ~he capaci~ance value of capacitor 32 i8 taken as CA, whlch ~ 8 expressed a~ follows:
CA ' ¦(aO + a4 ~...)-(a2 ~ a6 + ...)¦C .... (22) the third term of ~ormula (20) becomes zero, and the DC
level of the output becomes YSDc from wh~ch the DC level ~hift between the input and outp~t i9 removed. The transfer function H(z) become~ as follows and the signal gain i8 lowered.
H(z~ 8 ~ - -~r (aO ~ a2Z 1 ~
.~ .... (23 If ~he capacitance value CA of capac~o~ 32 ~s taken as C(3C~)~ the signal gain i8 maintained but ~he following DC level shift i~ generated~
(VDC + 2Vp - VsDc~ {1 -(aO ~ a2 ~ a4 - a6 ~ ...)~
In order to remove ~he above DC level shi~t, a capacitor 46 may b~ connectet between ground and connectlon point ~1 o~ the emitters of ~ranslstor~ llp and 12p or the connection point E2 of the emitter~ of transistors llm 12m as ~hown in dashed line, The capacitance ~alue C' o~
eapacltor 46 may be selected a~ follows-: ; -18-,5;3~ I
C' ~ k ¦1 -(aO - a2 + a4 - a6 + ...)¦ C .... (24) In the ormula (24), k is as follows:
VD~ ~ 2Vp ~ VSDC .,,, (25) which repre~ent~ the ratio between the peak value Vp of clock signal~ ~1 and ~2 and the tifference between the peak value (V~c ~ 2Vp) at the ho~ side of the re~pecti~e capaci~or in the buc~et brlgade device and the DC
component VsDc of the lnput signal V~. That i8, ~hen (aO - a2 +a4 - a6 ~ ,~.)>1, a negative DC level ~ihift i~ ~enerated due to an excesG o~ DC currcnt tischarged from capacitor 3~. Thu8, when thi~ exces~ DC currene i8 compensated by the pre~ence o~ cspacitor 46, the DC
le~el ~hift is removed. The capaci~ance ~alue C' o~
capacitor 46 may be selected as follow~ to accompli3h this compensstion:
C' ~ k {(aO - a2 + a4 ~ a6 + ...~ -1} C ..., t263 During th~ per~od~ when clock signal ~1 a~ume~ the ~alue VDc + Yp, the charge flow3 to capacitor~ CO', C~', and an exce~ charge expre3sed by ~he foIlowing formula (27) flow~ through ~ran3is~or llm ~o capac~tor 46.
VpC (~D~ + 2Vp - VsD~) {~aO - a2 + 84 - a6 ~ C
.... ~27) Thu8, an exce~s charge of YpC' i8 supplied through current mirror circ~lt 41 to capacltor 32. The shift .~' charge ~oxed in capacitor 32 by ~he:abo~e DC le~el ~hift i8 e~pr~ssed a~ follow~:
I~VD~ ~ 2Vp Y~D~ {1 -(aO - ~2 ~ a4 ~ a6 ~ ...)llC
(~D~ + 2Vp ~ VsDc) {(aO - a2 + a4 - a6 ~ l}C
.... (~8 ,~ .~ ,' .
53 ~ Z
~hi8 shift charge is cancelled by an excess charge suppliedby current mirror circuit 41.
When ~aO - a2 + a4 - a6 + ...)~ 1, a positi~e DC
level shift i9 caused by an excess charge on capac~to~ 32.
This excess can be cancelled if capacitor 46 connected to point ~1, has the following capacitance value C':
C' ~ k {l -(aO - a2 ~ a4 - a6 + ...)~C .... (29) Durin~ the periods in which cloc~ ?3ignal ~1 assumes the value VDc + Vp, a charge expres3ed by ~he following formula t30) flow~ to capacitor 46.
P~ (VDC + 2Vp ~ VSDC) {1 -taO - a2 ~ a4 - a6 + ...)}C
~... (30) This charge compensates for the DC le~el shift a~ in the previous case.
Fig. 8 ~hows another embodiment of the invention in which a non-recursive transversal filter including positive and neg~tive factor~ i8 formed using the circu~t of Fig. 6.
Transi~tor3 15p and 16p form a positlve output eircuit. The cold ?~ide?3 of capacitor3 Cl', C5', ....
whose factor?s (~1, a5, ...) are consldered to be positiv~, are connected together to the cormec~ion point be~ween ~che emitter~ of transistor?s 15p and 16p. Transi~tor~ lSm and 16m form a negative output circuitO The cold ?~ides Ole' capacitors C3', C7', ..., whose fac~ors (a3, a7, ...) are considered to be nega~ive, ars3 connee~ced together ~o the connection poln~ betwee~ ~he emit~ers o~ tran8~8tor8 l5m and 16m~ The collector of a tran~istor 37m ln ~he negative out~ut elrcuit i8 eonnected to the collector and base of tran8i8tor 42 a~d to the base of PNP transistor 44 in curren~ mirror eircul~ 41. The collec~or o~ a ~ransistor . -2~-~,~.
,~
~ ~ 2 ~ 3 ~ 2 37p, in the positive output circuit, and the collector of transi~tor 44 of current mirror circuit 41 are connected together to the emitter o ~ransistor 31 and to capacitor 32, An output voltage VOuT 18 produced by the circuit of Fig. 8 as follow3:
VOUT ~ ~ (al _ ~3z 1 ~ a5Z 2 _ a7Z~3 + )2-1V
~SDC
2Vp ~ VSDc) {1 - ~ (al - a3 + aS - a7 +...)}
....(31) i Thus, a non-recur~iYe transversal filtar wi~h a tranafer function H(z) expre~ed by the follwoing formula (32) is ormed.
H(z) ~ ~ (al - a3A 1 + a5Z 2 _ a7Z 3 + ...) .... (32) In this filter, lf ~he capacitance value C~ of capacitor 32 i8 ~elec~ed a~ expressed b~ the following formula (33), the DC level ~hi~t i~ ~he output volta~e VO~T disappear~.
CA ~ i(al + a5 ~ ...)-(a3 + a7 + ...)¦C. .... (33) ( ' If CA - C, a DC level ~hift ~xprs~sed by' (VDC + 2Vp - VsDc) {1 -(al - a3 + a5 ~ ~7 + ~}
i~ produced. ID ord~r to remov~ this DC lev~l ~hift, when ~al - a3 ~ a5 - a7 ~ ...) ~ 1, a capacitor 46~ ~hown in dashed line~, w th a capacitance valu~ G' ~xpre ~ed by the followlng ormula (34) may b~ conneceed b~we~n ground and ~h~ connec~lon point o~ th~ ~mitter~ of tran~istor~
15m and 16~.
C' ~ k ~ al - a3 ~ ~5 - a7 ~ C .... ~34) ~ hen ~al - a3 + a5 - a7 ~ ...) ~ 1, a DC offset cosrec~lon circuit, shown in dashed line, consisting o 53~32 .
complementary transistors 47, 48 and capacitor 46 may be inserted between the emitter of tran~istor 31 and ground.
Fig. 9 ~hows a further embodiment of the invention in which positive factors are derived from a circuit ~according to Fig. 4 and negative factors are derived from a circuit according to F$g, 6.
The cold sideq ofcapacitors CO', C4, ... are connected together to ~he connection point of the ~mitters of tran~i~tor~ llp and 12p, and the cold s~de~ of capacitors Cl', C5' ? ~ . . are co~nected together to the connection point of the emitter~ of transistor 15m and 16m. The cnllectors o~ transistor~ llp and 44 are connected together to transistor 31 and capacitor 32.
The transer function H(z) of the circuit of Fig. 9 iB expressed aQ follows:
H(z) - ~ (aO - alZ ~ + a4Z 2 _ a5Z 3 ~ ...) ....~35 . The capacitance Yalue of C' of capac~tors 46, ~hown in das~ed lines, for re ving ~he DC lev~l ~hift, may be selected as follows: .
; ` C' 3 k ll -(aO - al + a4 - a5 + ,--~ IC, ...... (3~) :
Fig. 10 show~ a fur~her embodimen~ of the~inv~ntion i~ which two filtered outpu~s ar~ deri~ed from a singl~
bucke brigade device uslng the circuits of F~g~. 7 and 8.
The cold side~ of capQcitors CO', C4', ... ar~ connected together to tran i8~0r8 ll~ and 12p~ which form a first filter 51a, and the cold ~id2s of the capacitors C2', C6', ... are connected together to transistor~ llm and 12m. ~urther, the cold 3ides of the capacitor~ Cl', G5', ... are connected together to tran~i3tors 15p and 16p, which form a second filter 51b, and the cold side~ o~ capacitors ; 3 9 2 , , C3', C7, ... are connected together to ~ran~istors 15m and 16m, The transfer function~ of the respective filters 51a and 51b are the same as those in the embodiments o~
Fig 7 and 8. -Fig. 11 ~hows a further embodimen~ of the ~n~ntion ~j which employ~ a differential amplifier in place of curren~ --mirror circuit 41 in the circuit of Fig. 7. Capacitor~
CO', C4', ..0 are connected to~e~her to ~r~nsistor~ llp and 12p, and the collec~or of transistor llp i8 connected to a transi~tor 31p and a capacitcr 32p. The capacitance -¦
l value Cp of capacitor 32p i~ selected a~ follows: ~¦
Cp 5 (aO + a4 ~ C ......................... (37) ~:
Capacitors C2', C6',... are connected together to transistors llm and 12m, and the eollector of tran~i~tor llm is connected to a tran8i9tor 31m and a capacitor 32~
The caparieance ~alue Cm of capac~tor 32m i8 select~d a~ ~ ¦
follows Cm ~ (a2 ~ a6 + ... )C ..................... (38) r A signal vol~age Vp, expres~ed by ehe f4110wing fonmula (39), i9 derived from the collec~or of ~ran~i~tor llp.
O+a4Z 2~...)VS~ SDC
A signal voltage Vm, expre~sed by the followlng for~ula - (4Q), i8 derived from th~ collector of eran~is~or llm.
(a2Z~1 ~ a6Z 3 + ~S~ SDC ~ 40) These ~i~n~ls are supplled to ~ differeati~l a~pli~ier 60p, which con~i~ts of transi~or3 61p, 62p~ 63p and a resi~tor 64p, and to a diferential amplifi~r 60m, whi~h consi3~s nf tran~ or~ 61~, 62m~ 63m and a re~ or 64~, respectively. A DC ~oleage ~ource 65-equal to ~h~ DC
component VsDc o~ the inpu~ signal i~ connected to th~ base~
~ ~ ~S ~9 ~
of transistors 63p and 63m. The collec~ors of ~ransistors 63p and 62m are connected together through a resistor 66 to power supply terminal 4 and also to an output terminal 67.
If it is a~sumed that the resistsnce of resistor 64p is Rp and that the resistance o~ resistor 6.6 i~
Ro, the gain o~ di~erential amplifier 60p i9 ~. If it is assumed that the resistance of re~istor 64m i9 Rm, the ga~n of differential amplifier 60m beco~es ~.
Thus, if re8i8tance ~p and Rm are selected by the following formulas (41) and (42) respectively, ~he AC compon~nt VOAC of the output signal i8 expre~sed by ormula ~43).
Rp aU+a4+..,. Ri ....(41) aZ~a6~ Ri ........................ ..(42) VOAC ~ ~ (aO - a2Z 1 + a4Z 2 _ a6Z 3 + ... )VsAc ~43) Fur~her, a non-recursive tran8ver8al filter ~not shown~ can be al~o formed using tha circuit of Fig. 8 with a differential amplifier in place of the current ~irror circuit thereo.
Figs~ 12 and 13 respectively ~hows fur~her embodi-ments of the ~nvention in w~ich a bucket brigade device including FETs ~field effect transi~tor~ u~ed. Capaei-tors Cl, C2, ... are connected be~ween the drains ~nd gate~ ~ respective ~ETs Xl, X2, ... Th~ ~oure2~ and drains thereof are successi~ely conneeted together. Thel ga~es o evexy other ~ET Xl, X2, ... are connected ~ogether.
The connection poi~ of the gates of e~en FET8 X2, X4, ...
are eonnected to clock terminal 6. The connectlon point~
of the gates of odd FETs Xl, ~3, ... are connected ~o clock terminal 7. Capacitor CO i8 connected between an input circuit A and clock terminal 6. In this bucket bri~ade . -2~-- - llZ53~Z
device, the output circuit ~mploys~ an enhanc~ment mode MOS FET.
The output o~ the embodiment of Fig. 12 i8 derived from divided portions C0', C2', ... of even capacitors C0, C2, ... and hence this circui~ corresponds .
to the circuit of Fig. 7. N-channel FETs 71~, 71~, 73, 76 and 77 are used in place of transistors lip, llm, 31, 34 and 35 of Fig. 7, and p-channel FETs 72p, 72m, 74 and 75 are us,ed in place of tran~istors 12p, 12m, 42 and 44 of Fig. 7. FETs 71p, 72p and those 71m, 72m are compli~mentary.
The output of ~he ,~mbodlment of Fig. 13, i~ derived from divided portion~ Cl', C3', ... of odd capacltors Cl, C3, ..., and hence this circui~ correQponds to the circuit of Fi~. 8. N-channel FETs 78p, 78m, 80p, 8~m, 31p, 81m and 82 are used in place of transistors 15p, 15m, 37p, 37m, 38p, 38m and 47 of Fig. 8, and p-channel FET8 79p, ~9m and S3 are used in place of transistor~ 16p, 16m and .48 of Fig. 8. The r~mainder of Fig. 13 1~ substane~ally the ~ame a~ Fig. 12. FET~ 78p3 79p; 78m, 7~m; and 82 and 83 respectively, are complementary.
( If th~ potential of clock ~ign 18 ~1 ~ and ,~2' in ~he circuits o~ Figs. 12 a~d 13 ~uppliied ~o the gates of F~Ts 71p, 72p and ?lm, 72m or 78p, 79p ~nd 78m, 7gm i9 et ~ VDC ~ VGS and ~ C + Vp ~ ~GS~ where VGs i8 the voltag~ drop across the gate-~ource of FET~ 71p, 71~, .
78p and 78m when they are conduc~ive, and VGs'' i,~ the voltage drop across the ga~e-Rource of FET8 72p, 7~m, 79p t and 79m when they are oonduc~ive, the circuit~ de~elop :
~n ou~put ~imilar to the circuits in preceding embodimen~
Fig~. 14 and 15 respecti~ely show still further ~mbodiment,~, of the invention u3ing charge coupled deYices (CCD). Electrode~ KO, Kl, ... each having zn area S
are provided on the CCD and al~ernate elecerode~ are connec~ed together. The connection po~nt of even numbered electrodes ~0, K2, ... is connected to clock tenminal 6 and the connection point o~ odd numbered electrode~
Kl, K3, ... i~ connected to clock terminal 7.
In the ~mbodiment of Fig~ 14, an output i8 derived Prom even electrode~ RO, K2, .,. which are respectively divided into electrode~ KO', KO"; K2', ~2"; ...
The areas of th~ electrodes are selected to be aOS, (l-aO~S;
a25, (1-a2)S; ... One portion cf each of divited elec~rode KO", K2", ... i~ connected to clock terminal 6. Certain ones of the other portions of divided electrodes ~O', K2', ... are connected together to ehe output circuit conqi~ting of FET~ 71p and 71m to 77, etc., in a m~nner ~quivalent to the output circuit of Fig. 12.
In the embodiment o ~ig. 15, an outpu~ i8 deri~ed from odd electrodes Kl, K3, ..O which are r~spectively d~videt into electrodes Kl', Kli'; X3i, K3"; ... in a mann~r slmilar to ehe embodimen~ o~ Fig. 14. One portion l of each ti~ided electrode Kl", R3'l, .,. i8 connected:
to clock terminal 7. Certain one~ of divited ~lectrodes Rl', K3', ... are conn~cted ~o ~he output circui~ coa~i~ting of FET~ 78p and 78m to 83, etc., in a ~anner equivalent to the outpue circuit o Fig. 13.
S~ray capaci~anc~ exi8t8 betw~en the elec~rodes supplied w~h clsck ~ignal~ nd ~2 and eh~ channel, and ~he charging and di~eharg~ng of the ~tray cap~cieànce dep~ndd upo~ the level of th~ inco~ing ~ignal. Accordingly, by divlding the electrodes from w~ich ~ha outpu~ i~
deri~ed in the above circuitJ, the capacitance can be ~, .
' -.
divided in correspondence with the areas of the divided electrodeis. If a separate clock signal i8 ~upplied ~o ones of the divided electrodes, the ~eighted outputs can be terived similar to the bucket brigade devlce. The outputs are then added and delivered as the output signal.
Further, ~ince the operation of the filter of ~he invention ii~ the same as the operation of ~ n~rmal charge transfer device, the signal transferred through the bucXet bri~ade device, or charge coupled deYice, or ~, the CCD i3 unaffected.
Having described specific preferred embodiments -of th~ invention with reference to the accompanying dr~wingg, it i3 to be understood ~hat the invention is not limited to those precise ~mbodiments, and tha~ various chan~e~ and modifications may be effected therein by one skilled in the art without depar~ing from the scope or spirlt of the inventlon ~ d~fioed in the appended clalm-.
,~ .
An additional cloclc period later from t4 to t5 of clock ~ignal ~l, a charge ex:pre~sed by the following equ~tion (7) is discharged Prom capacitor C4' through the collector of tran~i~tor ll~
p C {Vsl (VDc ~ Vp)~ ~ a4C ~(VDC + 2Vp)_YSl3 Since all discharging charge~ rom all of capacitor portions CO', ~2', C4'... flow throu~,h the collec~or of transistor 11, ~he total charge QOUT flowing ~hrough ~he collector of transistor 11 i~ expres~ed as follows:
QO~T ~ ~(VDC + 2Vp) ~ Vs~ C(aO + a2Z 1 + a4Z 2 -~where Z - e~T, S - ~w - ~2rrf and f i~ the frequency oP the input signal.
A ~ummed signal is thu~ derived at the collector of transistor 11 which corrcqponds to the ~uecessive sample~ of the inpu~c signal Vs succe~ively delayed by 0, T, 21, ..., weighted by aO, a2~ a4, .... and then added. Thu8, with selected values of aO, a2, ..., a fil~r having a prede~ermined transfer function i8 formed~
The average or mean ~lu~ IAV o~ the collector current of tran~istor ll is ea~pr~ssed a~ follows:
IAY ~ T ~ QOUT C
The em~odimellt o~ the invention in Fig. 3 produces an ~utput in the form oP a currerlt ~O. The embotiment of Fig. 4 produces a voltage output ~îgnal. Th~
collector of transistor ll l~ connected through the collector~emi~ter path o an NP~ transistor 31 to power supply termfnal 4 an~ the base of transi~tor 31 i8 cormected ~o clork termin~l 7. At the same time, ~, 3~2 a capacitor 32 wit~ a capacitance of CA i~ connected at one te~minal to the ~unction of the collector and emitter transistors 11 snd 31 respecti~ely and a~ the other terminal to clock terminal 6~ An output term~nal 33 i8 connec~ed to the connection point betwe~n the collector of transistor 11 and the ~mitter -of ~ransi~tor 31. The initial ~harge on capac~or 32 iY Vp CA.
A charge ~OUT i8 ~ran~ferred through tran~istor 11 as in the previou~ ~mbodiment; The charge on capacitor 32 become~ Vp CA - ~(VDc + Vp) S7 z-l + ....) during the hi~h periods ~VDc + Vp) of clock ~ignal ~1 and hence ~he po~ential of the signal voltage i3 added ~t inpu~ terminal 1. Thug, the outpu~ 'I
~oltage VOuT is expressed a~ follo~s: ¦
VPCA ~ ~(~ C+2Vp)~Vs} C(aO ~ a2Z 1 + .,.,) ¦
V ~ ~
OUT C~, ~VDc + Vp - ~ (aO + a2Z ~ ~ )Vs VP~A (VDc ~ 2Vp) C (aO + a2Z~l + .O..) +
; ~A
+ VDC + Vp ......................... (10) ~ + VSDC + ~SAC ~where ~SDC ' the DC ~ignal component and Vs~c ~ the AC ~ignal component~3 the VO1eage V~uT can be rewr~t~c~n a~ fO11OW~
~T ~ a ~ a2Z 1 + ~--)YSAC
VPCA tVD~ + ~VP - ~SDe) C (aO ~ 82Z 1 ~ , . ) ,~
~A
~DC + Yp .... ~11) ,J
'', '1~
~i2539Z
In the above formula, the fir~t term ~8 the AC signal term and all other terms are DC componen~
terms. Since f ~ O in tha DC component terms, Z
z-2 ~ 1. Therefore, the voltage ~OUT i8 expre88ed as ollows:
V ~ C (aO ~ a2Z 1 ~ ~vsAc PcA -tVDc ~ 2Vp - V5DC)C(aO + a2 + .,.
C
+vDc ~ Vp ....~12 That is, in the circuit shown in Fig. 4, an 1 of C (aO + a2Z~l + ~ )VSAC 18 P
response~to the AC signal component. At thi~ time, the DC signal component in the outpu~ is as follow~:
VPCA -(VDC +_2Vp - VSDc)C(aO + a2 ~
Thus, a DC level shift of ~ CA -~VDc ~ 2Vr - V~G)CI-O+~-+ . 3 +VDC ~ Vp - VsDc 19 produced.
Transistor 2 and diode 5 a~ the input side of the bucket brigade d~vic¢, increa~es the DC potential by 2V8E. The DC potential may be reduced u~ing a two,~tag~
cascad~d emitter follower circuit u~ing trans~stQr~ 34 and 35 ro produce an output at ~lternate ou~put tPrminal 33'. Th~ emit~er fcllowers have the additioaal advantage of reducing the current required from the circui~ to produce the output.
Alternatlv~ly, on~ ~nt o capacitor 32 may be connected to clock slgnal genera~or 13 as indicated by the broken line rather than to clock terminal 6. When connected this way, ~he output voltage VOuT become~ a~
~ol~ws:
t,~ - ~ 2 3~
VouT ~ VSl ~ 2VBE .... (13) Fig. 5 shows a~ embodiment of a ~ucket bxigade device in which the ~ignsl i8 passed beyond the input capacitor CO before it is called upon to produce an output signal. Odd numbered capacitors Cl, C3, .~. sre divided into capacitor portlons Cl', Cl"; C3', G3"; ,..
who~e capacitances are alC, (l-al3C; a3C, (l-a3)C;...
The cold ~ide~ ofthe odd numbered primed capacitor por~ion~ Cl', C3', ... are connected tog~ther, and the cold qides of the odd numbered double pr~med capacitor portion~ Cl", C3", ... are connected to clock ter~inal 7.
Complementary transistors 15 and 16 have their emitters connected together to the connection poi~t of th~ cold side~ o~ divided capacitors Cl', C3', ... ~nd their ba3e~ connected together to the oueput ~ide of ~
clock signal 8enerator 17. Clock signal gen~rator 17 ::
deli~er~ a clock s~gnal ~2' which ha~ the 3am~ ph~e as the clock ~ignal ~2 and which ass~mes voltage~ of VD~ ~ VB~
and ~ ~ + Yp ~ VBE (w~ere YBE i~ the ba~e-emitter voltage of transistor 15 aad 16). The collec~or of NP~ transistor 15 i~ connect~d to power supply terminal 4 and ehe collector of PNP transi3eor 16 i8 connected to a~ output terminal 18.
When no input ~ignal voltage is supplled, ~h~
te~rminal ~oltages~of all divided capacitor por~ions Cl', Cl", C3', C3", ... are Vp. Between to and tl (Fig. 2A) of clock signal ~1 i a 3ignal Yol~age Sl i~ applied ~o input term~nal 1, capaci~or CQ i8 charged up to a ~erminal of Vsl -(VDG + Vp). During ~he period ~1 ~ t~
clock signal ~2 enable~ a charge of alC ~DC + 2Vp) - Vsl~ :
to flow to capacitor portion Cl' from transistor 15 in the direction of an arrow Il. During the period t2 to t3, clock signal ~1 transfers the same charge through tran~s-tor 16 in ~he d~rection of an arrow I0.
During th2 period t3 eo t4, a charge of a3C {(VDc + 2Vp) - Vsl~ 10ws rom capacitor C3' through tr~nsi~tor 16 in ~tle direct$on of the arrow I0.
During the period t4 to t5, a charge of aSC
~(VDc + 2Vp) - Vsl} flows from c.apacitor C5 through ehe collector of transistor 16.
Th~ total amount of charge Q0UT~ which flow~
through th~ collector of tran~istor 16 at ~his ti~e, iA
expressed as follows: ;
QOUT ' ~(VD~ ~ 2Vp) ~ Vs~ C (alZ 1 ~ a3z~2 + ...) - ~(VDc + 2Vp3 - Vs} C Z l ~al ~ a3Zl ~ ...)...(14) That is a signal current Io i~ derlved ~rom the collector of tran3~stor 16 which corre~pond~ ~o the succe~ive samples of the inpue ~ignal delayed by 0, t, 2~, ..., weighted by al; a33 a5, ~.~ and then added. Since the ~ormula for the output ~ignal ~ multlplied b~ z 1, th~ fil~er delays the st reeen~ ~ample by T befor~
providing an ou~put. However, 3inC~ the character$~tic of the fil~er i8 deeermined by the eerm (al + a3Z 1 1 ..~, a filter having ~ charaeteristic ~imilar eo th~ on~ ln Fig. 3 can be for~ed by proper ad~us~ment of th~ valu~s o the constant~ al, a3, ...
The a~erage or m~a~ v~lue IAV of ehe colleotor current of transi~tor 16 i~ expressed ~ follow~:
I ~ QOUT ~ Q f ....(15) ~ 3~ 2 Fig. 6 i~ an embodiment of the invention otherwi~e ~imilar to that shown on Fig. 5, excep~ thae the output i8 a volta~e rather than a current. The collector of transistor 16 i~ grounded through the collector-emitter path of an NPN transi~tor 36 which, ~ogether wlth an NPN
~ransi~tor 37, form3 a current mirror circuit. The emitter of transistor 37 i8 grounded and i~3 collec~or i8 connec~ed to the emitter of t~an~i~tor 31 and to capacitor 32. The base of transistor 31 ~8 connected to ehe connectlon point of the emitters of tran~is~or~ 15 and 16 at which 8 ~ignal equ~valent to clock signal ~2 i~ obt~ined. Outpue terminal 33 i8 connected to the connection polnt of transistor~ 31 and 37.
The base o transi tor 31 receive~ a slgnal equiv-alent to clock ~ignal ~2. Capacitor 32 is driven by clock s~gnal ~1, and during ~he periods when clock signal ~1 as~ume~ the voltage VDc + Yp, tran~istor~ 16 and 37 are turned ON to d~charge capacltor 32~ Thu8, an outpu~
voltage VOu~ is produced in a msn~er similar so circuit of Fig. 4 a~ follows:
~OUT ~ ~ ~al + a3Z 1 + ~3z 1 ~ V~Ac ,~, V~
- CA
~ ~DC + Vp .. ~.(16) E~Oltter followers 34 and 35 ~ay b~ u~ed to r~mov~
th~ DC offset ~ in th~ circu~t of Fig o 4 ~
The ba~e of tr~n~l~tor 31 m~y alternatively be connected to clocki~ 3ignal g~nera~or 17 E19 shown by th~
broken line, In thls ca~e, ~he oueput vol~age ~OUT i~
expre~sed as ~ollows:
YOUT ~ VSl ~ VBE ...(17) F~g. 7 shows an embodiment of a non-recursive transversal f~lter according to the present i~vention using the circuit of Fig. 4 including the broken line connection, but also includlng an arrangemen~ for using both positive and negative factor~ or cons~ants. Transis-tors llp and 12p form a posi~ive output circuit. The cold s~des of selected capacitor por~on~ CO', C4',....
who~e factors aO, a4, ... are positive, are connected together to the connection point between the emitter~ of i transistors llp and 12p Transistora llm and l~m form a negative output circuit. The cold side~ of capaci~or3 C2', C6', ...,whose factors a2, a6, ~.. are nega~i~e, are connected together to the connection point between the emitters of tr~nsi~tor~ llm and 12 The collector of ~ranslstor llm i~ connected to the collector and baYe of a PNP ~ransistor 42 which, ~ogether wi~h a P~IP transistor 44 form~ a current mirror circuit 41. T~e emitterc of tran~istors 42 and 44 are -- connected ~hrough resi~tors 43 and 45 re~pectively to power ~upply terminal 4. The bases of transi~or 42 ~nd 44 are connected together. Resis~ors 43 and 45 balance curreat mirror circuit 41 and generally are selected for equal re~is~ance which may include zero. The collector~
of transis~ors llp ~nd 44 are connected together to ~h~
emitter of ~ransi~tor~31 and ~o capaci~or 32.
When clock ~ignal ~l as~umes the value o V~c ~ Vp, a charge of {(VD~ + 2Vp) - V5} C(aO + a4Z ~ ~ ...) flow~ from capaci~or 32 through transistor llp to capacitor ~ i ' ~
~2~3~
.
portlon~ CO', C4', ... During the same periods, a charge of.
~(VD~ + 2~p) ~ Vs} C(a2Z 1 + a6Z~3 + ...) flow~ through transistor llm rom capacitor portions C2', C6~o~ to current mirror ~ircuit 41. A like charge from current mirror circuit 41 i~ added to capacitor 32~ i The final charge ~A on capacitor 32 i~ expr~sed as follows: ~
Q~ 8 Vp CA ~ {(V~ + 2Vp) Ys} C(a~ ¦
+ {(VDc + 2Vp~ - V~} C~a2Z 1 + a6% 3 ~ ...) ....(18) Thu~, t~e output voltage VOuT is added to the potential of clock ~ignal ~1 and hence i~ expres~ed as ~ollow~:
VOUT ~ [VpcA ~ {(VDc -~ 2Vp) - Vs~ C(aO + a4A 2 ~ ...
{(VDc + 2Vp) - V5} C(a2Z 1 + a~A 3 + O..)]
DC ~ YP
~ ~ I(aO + a4z~2 + ...)-(a2Z~~ + a6Z~3 + ...)~ V~
+ ~ 1trPCA ~ : 1¦
- ~VDc + 2Vp)C ~aO ~ ~4Z
-1 + a6Z~3 ~ )}1+ VDC P
If lt i~ assumed in formula (19) that Vs ~ VsDC * VsAC
and z-l ~ z-2 ~ .,. 1, tha output voltag~ VOuT can b~
expre~sed a~ follows.
Y~UT ~ ~ (aO ~ a2Z~1 + ~4z-2 _ a6Z~3 ~ )V
~SDC
(VDC ~ 2Vp - V5Dc~{ 1 - ~ ~aO-a2+a4-a~..)}
,o,.~20 I~ formula (2~ he fir t torm i8 the AC ~i~nal ~erm ~d the ~Qcond and ollowin~ ~r~ are th~ DC ~ignal - ~2~
~erm~.
Thu8, accordin~ to the present invention, a very simple non-recurs~ve transversal filter can be provided having a trans~er function H(z) of:
H(z)- ~ (aO _ a2Z~1 ~ a4~~2 - a6Z~3 + ...) ..,. (21) Further, since the capacitor~ are supplied with olock pul~es during normal transfer ~imes, the signal tran~ferred through ~he bucket brigade device i8 no~
affected by the output circuit of F~g. 7.
I~ ~he capaci~ance value of capacitor 32 i8 taken as CA, whlch ~ 8 expressed a~ follows:
CA ' ¦(aO + a4 ~...)-(a2 ~ a6 + ...)¦C .... (22) the third term of ~ormula (20) becomes zero, and the DC
level of the output becomes YSDc from wh~ch the DC level ~hift between the input and outp~t i9 removed. The transfer function H(z) become~ as follows and the signal gain i8 lowered.
H(z~ 8 ~ - -~r (aO ~ a2Z 1 ~
.~ .... (23 If ~he capacitance value CA of capac~o~ 32 ~s taken as C(3C~)~ the signal gain i8 maintained but ~he following DC level shift i~ generated~
(VDC + 2Vp - VsDc~ {1 -(aO ~ a2 ~ a4 - a6 ~ ...)~
In order to remove ~he above DC level shi~t, a capacitor 46 may b~ connectet between ground and connectlon point ~1 o~ the emitters of ~ranslstor~ llp and 12p or the connection point E2 of the emitter~ of transistors llm 12m as ~hown in dashed line, The capacitance ~alue C' o~
eapacltor 46 may be selected a~ follows-: ; -18-,5;3~ I
C' ~ k ¦1 -(aO - a2 + a4 - a6 + ...)¦ C .... (24) In the ormula (24), k is as follows:
VD~ ~ 2Vp ~ VSDC .,,, (25) which repre~ent~ the ratio between the peak value Vp of clock signal~ ~1 and ~2 and the tifference between the peak value (V~c ~ 2Vp) at the ho~ side of the re~pecti~e capaci~or in the buc~et brlgade device and the DC
component VsDc of the lnput signal V~. That i8, ~hen (aO - a2 +a4 - a6 ~ ,~.)>1, a negative DC level ~ihift i~ ~enerated due to an excesG o~ DC currcnt tischarged from capacitor 3~. Thu8, when thi~ exces~ DC currene i8 compensated by the pre~ence o~ cspacitor 46, the DC
le~el ~hift is removed. The capaci~ance ~alue C' o~
capacitor 46 may be selected as follow~ to accompli3h this compensstion:
C' ~ k {(aO - a2 + a4 ~ a6 + ...~ -1} C ..., t263 During th~ per~od~ when clock signal ~1 a~ume~ the ~alue VDc + Yp, the charge flow3 to capacitor~ CO', C~', and an exce~ charge expre3sed by ~he foIlowing formula (27) flow~ through ~ran3is~or llm ~o capac~tor 46.
VpC (~D~ + 2Vp - VsD~) {~aO - a2 + 84 - a6 ~ C
.... ~27) Thu8, an exce~s charge of YpC' i8 supplied through current mirror circ~lt 41 to capacltor 32. The shift .~' charge ~oxed in capacitor 32 by ~he:abo~e DC le~el ~hift i8 e~pr~ssed a~ follow~:
I~VD~ ~ 2Vp Y~D~ {1 -(aO - ~2 ~ a4 ~ a6 ~ ...)llC
(~D~ + 2Vp ~ VsDc) {(aO - a2 + a4 - a6 ~ l}C
.... (~8 ,~ .~ ,' .
53 ~ Z
~hi8 shift charge is cancelled by an excess charge suppliedby current mirror circuit 41.
When ~aO - a2 + a4 - a6 + ...)~ 1, a positi~e DC
level shift i9 caused by an excess charge on capac~to~ 32.
This excess can be cancelled if capacitor 46 connected to point ~1, has the following capacitance value C':
C' ~ k {l -(aO - a2 ~ a4 - a6 + ...)~C .... (29) Durin~ the periods in which cloc~ ?3ignal ~1 assumes the value VDc + Vp, a charge expres3ed by ~he following formula t30) flow~ to capacitor 46.
P~ (VDC + 2Vp ~ VSDC) {1 -taO - a2 ~ a4 - a6 + ...)}C
~... (30) This charge compensates for the DC le~el shift a~ in the previous case.
Fig. 8 ~hows another embodiment of the invention in which a non-recursive transversal filter including positive and neg~tive factor~ i8 formed using the circu~t of Fig. 6.
Transi~tor3 15p and 16p form a positlve output eircuit. The cold ?~ide?3 of capacitor3 Cl', C5', ....
whose factor?s (~1, a5, ...) are consldered to be positiv~, are connected together to the cormec~ion point be~ween ~che emitter~ of transistor?s 15p and 16p. Transi~tor~ lSm and 16m form a negative output circuitO The cold ?~ides Ole' capacitors C3', C7', ..., whose fac~ors (a3, a7, ...) are considered to be nega~ive, ars3 connee~ced together ~o the connection poln~ betwee~ ~he emit~ers o~ tran8~8tor8 l5m and 16m~ The collector of a tran~istor 37m ln ~he negative out~ut elrcuit i8 eonnected to the collector and base of tran8i8tor 42 a~d to the base of PNP transistor 44 in curren~ mirror eircul~ 41. The collec~or o~ a ~ransistor . -2~-~,~.
,~
~ ~ 2 ~ 3 ~ 2 37p, in the positive output circuit, and the collector of transi~tor 44 of current mirror circuit 41 are connected together to the emitter o ~ransistor 31 and to capacitor 32, An output voltage VOuT 18 produced by the circuit of Fig. 8 as follow3:
VOUT ~ ~ (al _ ~3z 1 ~ a5Z 2 _ a7Z~3 + )2-1V
~SDC
2Vp ~ VSDc) {1 - ~ (al - a3 + aS - a7 +...)}
....(31) i Thus, a non-recur~iYe transversal filtar wi~h a tranafer function H(z) expre~ed by the follwoing formula (32) is ormed.
H(z) ~ ~ (al - a3A 1 + a5Z 2 _ a7Z 3 + ...) .... (32) In this filter, lf ~he capacitance value C~ of capacitor 32 i8 ~elec~ed a~ expressed b~ the following formula (33), the DC level ~hi~t i~ ~he output volta~e VO~T disappear~.
CA ~ i(al + a5 ~ ...)-(a3 + a7 + ...)¦C. .... (33) ( ' If CA - C, a DC level ~hift ~xprs~sed by' (VDC + 2Vp - VsDc) {1 -(al - a3 + a5 ~ ~7 + ~}
i~ produced. ID ord~r to remov~ this DC lev~l ~hift, when ~al - a3 ~ a5 - a7 ~ ...) ~ 1, a capacitor 46~ ~hown in dashed line~, w th a capacitance valu~ G' ~xpre ~ed by the followlng ormula (34) may b~ conneceed b~we~n ground and ~h~ connec~lon point o~ th~ ~mitter~ of tran~istor~
15m and 16~.
C' ~ k ~ al - a3 ~ ~5 - a7 ~ C .... ~34) ~ hen ~al - a3 + a5 - a7 ~ ...) ~ 1, a DC offset cosrec~lon circuit, shown in dashed line, consisting o 53~32 .
complementary transistors 47, 48 and capacitor 46 may be inserted between the emitter of tran~istor 31 and ground.
Fig. 9 ~hows a further embodiment of the invention in which positive factors are derived from a circuit ~according to Fig. 4 and negative factors are derived from a circuit according to F$g, 6.
The cold sideq ofcapacitors CO', C4, ... are connected together to ~he connection point of the ~mitters of tran~i~tor~ llp and 12p, and the cold s~de~ of capacitors Cl', C5' ? ~ . . are co~nected together to the connection point of the emitter~ of transistor 15m and 16m. The cnllectors o~ transistor~ llp and 44 are connected together to transistor 31 and capacitor 32.
The transer function H(z) of the circuit of Fig. 9 iB expressed aQ follows:
H(z) - ~ (aO - alZ ~ + a4Z 2 _ a5Z 3 ~ ...) ....~35 . The capacitance Yalue of C' of capac~tors 46, ~hown in das~ed lines, for re ving ~he DC lev~l ~hift, may be selected as follows: .
; ` C' 3 k ll -(aO - al + a4 - a5 + ,--~ IC, ...... (3~) :
Fig. 10 show~ a fur~her embodimen~ of the~inv~ntion i~ which two filtered outpu~s ar~ deri~ed from a singl~
bucke brigade device uslng the circuits of F~g~. 7 and 8.
The cold side~ of capQcitors CO', C4', ... ar~ connected together to tran i8~0r8 ll~ and 12p~ which form a first filter 51a, and the cold ~id2s of the capacitors C2', C6', ... are connected together to transistor~ llm and 12m. ~urther, the cold 3ides of the capacitor~ Cl', G5', ... are connected together to tran~i3tors 15p and 16p, which form a second filter 51b, and the cold side~ o~ capacitors ; 3 9 2 , , C3', C7, ... are connected together to ~ran~istors 15m and 16m, The transfer function~ of the respective filters 51a and 51b are the same as those in the embodiments o~
Fig 7 and 8. -Fig. 11 ~hows a further embodimen~ of the ~n~ntion ~j which employ~ a differential amplifier in place of curren~ --mirror circuit 41 in the circuit of Fig. 7. Capacitor~
CO', C4', ..0 are connected to~e~her to ~r~nsistor~ llp and 12p, and the collec~or of transistor llp i8 connected to a transi~tor 31p and a capacitcr 32p. The capacitance -¦
l value Cp of capacitor 32p i~ selected a~ follows: ~¦
Cp 5 (aO + a4 ~ C ......................... (37) ~:
Capacitors C2', C6',... are connected together to transistors llm and 12m, and the eollector of tran~i~tor llm is connected to a tran8i9tor 31m and a capacitor 32~
The caparieance ~alue Cm of capac~tor 32m i8 select~d a~ ~ ¦
follows Cm ~ (a2 ~ a6 + ... )C ..................... (38) r A signal vol~age Vp, expres~ed by ehe f4110wing fonmula (39), i9 derived from the collec~or of ~ran~i~tor llp.
O+a4Z 2~...)VS~ SDC
A signal voltage Vm, expre~sed by the followlng for~ula - (4Q), i8 derived from th~ collector of eran~is~or llm.
(a2Z~1 ~ a6Z 3 + ~S~ SDC ~ 40) These ~i~n~ls are supplled to ~ differeati~l a~pli~ier 60p, which con~i~ts of transi~or3 61p, 62p~ 63p and a resi~tor 64p, and to a diferential amplifi~r 60m, whi~h consi3~s nf tran~ or~ 61~, 62m~ 63m and a re~ or 64~, respectively. A DC ~oleage ~ource 65-equal to ~h~ DC
component VsDc o~ the inpu~ signal i~ connected to th~ base~
~ ~ ~S ~9 ~
of transistors 63p and 63m. The collec~ors of ~ransistors 63p and 62m are connected together through a resistor 66 to power supply terminal 4 and also to an output terminal 67.
If it is a~sumed that the resistsnce of resistor 64p is Rp and that the resistance o~ resistor 6.6 i~
Ro, the gain o~ di~erential amplifier 60p i9 ~. If it is assumed that the resistance of re~istor 64m i9 Rm, the ga~n of differential amplifier 60m beco~es ~.
Thus, if re8i8tance ~p and Rm are selected by the following formulas (41) and (42) respectively, ~he AC compon~nt VOAC of the output signal i8 expre~sed by ormula ~43).
Rp aU+a4+..,. Ri ....(41) aZ~a6~ Ri ........................ ..(42) VOAC ~ ~ (aO - a2Z 1 + a4Z 2 _ a6Z 3 + ... )VsAc ~43) Fur~her, a non-recursive tran8ver8al filter ~not shown~ can be al~o formed using tha circuit of Fig. 8 with a differential amplifier in place of the current ~irror circuit thereo.
Figs~ 12 and 13 respectively ~hows fur~her embodi-ments of the ~nvention in w~ich a bucket brigade device including FETs ~field effect transi~tor~ u~ed. Capaei-tors Cl, C2, ... are connected be~ween the drains ~nd gate~ ~ respective ~ETs Xl, X2, ... Th~ ~oure2~ and drains thereof are successi~ely conneeted together. Thel ga~es o evexy other ~ET Xl, X2, ... are connected ~ogether.
The connection poi~ of the gates of e~en FET8 X2, X4, ...
are eonnected to clock terminal 6. The connectlon point~
of the gates of odd FETs Xl, ~3, ... are connected ~o clock terminal 7. Capacitor CO i8 connected between an input circuit A and clock terminal 6. In this bucket bri~ade . -2~-- - llZ53~Z
device, the output circuit ~mploys~ an enhanc~ment mode MOS FET.
The output o~ the embodiment of Fig. 12 i8 derived from divided portions C0', C2', ... of even capacitors C0, C2, ... and hence this circui~ corresponds .
to the circuit of Fig. 7. N-channel FETs 71~, 71~, 73, 76 and 77 are used in place of transistors lip, llm, 31, 34 and 35 of Fig. 7, and p-channel FETs 72p, 72m, 74 and 75 are us,ed in place of tran~istors 12p, 12m, 42 and 44 of Fig. 7. FETs 71p, 72p and those 71m, 72m are compli~mentary.
The output of ~he ,~mbodlment of Fig. 13, i~ derived from divided portion~ Cl', C3', ... of odd capacltors Cl, C3, ..., and hence this circui~ correQponds to the circuit of Fi~. 8. N-channel FETs 78p, 78m, 80p, 8~m, 31p, 81m and 82 are used in place of transistors 15p, 15m, 37p, 37m, 38p, 38m and 47 of Fig. 8, and p-channel FET8 79p, ~9m and S3 are used in place of transistor~ 16p, 16m and .48 of Fig. 8. The r~mainder of Fig. 13 1~ substane~ally the ~ame a~ Fig. 12. FET~ 78p3 79p; 78m, 7~m; and 82 and 83 respectively, are complementary.
( If th~ potential of clock ~ign 18 ~1 ~ and ,~2' in ~he circuits o~ Figs. 12 a~d 13 ~uppliied ~o the gates of F~Ts 71p, 72p and ?lm, 72m or 78p, 79p ~nd 78m, 7gm i9 et ~ VDC ~ VGS and ~ C + Vp ~ ~GS~ where VGs i8 the voltag~ drop across the gate-~ource of FET~ 71p, 71~, .
78p and 78m when they are conduc~ive, and VGs'' i,~ the voltage drop across the ga~e-Rource of FET8 72p, 7~m, 79p t and 79m when they are oonduc~ive, the circuit~ de~elop :
~n ou~put ~imilar to the circuits in preceding embodimen~
Fig~. 14 and 15 respecti~ely show still further ~mbodiment,~, of the invention u3ing charge coupled deYices (CCD). Electrode~ KO, Kl, ... each having zn area S
are provided on the CCD and al~ernate elecerode~ are connec~ed together. The connection po~nt of even numbered electrodes ~0, K2, ... is connected to clock tenminal 6 and the connection point o~ odd numbered electrode~
Kl, K3, ... i~ connected to clock terminal 7.
In the ~mbodiment of Fig~ 14, an output i8 derived Prom even electrode~ RO, K2, .,. which are respectively divided into electrode~ KO', KO"; K2', ~2"; ...
The areas of th~ electrodes are selected to be aOS, (l-aO~S;
a25, (1-a2)S; ... One portion cf each of divited elec~rode KO", K2", ... i~ connected to clock terminal 6. Certain ones of the other portions of divided electrodes ~O', K2', ... are connected together to ehe output circuit conqi~ting of FET~ 71p and 71m to 77, etc., in a m~nner ~quivalent to the output circuit of Fig. 12.
In the embodiment o ~ig. 15, an outpu~ i8 deri~ed from odd electrodes Kl, K3, ..O which are r~spectively d~videt into electrodes Kl', Kli'; X3i, K3"; ... in a mann~r slmilar to ehe embodimen~ o~ Fig. 14. One portion l of each ti~ided electrode Kl", R3'l, .,. i8 connected:
to clock terminal 7. Certain one~ of divited ~lectrodes Rl', K3', ... are conn~cted ~o ~he output circui~ coa~i~ting of FET~ 78p and 78m to 83, etc., in a ~anner equivalent to the outpue circuit o Fig. 13.
S~ray capaci~anc~ exi8t8 betw~en the elec~rodes supplied w~h clsck ~ignal~ nd ~2 and eh~ channel, and ~he charging and di~eharg~ng of the ~tray cap~cieànce dep~ndd upo~ the level of th~ inco~ing ~ignal. Accordingly, by divlding the electrodes from w~ich ~ha outpu~ i~
deri~ed in the above circuitJ, the capacitance can be ~, .
' -.
divided in correspondence with the areas of the divided electrodeis. If a separate clock signal i8 ~upplied ~o ones of the divided electrodes, the ~eighted outputs can be terived similar to the bucket brigade devlce. The outputs are then added and delivered as the output signal.
Further, ~ince the operation of the filter of ~he invention ii~ the same as the operation of ~ n~rmal charge transfer device, the signal transferred through the bucXet bri~ade device, or charge coupled deYice, or ~, the CCD i3 unaffected.
Having described specific preferred embodiments -of th~ invention with reference to the accompanying dr~wingg, it i3 to be understood ~hat the invention is not limited to those precise ~mbodiments, and tha~ various chan~e~ and modifications may be effected therein by one skilled in the art without depar~ing from the scope or spirlt of the inventlon ~ d~fioed in the appended clalm-.
,~ .
Claims (13)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A filter circuit comprising:
a charge transfer device;
clock signal drive circuit means including means for supplying a clock signal to said charge transfer device;
said charge transfer device including a plurality of successive capacitive storage means for sequentially holding a charge level representing a time sampled input signal, each of said capacitive storage means having a first clocking electrode for receiving said clock signal so that said charge level is transferred from one to another of said capacitive storage means in succession in response to said clock signal;
a predetermined plurality of said plurality of capacitive storage means each including respective first and second capacitive portions, said respective first and second capacitive portions being connected in parallel with each other for said transfer from the repsective capacitive storage means to another of said capacitive storage means, said respective first and second capacitive portions having a selected capacitive ratio;
each of said first capacitive portions having a respective one of said first clocking electrodes for receiving said clock signal, and said second capacitive portions having respective second clocking electrodes;
a first connection point connected to a predeter-mined number of said second clocking electrodes;
a second connection point connected to a remaining number of said second clocking electrodes;
said clock signal drive circuit means further including first and second clock driver circuits operated in synchronism with said clock signal and connected to said first and second connection points, respectively;
current detecting means for detecting currents flowing through said first and second clock driver circuits, respectively, and output means for compounding the detected currents and deriving an output signal.
a charge transfer device;
clock signal drive circuit means including means for supplying a clock signal to said charge transfer device;
said charge transfer device including a plurality of successive capacitive storage means for sequentially holding a charge level representing a time sampled input signal, each of said capacitive storage means having a first clocking electrode for receiving said clock signal so that said charge level is transferred from one to another of said capacitive storage means in succession in response to said clock signal;
a predetermined plurality of said plurality of capacitive storage means each including respective first and second capacitive portions, said respective first and second capacitive portions being connected in parallel with each other for said transfer from the repsective capacitive storage means to another of said capacitive storage means, said respective first and second capacitive portions having a selected capacitive ratio;
each of said first capacitive portions having a respective one of said first clocking electrodes for receiving said clock signal, and said second capacitive portions having respective second clocking electrodes;
a first connection point connected to a predeter-mined number of said second clocking electrodes;
a second connection point connected to a remaining number of said second clocking electrodes;
said clock signal drive circuit means further including first and second clock driver circuits operated in synchronism with said clock signal and connected to said first and second connection points, respectively;
current detecting means for detecting currents flowing through said first and second clock driver circuits, respectively, and output means for compounding the detected currents and deriving an output signal.
2. A filter circuit according to claim 1, wherein said first clock driver circuit includes first and second comple-mentary transistors, each having first, second and control elec-trodes, said control electrodes of the first and second transis-tors being commonly connected for being driven in synchronism by said clock signal and said first electrodes thereof being commonly connected to said first connection point; said second clock driver circuit includes third and fourth complementary transistors, each having first, second and control electrodes, said control electrodes of the third and fourth transistors being commonly connected for being driven in synchronism by said clock signal and said first electrodes of the third and fourth transis-tors being commonly connected to said second connection point;
and said current detecting means being effective to detect cur-rents flowing through said second electrodes of said first and third transistors.
and said current detecting means being effective to detect cur-rents flowing through said second electrodes of said first and third transistors.
3. A filter circuit according to claim 2; wherein said complementary transistors are bipolar transistors each having a base, an emitter and a collector respectively constituting said control, first and second electrodes.
4. A filter circuit according to claim 3; wherein said complementary transistors both operate in active regions.
5. A filter circuit according to claim 2; wherein said complementary transistors are field-effect transistors each having a gate, a source and a drain respectively constituting said con-trol, first and second electrodes.
6. A filter circuit according to claim 2; wherein said output means includes capacitive means connected to said second electrode of said first transistor and also to said second elec-trode of said third transistor, said capacitive means being charged and discharged in response to both currents flowing through said first and third transistors; and said output signal being derived from said capacitive means.
7. A filter circuit according to claim 6; wherein said first and second clock driver circuits include another capa-citive means connected to at least one of said first electrodes of said first and third transistors, said other capacitive means having a capacitance effective to provide DC compensation.
8. A filter circuit according to claim 2; wherein said output means comprises current to voltage converting means connected to said second electrodes of said first and third tran-sistors; and a differential amplifier connected to said converting circuit for compounding voltages therefrom.
9. A filter circuit according to claim 2; wherein said current detecting means comprises a current mirror circuit including an input active device and an output active device, said current flowing through said first transistor being supplied to said input active device and a current in propor-tion to the current through said input active device flowing through said output active device as a detected current of said first transistor.
10. A filter circuit according to claim 9, wherein said current detecting means comprises another current mirror circuit including an input active device and an output active device, said current flowing through said third transistor being supplied to said input active device and a current in proportion to the current flowing through said input active device flowing through said output active device as a detected current of said third transistor.
11. A filter circuit according to claim 2; wherein said clock signal is composed of two phase clock signals, said first mentioned clocking electrode of each of said capacitive storage means receives one of said two phase clock signals; and each of said first and second clock driver circuits is operated in synchronism with one of said two phase clock signals.
12. A filter circuit according to claim 11; wherein said first clock driver circuit is operated in synchronism with one of said two phase clock signals, and said second clock driver circuit is operated in synchronism with the other of said two phase clock signals.
13. A charge transfer device according to claim 1;
wherein each of said capacitive storage means comprises a capa-citor having two electrodes, one of said two electrodes being said clocking electrode and the other of said two electrodes being a non-clocking electrode; and further comprising a plurality of transfer transistors of the same polarity, each of said transfer transistors being provided for controlling the transfer of charge from a respective one of said capacitors to a succeed-ing one of said capacitors and each having a control electrode, an input electrode and an output electrode, said transfer transistors being connected in series at their input and output electrodes, and said non-clocking and clocking electrodes of each of said capacitors being connected to the input and control electrodes; respectively, of a related one of the transfer transistors.
wherein each of said capacitive storage means comprises a capa-citor having two electrodes, one of said two electrodes being said clocking electrode and the other of said two electrodes being a non-clocking electrode; and further comprising a plurality of transfer transistors of the same polarity, each of said transfer transistors being provided for controlling the transfer of charge from a respective one of said capacitors to a succeed-ing one of said capacitors and each having a control electrode, an input electrode and an output electrode, said transfer transistors being connected in series at their input and output electrodes, and said non-clocking and clocking electrodes of each of said capacitors being connected to the input and control electrodes; respectively, of a related one of the transfer transistors.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8592/79 | 1979-01-26 | ||
| JP859279A JPS55100727A (en) | 1979-01-26 | 1979-01-26 | Noncyclic transversal filter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1125392A true CA1125392A (en) | 1982-06-08 |
Family
ID=11697246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA344,111A Expired CA1125392A (en) | 1979-01-26 | 1980-01-21 | Filter circuit utilizing charge transfer device |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US4308509A (en) |
| JP (1) | JPS55100727A (en) |
| AU (1) | AU532006B2 (en) |
| CA (1) | CA1125392A (en) |
| DE (1) | DE3002705A1 (en) |
| FR (1) | FR2447645B1 (en) |
| GB (1) | GB2042298B (en) |
| NL (1) | NL8000519A (en) |
Families Citing this family (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8400805A (en) * | 1984-03-14 | 1985-10-01 | Philips Nv | CHARGE COUPLED TRANSVERSAL FILTER. |
| US5111419A (en) * | 1988-03-23 | 1992-05-05 | Central Institute For The Deaf | Electronic filters, signal conversion apparatus, hearing aids and methods |
| US7106570B2 (en) * | 1997-04-08 | 2006-09-12 | Xzy Altenuators, Llc | Pathway arrangement |
| US7110227B2 (en) * | 1997-04-08 | 2006-09-19 | X2Y Attenuators, Llc | Universial energy conditioning interposer with circuit architecture |
| US6650525B2 (en) * | 1997-04-08 | 2003-11-18 | X2Y Attenuators, Llc | Component carrier |
| US6894884B2 (en) * | 1997-04-08 | 2005-05-17 | Xzy Attenuators, Llc | Offset pathway arrangements for energy conditioning |
| US6603646B2 (en) | 1997-04-08 | 2003-08-05 | X2Y Attenuators, Llc | Multi-functional energy conditioner |
| US7336467B2 (en) * | 2000-10-17 | 2008-02-26 | X2Y Attenuators, Llc | Energy pathway arrangement |
| US6018448A (en) * | 1997-04-08 | 2000-01-25 | X2Y Attenuators, L.L.C. | Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package |
| US7301748B2 (en) | 1997-04-08 | 2007-11-27 | Anthony Anthony A | Universal energy conditioning interposer with circuit architecture |
| US6606011B2 (en) * | 1998-04-07 | 2003-08-12 | X2Y Attenuators, Llc | Energy conditioning circuit assembly |
| US7336468B2 (en) | 1997-04-08 | 2008-02-26 | X2Y Attenuators, Llc | Arrangement for energy conditioning |
| WO1999052210A1 (en) * | 1998-04-07 | 1999-10-14 | X2Y Attenuators, L.L.C. | Component carrier |
| US7274549B2 (en) | 2000-12-15 | 2007-09-25 | X2Y Attenuators, Llc | Energy pathway arrangements for energy conditioning |
| US7110235B2 (en) * | 1997-04-08 | 2006-09-19 | Xzy Altenuators, Llc | Arrangement for energy conditioning |
| US7042703B2 (en) * | 2000-03-22 | 2006-05-09 | X2Y Attenuators, Llc | Energy conditioning structure |
| US9054094B2 (en) | 1997-04-08 | 2015-06-09 | X2Y Attenuators, Llc | Energy conditioning circuit arrangement for integrated circuit |
| US20030161086A1 (en) | 2000-07-18 | 2003-08-28 | X2Y Attenuators, Llc | Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package |
| US6636406B1 (en) | 1997-04-08 | 2003-10-21 | X2Y Attenuators, Llc | Universal multi-functional common conductive shield structure for electrical circuitry and energy conditioning |
| US7321485B2 (en) | 1997-04-08 | 2008-01-22 | X2Y Attenuators, Llc | Arrangement for energy conditioning |
| US7427816B2 (en) | 1998-04-07 | 2008-09-23 | X2Y Attenuators, Llc | Component carrier |
| US6157528A (en) * | 1999-01-28 | 2000-12-05 | X2Y Attenuators, L.L.C. | Polymer fuse and filter apparatus |
| SE516291C2 (en) * | 1999-06-15 | 2001-12-10 | Ericsson Telefon Ab L M | Switchable capacitors and method of weighting an input signal |
| US7113383B2 (en) * | 2000-04-28 | 2006-09-26 | X2Y Attenuators, Llc | Predetermined symmetrically balanced amalgam with complementary paired portions comprising shielding electrodes and shielded electrodes and other predetermined element portions for symmetrically balanced and complementary energy portion conditioning |
| US7262949B2 (en) * | 2000-08-15 | 2007-08-28 | X2Y Attenuators, Llc | Electrode arrangement for circuit energy conditioning |
| US7193831B2 (en) | 2000-10-17 | 2007-03-20 | X2Y Attenuators, Llc | Energy pathway arrangement |
| WO2002033798A1 (en) | 2000-10-17 | 2002-04-25 | X2Y Attenuators, Llc | Amalgam of shielding and shielded energy pathways and other elements for single or multiple circuitries with common reference node |
| US7180718B2 (en) | 2003-01-31 | 2007-02-20 | X2Y Attenuators, Llc | Shielded energy conditioner |
| WO2005002018A2 (en) | 2003-05-29 | 2005-01-06 | X2Y Attenuators, Llc | Connector related structures including an energy |
| EP1649572A4 (en) | 2003-07-21 | 2012-06-27 | X2Y Attenuators Llc | Filter assembly |
| CN1890854A (en) | 2003-12-22 | 2007-01-03 | X2Y艾泰钮埃特有限责任公司 | Internally shielded energy conditioner |
| WO2006104613A2 (en) | 2005-03-01 | 2006-10-05 | X2Y Attenuators, Llc | Conditioner with coplanar conductors |
| US7817397B2 (en) | 2005-03-01 | 2010-10-19 | X2Y Attenuators, Llc | Energy conditioner with tied through electrodes |
| WO2006099297A2 (en) | 2005-03-14 | 2006-09-21 | X2Y Attenuators, Llc | Conditioner with coplanar conductors |
| KR101390426B1 (en) | 2006-03-07 | 2014-04-30 | 엑스2와이 어테뉴에이터스, 엘.엘.씨 | Energy conditioner structures |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3474260A (en) * | 1966-10-10 | 1969-10-21 | South Pacific Co | Time domain equalizer using analog shift register |
| US3877056A (en) * | 1973-01-02 | 1975-04-08 | Texas Instruments Inc | Charge transfer device signal processing system |
| FR2302636A1 (en) * | 1975-02-28 | 1976-09-24 | Thomson Csf | ANALOGUE SIGNAL FILTERING PROCESS |
| DE2630085C3 (en) * | 1975-07-21 | 1978-07-13 | Hughes Aircraft Co., Culver City, Calif. (V.St.A.) | CCD transversal filter |
| US4195273A (en) * | 1976-10-29 | 1980-03-25 | Hughes Aircraft Company | CTD charge subtraction transversal filter |
-
1979
- 1979-01-26 JP JP859279A patent/JPS55100727A/en active Granted
-
1980
- 1980-01-18 US US06/113,401 patent/US4308509A/en not_active Expired - Lifetime
- 1980-01-21 CA CA344,111A patent/CA1125392A/en not_active Expired
- 1980-01-25 DE DE19803002705 patent/DE3002705A1/en not_active Withdrawn
- 1980-01-25 FR FR8001676A patent/FR2447645B1/en not_active Expired
- 1980-01-25 GB GB8002507A patent/GB2042298B/en not_active Expired
- 1980-01-28 NL NL8000519A patent/NL8000519A/en not_active Application Discontinuation
- 1980-01-29 AU AU55001/80A patent/AU532006B2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| AU532006B2 (en) | 1983-09-15 |
| DE3002705A1 (en) | 1980-08-07 |
| JPS55100727A (en) | 1980-07-31 |
| US4308509A (en) | 1981-12-29 |
| AU5500180A (en) | 1980-07-31 |
| JPS6313365B2 (en) | 1988-03-25 |
| FR2447645A1 (en) | 1980-08-22 |
| GB2042298B (en) | 1983-05-11 |
| NL8000519A (en) | 1980-07-29 |
| FR2447645B1 (en) | 1988-06-24 |
| GB2042298A (en) | 1980-09-17 |
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