CA1122721A - Linear semiconductor resistor - Google Patents
Linear semiconductor resistorInfo
- Publication number
- CA1122721A CA1122721A CA347,882A CA347882A CA1122721A CA 1122721 A CA1122721 A CA 1122721A CA 347882 A CA347882 A CA 347882A CA 1122721 A CA1122721 A CA 1122721A
- Authority
- CA
- Canada
- Prior art keywords
- resistance
- layer
- isolation layer
- resistor
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/40—Resistors
- H10D1/43—Resistors having PN junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/209—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/78—Simultaneous conversion using ladder network
- H03M1/785—Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders
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- Semiconductor Integrated Circuits (AREA)
Abstract
LINEAR SEMICONDUCTOR RESISTOR
ABSTRACT OF THE DISCLOSURE
A diffused semiconductor resistance structure having a resistance value that is practically indepen-dent of applied voltage. The novel structure of the invention, as it relates to the illustrative embodi-ment, includes an isolation layer diffused into an underlying substrate, a resistance layer diffused into the isolation layer, and a conductive element connect-ing the isolation layer to an electrical contact near the mid-point of the resistance layer. The junction between the resistance layer and the isolation layer is thereby zero-biased at its midpoint, is forward-biased on one side of the midpoint, and is reverse-biased on the other side of the midpoint. Consequently, the average thickness of a depletion region formed at the junction, and the average effective depth of the resistance layer, are maintained constant and practi-cally independent of applied voltage, to provide a resistance value that is also practically constant.
ABSTRACT OF THE DISCLOSURE
A diffused semiconductor resistance structure having a resistance value that is practically indepen-dent of applied voltage. The novel structure of the invention, as it relates to the illustrative embodi-ment, includes an isolation layer diffused into an underlying substrate, a resistance layer diffused into the isolation layer, and a conductive element connect-ing the isolation layer to an electrical contact near the mid-point of the resistance layer. The junction between the resistance layer and the isolation layer is thereby zero-biased at its midpoint, is forward-biased on one side of the midpoint, and is reverse-biased on the other side of the midpoint. Consequently, the average thickness of a depletion region formed at the junction, and the average effective depth of the resistance layer, are maintained constant and practi-cally independent of applied voltage, to provide a resistance value that is also practically constant.
Description
~lZZ'7Zl BACKGROUND OF THE INVENTION
This invention relates generally to integrated semiconductor circuits, and, more particularly, to resistance elements used in integrated circuits.
In the manufacture of integrated circuits, electrical resistance elements are typically fabricated by forming, such as by diffusion, a semiconductor resistance layer on an underlying material, which may be a substrate, the resistance layer being doped to provide a material of different semiconductor type from the underlying material. As is well known, semiconductor materials are basically either n type or p type, the n type materials being doped with a selected concentration of penta-valent atoms to provide a majority of free electrons as charge carriers, and the p type materials being doped with a selected concentration of trivalent atoms to provide a majority of free holes as charge carriers. For example, a resistance layer might be formed of n type material diffused into the surface of a p type substrate. Electrical contact with the n type resistance layer would be made at opposite end portions of the layer, and the resistance value provided by the layer would be dependent primarily on its dimensions. In general, such resistance layers are diffused to a constant depth, and the resistance value is determined by the width and length of the layer.
A fundamental problem with semiconductor resistance elements of this general type is that they have a non-linear voltage-current characteristic, i.e., the resistance value varies signifi-cantly as the voltage applied across the resistance element is varied. This phenomenon is sometimes referred to as a JFET effect, since the resistance layer and the adjacent substrate behave in a manner sililar to a junction field effect transistor (JFET).
In particular, a depletion region or space-charge region is formed along the junction between the n type resistance element and the p type substrate, and the thickness of this region varies according to the voltage difference across the junction. The depletion region, in effect, encroaches on the n type resistance layer, reduces its effective depth, and thereby increases the resistance of the layer significantly, The thickness of the depletion region at any point along the junction depends on the voltage across the junction at that point. Accordingly, the overall effect of the depletion region on the resistance value depends on the voltage levels applied to the resistance termin-als.
This problem of non-linearity has little or no effect on digital integrated circuits, since, in digital devices, the primary concern is with voltage or current thresholds rather than absolute values. In analog circuits, on the other hand, the absolute value of a current or voltage is important, and the non-linearity of a resistor can be a critical problem. For example, in a digital-to-analog converter, an analog output voltage is developed by controlling the current applied to a resistor network. If the resistance values vary significantly, the analog output voltage can be correspondingly in error, and the accuracy of the device is then in serious question.
By way of a more specific example, in a typical circuit involving digital-to-analog conversion a resistance element may be subject to voltages between zero and 1 volt, and the corresponding variation in resistance value over this range can be one or two percent. In a digital-to-analog converter having a twelve-bit resolution, i.e., having the capability of converting a twelve-bit input quantity to a corresponding analog signal, the least significant bit of the digital input has a weight of 1/4096, or approximately .025 percent. Thus, a resistance error of one percent is equivalent to approximately forty times the weight of the least significant bit, meaning that the accuracy ~ .
of the analog output signal is not consistent with the resolution of the digital input data, and the lower six bits of the twelve-bit input may be improperly interpreted ln the con-vers~on process.
Although it is possible to compensate for resistance non-linearity by means of external circuitry, or by employing a totally different fabrication process for the resistors, this is clearly contrary to the usual objective of providing a monolithic circuit at reasonable cost. Accordingly, there exists a critical need in the integrated circuit field for a semi-conductor resistance element that has a practically constant resistance value over a wide range of applied voltages. The present invention fulfills this need.
SUMMARY OF THE INVENTION
The present invention resides in a semiconductor resistor providing a practically constant resistance value over a substantial operating voltage range. Basically, and in general terms, the resistor of the invention comprises an isolation layer, and a semiconductor resistance layer formed adjacent to the isolation layer and having two electrical contacts disposed in it to provide resistor terminals, and a third electrical contact disposed a selected intermediate point between the first two, preferably midway between them. The resistor of the invention further comprises conducting means connecting the isolation layer with the third electrical contact in the resistance layer. The isolation layer is thereby maintained at a potential between the voltage levels applied to the resistor terminals, and the nature of the thickness of the depletion region thereby formed at the junction between the resistance layer and the isolation layer is such that the average effective depth of the resistance layer is maintained practically constant, regardless of variations in applied ~.
112;~ 2'1 terminal voltage. Accordingly, the resistance between the termlnals is also maintained practically constant.
It will be apparent that, in the resistor of the invention, the junction between the resistance layer and the isolation layer is reverse biased toward one end of the junction, and is forward~l biased toward the opposite end. A zero bias is maintained at the selected intermediate point along the junction, since the third electrical contact in the resistance layer is electrically connected to the isolation layer. The depletion region varies from a maximum thickness at the reverse-biased end of the junction to a minimum thickness at the forward-biased end of the junction.
An increase in thickness of the depletion region results in a decrease in the effective depth of the resistance layer, and vice versa. Thus, the sheet resistance of the resistance layer is greatest at the reverse-biased end and is least at the forward-biased end. However, the average effective depth of the resis-tance layer is approximately equal to the depth at the approxi-mate midpoint, which depth is held constant by the electrical connection to the isolation layer. Thus, when the voltages applied to the resistor terminals are varied, the thickness of the depletion layer also varies, but its average thickness is held practically constant, and the average effective depth of the resistance layer is also held practically constant.
In accordance with the method of the invention, a semiconductor resistor is manufactured by forming an isolation layer in a substrate or other underlying material, forming a resistance layer having a junction with the isolation layer, and forming four electrical contacts, of which two are terminal contacts in t~e resistance layer, a third is disposed between the first two, and a fourth is disposed in the isolation layer.
Finally, the third and fourth contacts are electrically connected, to maintain a zero-bias condition at an intermediate ~1227Zl point along the junction between the resistance layer and the isolation layer.
An important but avoidable limitation of the invention is that, if the voltages applied to the resistor terminals are such that the forward-biased end portion of the junction between the resistance layer and the isolation layer is biased into conduction, this will result in unwanted conduction of current from the resistance layer, and will clearly distort the intended resistance value significantly. Consequently, care must be taken to maintain the voltages across the resistance layer at such values that the junction between the resistance layer and the isolation layer is not forward-biased sufficiently to cause conduction of substantial current through the junction. In accordance with one aspect of the invention, this problem can be alleviated by utilizing a plurality of resistors, constructed in accordance with the invention and connected in series to reduce the voltage difference between the resistance layer and the isolation layer in each resistor.
It will be appreciated from the foregoing that the resistor of the present invention has application not only to digital-to-analog converters, but to any integrated circuitry in whichanalog signals are generated or processed. Other aspects and advantages of the invention will become apparent from the following more detailed description, taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a diagrammatic sectional view of a semiconductor diffused resistance region typical of the prior art;
FIG. 2 is a diagrammatic sectional view of the semiconductor resistor of the present invention;
FIG. 3 is an enlarged, fragmentary, diagrammatic sectional view of the resistance element of the invention, showing how the 1~2Z~7Zl average depth to the boundary of the depletion region is maintained substantially constant.
FIG. 4 is a diagrammatic sectional view showing four resistors constructed in accordance with the invention and connected in series to maintain the forward-bias voltage below undesirably high levels;
FIG. 5 is a diagrammatical sectional view of an alternate form of the semiconductcr reistor of the invention; and FIG. 6 is a simplified block diagram and schematic view of a digital-to-analog converter utilizing resistance elements constructed in accordance with the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
As shown in the ~rawings for purposes of illustration, the present invention is concerned with semiconductor resistive elements, and with the application of such elements to integrated circuits, such as digital-to-analog converters. As shown in FIG.
1, one common method of fabricating resistors in integrated circuits is by diffusing a resistance layer of one particular type of semiconductor material, such as the n type region designated by the reference numeral 10, into an underlying sub-strate material 12 of a different type, shown in FIG. 1 as a p type substrate. Electrical contacts 14 and 16 are located at opposite ends of the resistance layer 10, which has a resistance value dependent on the dimensions of the n type diffusion region forming the resistance layer. As is well known, a region known as a depletion region, or spacecharge region, is formed in the vicinity of a p-n junction, such as the one between the layers 10 and 12, when two such layers are placed in contact.
The depletion region is formed in part by the diffusion of free electrons from the n type material to the p type material, where the electrons each fill a fourth covalant bond in a p bype impurity atom in the p type region. Similarly, holes from the p type material diffuse across the junction and recombine with free electrons in the n type material. As a result, the depletion region is formed, comprising a layer of negative ions close to the junction on the p type side, and a layer of positive ions on the n type side of the junction. This depletion region presents a potential barrier to the flow of current across the junction, and accounts for the well known voltage-current characteristic of a p-n junction diode.
More importantly from the standpoint of the present invention, however, the depletion region has the effect of thin-ning the cross section of the resistance region 10, and thereby increasing its resistance value. The broken line 18 in FIG. 1 shows the approximate upper boundary of the depletion region in the n type material 10. It will be appreciated that the depletion region also extends into the substrate 12. In the condition shown in FIG. 1, with zero volts applied to the left-hand terminal 14 and -1.0 volt applied to the right-hand termin-al 16, the depletion region will be thinner at the right-hand end of the junction, since that end is reverse-biased to a lesser extent than the left-hand end, assuming that approximately -5.0 volts is applied to the substrate 12. As is also well known, when a reverse bias is applied across a p-n junction, the depletion region becomes significantly thicker. Accordingly, in the resistor shown in FIG. 1, if the voltage on the right-hand terminal 16 becomes less negative, the depletion region at the end of the junction near that terminal becomes thicker, and the overall resistance value increases correspondingly. It will be apparent that the resistance value will not be constant, but will depend upon the applied voltage and upon the differences between the terminal voltages and the electrical potential of the sub-strate region 12. The variations in resistance value can be one or two percent for a one-volt variation in applied voltage.
~' 1~2Z72~
Although this variation in resistance value is of little or no consequence in digital devices, which are normally operative on the basis a voltage or current threshold, resistance variations are often critically important in circuits that generate or process analog signals, such as digital-to-analog converters.
In accordance with the present invention as it relates to the illustrative embodiment shown in FIG. 2, a semiconductor resistance layer 20 is isolated from the substrate 12 by an isolation layer 22, and the potential applied to the isolation layer is the same as the potential at an lntermediate point along the resistance layer. In the exa~ple shown in FIG. 2, the isolation layer 22 is of n type material, and the resistance region 20 is of p+ type material. The resistance layer 20 has, as before, two electrical contacts 24 and 26 to provide resistor terminals, and in addition has a third electrical contact 28 situated approximately midway between the contacts 24 and 26.
The third contact 28 is connected by a conductive element 30 to a further electrical contact 32 in the isolation layer 22.
As in the prior art, the junction between the resistance layer 20 and the isolation layer 22 is subject to distortion by the depletion region, but with one important difference. Near the midpoint of the junction, the bias voltage between the two layers is held at zero, since the resistance layer 20 at this point and the isolation layer 22 are electrically tied together by the conductive element 30. Thus, the depth of the upper boundary of the depletion region at the midpoint is a zero-bias value, as indicated by the broken line 34 in FIG. 3. This line indicates the depth of the depletion region when zero voltage is applied to both the electrical contacts 24 and 26.
When different voltages are applied to the terminals 24 and 26, the zero-bias condition is still maintained at the midpoint between the contacts. If, for example, a zero voltage is .. .
`` 112Z7Zl applied to the left-hand terminal 24 and -1.0 volt is applied to the right-hand terminal 26, it will be apparent that the junction between the layers 20 and 22 is forward-biased to the left of the midpoint, and is reverse biased to the right of the midpoint.
Accordingly, the depth of the upper boundary of the depletion region will be as shown in FIG. 3 by the broken line 36. At the forward-biased end of the resistor, the potential barrier set up by the depletion region is partly overcome, while at the reverse-biased end the potential barrier is further reinforced. Although the extent of the depletion region is shown only approximately by the straight line boundary indicated in FIG. 3, the resistance at the forward-biased end of the layer 20 is increased by an amount approximately equivalent to that by which the resistance at the reverse-biased end of the resistance layer is decreased.
The line 36 indicating the extent of the depletion region is, in effect, pivoted about a fixed point in the zero-bias line 34, and the total resistance of the layer 20, between the contacts 24 and 26, remains substantially constant, regardless of variations in applied voltage. Another important benefit derived from use of the invention is that a resistor having an extremely low temperature coefficient of resistance is obtained. However, the reasons for this result are not entirely understood at this stage.
The only practical limitation of the invention as described with reference to FIGS. 2 and 3, is that the forward-biased end of the resistance layer 20 cannot be forwardly biased to such an extent that the potential barrier imposed by the depletion region is completely overcome. If this occurs, the junction between the resistance layer 20 and the isolation layer 22 becomes conductive, and the three regions, i.e. the resistance layer 20, the isolation layer 22 and the substrate 12, behave like a conductive transistor. Current that should be confined to the resistance layer 20 is then lost to the substrate 12, and _g_ llZ27Z~
the linearity of the resistance layer is clearly destroyed. To obviate this problem, resistors can be strung together in series, as indicated in FIG. 4. As this figure shows, a voltage of -1.0 volt is applied across a series string of four resistors formed in the same substrate 12'. The resistance layers are indicated at 20(a)-20(d), and the isolation layers are indicated at 22(a)-22(d). In the illustrative example, the maximum voltage across each of the resistors is limited to 0.25 volt, and the maximum forward-bias voltage in each resistor is limited to 0.125 volt. Since the latter figure is very much below 0.75 volt, which is the typical forward-bias voltage value at which a p-n junction becomes conductive, the problem posed by possible conduction through the junctions is avoided.
The resistance layer 20 and isolation layer 22 may be formed by a conventional diffusion process. Basically, in such a process each layer if diffused into the region below it, i.e., the isolation layer is diffused into the substrate and the resistance layer is diffused into the isolation layer. The areas of the layers are defined by photolith masks (not shown), used in conjunction with a conventional photoresist process.
It will be appreciated that the isolation layer 22 need not be interposed between the resistance layer 20 and a substrate, nor does the resistance layer have to be of p type material.
As shown in FIG. 5, an n~ type resistance layer 20', can be formed adjacent to a p+ isolation layer 22', which is itself formed adjacent to a separation layer 60 of n type material. The separation layer is, in turn, formed adjacent to the substrate 12.
Although the illustrative embodiments are related to a diffusion fabrication process, it will be appreciated that the invention is equally applicable to epitaxial and other semiconductor fabri-cation processes. The essential ingredient in all cases is a resistance layer, an adjaeent isolation layer, and an electrical ~1227Zl connection between the isolation layer and an intermediate point on the resistance layer between the resistor terminals.
FIG. 6 shows how the resistor of the invention may be applied to a digital-to-analog converter circuit. A mult~ple-stage digital input signal, indicated at 40, is clocked into aplurality of flip flops 42, and then passed through a digital buffer 44 under the control of appropriate clock signals. The digital signals are used to control a plurality of control switches, indicated diagrammatically at 46(a)-46(1). These switches control the flow of current from a corresponding plurality of constant current generators 48(a) - 48(1) into a resistance network, referred to as an R-2R ladder network. The resistance network in the illustrative circuit has twelve input terminals, indicated at 58(a-) - 58(1), and has a resistance R
connected between adjacent terminals, i.e., between terminals 58(a) and 58(b), between terminals 58(b) and 58(c), and so forth.
It also has a resistance R connected between each of the first and last input terminals 58(a) and 58(1) and ground, and a resistance 2R connected between every other input terminal and ground. As is well known, a resistance network of this type has the characteristic that the resistance as viewed from any of the input terminals is 2R/3.
An analog output voltage signal is derived from the input terminal 58(a), as shown at 60. If the current contri-bution from each of the current generators 48(a) - 48(1) is designated by I, the voltage contribution to the analog output signal from current generator 48(a) is I x 2R/3, and the voltage contribution to the output signal from current generator 48(b) is a I/2 x 2R/3. Similarly, the contribution from the third generator 48(c) is I/4 x 2R/3, and so on. Thus~ the network provides appropriate binary weighting of the digital input signals to the analog output signal. The switches 46(a) - 46(1) 11227~1 are controlled by the digital input signals, and switch the current from the generators 48(a)-48(1) either into the appropriate terminals of the ladder, or to corresponding termin-als of a dummy R-2R ladder (not shown), to maintain the symmetry of the circuit.
It will be apparent that the values of the resistors in the resistance network are critical to generation of an accurate analog signal, and that the resistor of the invention is well suited to maintain the linearity and accuracy of a digital-to-analog converter.
It will be appreciated from the foregoing that the present invention represents a significant advance in the field of integrated circuitry. In particular, it provides a semi-conductor resistor of which the resistance value is practically independent of applied voltage. It will also be appreciated that, although specific embodiments of the invention has been described in detail for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be limited except as by the appended claims.
This invention relates generally to integrated semiconductor circuits, and, more particularly, to resistance elements used in integrated circuits.
In the manufacture of integrated circuits, electrical resistance elements are typically fabricated by forming, such as by diffusion, a semiconductor resistance layer on an underlying material, which may be a substrate, the resistance layer being doped to provide a material of different semiconductor type from the underlying material. As is well known, semiconductor materials are basically either n type or p type, the n type materials being doped with a selected concentration of penta-valent atoms to provide a majority of free electrons as charge carriers, and the p type materials being doped with a selected concentration of trivalent atoms to provide a majority of free holes as charge carriers. For example, a resistance layer might be formed of n type material diffused into the surface of a p type substrate. Electrical contact with the n type resistance layer would be made at opposite end portions of the layer, and the resistance value provided by the layer would be dependent primarily on its dimensions. In general, such resistance layers are diffused to a constant depth, and the resistance value is determined by the width and length of the layer.
A fundamental problem with semiconductor resistance elements of this general type is that they have a non-linear voltage-current characteristic, i.e., the resistance value varies signifi-cantly as the voltage applied across the resistance element is varied. This phenomenon is sometimes referred to as a JFET effect, since the resistance layer and the adjacent substrate behave in a manner sililar to a junction field effect transistor (JFET).
In particular, a depletion region or space-charge region is formed along the junction between the n type resistance element and the p type substrate, and the thickness of this region varies according to the voltage difference across the junction. The depletion region, in effect, encroaches on the n type resistance layer, reduces its effective depth, and thereby increases the resistance of the layer significantly, The thickness of the depletion region at any point along the junction depends on the voltage across the junction at that point. Accordingly, the overall effect of the depletion region on the resistance value depends on the voltage levels applied to the resistance termin-als.
This problem of non-linearity has little or no effect on digital integrated circuits, since, in digital devices, the primary concern is with voltage or current thresholds rather than absolute values. In analog circuits, on the other hand, the absolute value of a current or voltage is important, and the non-linearity of a resistor can be a critical problem. For example, in a digital-to-analog converter, an analog output voltage is developed by controlling the current applied to a resistor network. If the resistance values vary significantly, the analog output voltage can be correspondingly in error, and the accuracy of the device is then in serious question.
By way of a more specific example, in a typical circuit involving digital-to-analog conversion a resistance element may be subject to voltages between zero and 1 volt, and the corresponding variation in resistance value over this range can be one or two percent. In a digital-to-analog converter having a twelve-bit resolution, i.e., having the capability of converting a twelve-bit input quantity to a corresponding analog signal, the least significant bit of the digital input has a weight of 1/4096, or approximately .025 percent. Thus, a resistance error of one percent is equivalent to approximately forty times the weight of the least significant bit, meaning that the accuracy ~ .
of the analog output signal is not consistent with the resolution of the digital input data, and the lower six bits of the twelve-bit input may be improperly interpreted ln the con-vers~on process.
Although it is possible to compensate for resistance non-linearity by means of external circuitry, or by employing a totally different fabrication process for the resistors, this is clearly contrary to the usual objective of providing a monolithic circuit at reasonable cost. Accordingly, there exists a critical need in the integrated circuit field for a semi-conductor resistance element that has a practically constant resistance value over a wide range of applied voltages. The present invention fulfills this need.
SUMMARY OF THE INVENTION
The present invention resides in a semiconductor resistor providing a practically constant resistance value over a substantial operating voltage range. Basically, and in general terms, the resistor of the invention comprises an isolation layer, and a semiconductor resistance layer formed adjacent to the isolation layer and having two electrical contacts disposed in it to provide resistor terminals, and a third electrical contact disposed a selected intermediate point between the first two, preferably midway between them. The resistor of the invention further comprises conducting means connecting the isolation layer with the third electrical contact in the resistance layer. The isolation layer is thereby maintained at a potential between the voltage levels applied to the resistor terminals, and the nature of the thickness of the depletion region thereby formed at the junction between the resistance layer and the isolation layer is such that the average effective depth of the resistance layer is maintained practically constant, regardless of variations in applied ~.
112;~ 2'1 terminal voltage. Accordingly, the resistance between the termlnals is also maintained practically constant.
It will be apparent that, in the resistor of the invention, the junction between the resistance layer and the isolation layer is reverse biased toward one end of the junction, and is forward~l biased toward the opposite end. A zero bias is maintained at the selected intermediate point along the junction, since the third electrical contact in the resistance layer is electrically connected to the isolation layer. The depletion region varies from a maximum thickness at the reverse-biased end of the junction to a minimum thickness at the forward-biased end of the junction.
An increase in thickness of the depletion region results in a decrease in the effective depth of the resistance layer, and vice versa. Thus, the sheet resistance of the resistance layer is greatest at the reverse-biased end and is least at the forward-biased end. However, the average effective depth of the resis-tance layer is approximately equal to the depth at the approxi-mate midpoint, which depth is held constant by the electrical connection to the isolation layer. Thus, when the voltages applied to the resistor terminals are varied, the thickness of the depletion layer also varies, but its average thickness is held practically constant, and the average effective depth of the resistance layer is also held practically constant.
In accordance with the method of the invention, a semiconductor resistor is manufactured by forming an isolation layer in a substrate or other underlying material, forming a resistance layer having a junction with the isolation layer, and forming four electrical contacts, of which two are terminal contacts in t~e resistance layer, a third is disposed between the first two, and a fourth is disposed in the isolation layer.
Finally, the third and fourth contacts are electrically connected, to maintain a zero-bias condition at an intermediate ~1227Zl point along the junction between the resistance layer and the isolation layer.
An important but avoidable limitation of the invention is that, if the voltages applied to the resistor terminals are such that the forward-biased end portion of the junction between the resistance layer and the isolation layer is biased into conduction, this will result in unwanted conduction of current from the resistance layer, and will clearly distort the intended resistance value significantly. Consequently, care must be taken to maintain the voltages across the resistance layer at such values that the junction between the resistance layer and the isolation layer is not forward-biased sufficiently to cause conduction of substantial current through the junction. In accordance with one aspect of the invention, this problem can be alleviated by utilizing a plurality of resistors, constructed in accordance with the invention and connected in series to reduce the voltage difference between the resistance layer and the isolation layer in each resistor.
It will be appreciated from the foregoing that the resistor of the present invention has application not only to digital-to-analog converters, but to any integrated circuitry in whichanalog signals are generated or processed. Other aspects and advantages of the invention will become apparent from the following more detailed description, taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a diagrammatic sectional view of a semiconductor diffused resistance region typical of the prior art;
FIG. 2 is a diagrammatic sectional view of the semiconductor resistor of the present invention;
FIG. 3 is an enlarged, fragmentary, diagrammatic sectional view of the resistance element of the invention, showing how the 1~2Z~7Zl average depth to the boundary of the depletion region is maintained substantially constant.
FIG. 4 is a diagrammatic sectional view showing four resistors constructed in accordance with the invention and connected in series to maintain the forward-bias voltage below undesirably high levels;
FIG. 5 is a diagrammatical sectional view of an alternate form of the semiconductcr reistor of the invention; and FIG. 6 is a simplified block diagram and schematic view of a digital-to-analog converter utilizing resistance elements constructed in accordance with the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
As shown in the ~rawings for purposes of illustration, the present invention is concerned with semiconductor resistive elements, and with the application of such elements to integrated circuits, such as digital-to-analog converters. As shown in FIG.
1, one common method of fabricating resistors in integrated circuits is by diffusing a resistance layer of one particular type of semiconductor material, such as the n type region designated by the reference numeral 10, into an underlying sub-strate material 12 of a different type, shown in FIG. 1 as a p type substrate. Electrical contacts 14 and 16 are located at opposite ends of the resistance layer 10, which has a resistance value dependent on the dimensions of the n type diffusion region forming the resistance layer. As is well known, a region known as a depletion region, or spacecharge region, is formed in the vicinity of a p-n junction, such as the one between the layers 10 and 12, when two such layers are placed in contact.
The depletion region is formed in part by the diffusion of free electrons from the n type material to the p type material, where the electrons each fill a fourth covalant bond in a p bype impurity atom in the p type region. Similarly, holes from the p type material diffuse across the junction and recombine with free electrons in the n type material. As a result, the depletion region is formed, comprising a layer of negative ions close to the junction on the p type side, and a layer of positive ions on the n type side of the junction. This depletion region presents a potential barrier to the flow of current across the junction, and accounts for the well known voltage-current characteristic of a p-n junction diode.
More importantly from the standpoint of the present invention, however, the depletion region has the effect of thin-ning the cross section of the resistance region 10, and thereby increasing its resistance value. The broken line 18 in FIG. 1 shows the approximate upper boundary of the depletion region in the n type material 10. It will be appreciated that the depletion region also extends into the substrate 12. In the condition shown in FIG. 1, with zero volts applied to the left-hand terminal 14 and -1.0 volt applied to the right-hand termin-al 16, the depletion region will be thinner at the right-hand end of the junction, since that end is reverse-biased to a lesser extent than the left-hand end, assuming that approximately -5.0 volts is applied to the substrate 12. As is also well known, when a reverse bias is applied across a p-n junction, the depletion region becomes significantly thicker. Accordingly, in the resistor shown in FIG. 1, if the voltage on the right-hand terminal 16 becomes less negative, the depletion region at the end of the junction near that terminal becomes thicker, and the overall resistance value increases correspondingly. It will be apparent that the resistance value will not be constant, but will depend upon the applied voltage and upon the differences between the terminal voltages and the electrical potential of the sub-strate region 12. The variations in resistance value can be one or two percent for a one-volt variation in applied voltage.
~' 1~2Z72~
Although this variation in resistance value is of little or no consequence in digital devices, which are normally operative on the basis a voltage or current threshold, resistance variations are often critically important in circuits that generate or process analog signals, such as digital-to-analog converters.
In accordance with the present invention as it relates to the illustrative embodiment shown in FIG. 2, a semiconductor resistance layer 20 is isolated from the substrate 12 by an isolation layer 22, and the potential applied to the isolation layer is the same as the potential at an lntermediate point along the resistance layer. In the exa~ple shown in FIG. 2, the isolation layer 22 is of n type material, and the resistance region 20 is of p+ type material. The resistance layer 20 has, as before, two electrical contacts 24 and 26 to provide resistor terminals, and in addition has a third electrical contact 28 situated approximately midway between the contacts 24 and 26.
The third contact 28 is connected by a conductive element 30 to a further electrical contact 32 in the isolation layer 22.
As in the prior art, the junction between the resistance layer 20 and the isolation layer 22 is subject to distortion by the depletion region, but with one important difference. Near the midpoint of the junction, the bias voltage between the two layers is held at zero, since the resistance layer 20 at this point and the isolation layer 22 are electrically tied together by the conductive element 30. Thus, the depth of the upper boundary of the depletion region at the midpoint is a zero-bias value, as indicated by the broken line 34 in FIG. 3. This line indicates the depth of the depletion region when zero voltage is applied to both the electrical contacts 24 and 26.
When different voltages are applied to the terminals 24 and 26, the zero-bias condition is still maintained at the midpoint between the contacts. If, for example, a zero voltage is .. .
`` 112Z7Zl applied to the left-hand terminal 24 and -1.0 volt is applied to the right-hand terminal 26, it will be apparent that the junction between the layers 20 and 22 is forward-biased to the left of the midpoint, and is reverse biased to the right of the midpoint.
Accordingly, the depth of the upper boundary of the depletion region will be as shown in FIG. 3 by the broken line 36. At the forward-biased end of the resistor, the potential barrier set up by the depletion region is partly overcome, while at the reverse-biased end the potential barrier is further reinforced. Although the extent of the depletion region is shown only approximately by the straight line boundary indicated in FIG. 3, the resistance at the forward-biased end of the layer 20 is increased by an amount approximately equivalent to that by which the resistance at the reverse-biased end of the resistance layer is decreased.
The line 36 indicating the extent of the depletion region is, in effect, pivoted about a fixed point in the zero-bias line 34, and the total resistance of the layer 20, between the contacts 24 and 26, remains substantially constant, regardless of variations in applied voltage. Another important benefit derived from use of the invention is that a resistor having an extremely low temperature coefficient of resistance is obtained. However, the reasons for this result are not entirely understood at this stage.
The only practical limitation of the invention as described with reference to FIGS. 2 and 3, is that the forward-biased end of the resistance layer 20 cannot be forwardly biased to such an extent that the potential barrier imposed by the depletion region is completely overcome. If this occurs, the junction between the resistance layer 20 and the isolation layer 22 becomes conductive, and the three regions, i.e. the resistance layer 20, the isolation layer 22 and the substrate 12, behave like a conductive transistor. Current that should be confined to the resistance layer 20 is then lost to the substrate 12, and _g_ llZ27Z~
the linearity of the resistance layer is clearly destroyed. To obviate this problem, resistors can be strung together in series, as indicated in FIG. 4. As this figure shows, a voltage of -1.0 volt is applied across a series string of four resistors formed in the same substrate 12'. The resistance layers are indicated at 20(a)-20(d), and the isolation layers are indicated at 22(a)-22(d). In the illustrative example, the maximum voltage across each of the resistors is limited to 0.25 volt, and the maximum forward-bias voltage in each resistor is limited to 0.125 volt. Since the latter figure is very much below 0.75 volt, which is the typical forward-bias voltage value at which a p-n junction becomes conductive, the problem posed by possible conduction through the junctions is avoided.
The resistance layer 20 and isolation layer 22 may be formed by a conventional diffusion process. Basically, in such a process each layer if diffused into the region below it, i.e., the isolation layer is diffused into the substrate and the resistance layer is diffused into the isolation layer. The areas of the layers are defined by photolith masks (not shown), used in conjunction with a conventional photoresist process.
It will be appreciated that the isolation layer 22 need not be interposed between the resistance layer 20 and a substrate, nor does the resistance layer have to be of p type material.
As shown in FIG. 5, an n~ type resistance layer 20', can be formed adjacent to a p+ isolation layer 22', which is itself formed adjacent to a separation layer 60 of n type material. The separation layer is, in turn, formed adjacent to the substrate 12.
Although the illustrative embodiments are related to a diffusion fabrication process, it will be appreciated that the invention is equally applicable to epitaxial and other semiconductor fabri-cation processes. The essential ingredient in all cases is a resistance layer, an adjaeent isolation layer, and an electrical ~1227Zl connection between the isolation layer and an intermediate point on the resistance layer between the resistor terminals.
FIG. 6 shows how the resistor of the invention may be applied to a digital-to-analog converter circuit. A mult~ple-stage digital input signal, indicated at 40, is clocked into aplurality of flip flops 42, and then passed through a digital buffer 44 under the control of appropriate clock signals. The digital signals are used to control a plurality of control switches, indicated diagrammatically at 46(a)-46(1). These switches control the flow of current from a corresponding plurality of constant current generators 48(a) - 48(1) into a resistance network, referred to as an R-2R ladder network. The resistance network in the illustrative circuit has twelve input terminals, indicated at 58(a-) - 58(1), and has a resistance R
connected between adjacent terminals, i.e., between terminals 58(a) and 58(b), between terminals 58(b) and 58(c), and so forth.
It also has a resistance R connected between each of the first and last input terminals 58(a) and 58(1) and ground, and a resistance 2R connected between every other input terminal and ground. As is well known, a resistance network of this type has the characteristic that the resistance as viewed from any of the input terminals is 2R/3.
An analog output voltage signal is derived from the input terminal 58(a), as shown at 60. If the current contri-bution from each of the current generators 48(a) - 48(1) is designated by I, the voltage contribution to the analog output signal from current generator 48(a) is I x 2R/3, and the voltage contribution to the output signal from current generator 48(b) is a I/2 x 2R/3. Similarly, the contribution from the third generator 48(c) is I/4 x 2R/3, and so on. Thus~ the network provides appropriate binary weighting of the digital input signals to the analog output signal. The switches 46(a) - 46(1) 11227~1 are controlled by the digital input signals, and switch the current from the generators 48(a)-48(1) either into the appropriate terminals of the ladder, or to corresponding termin-als of a dummy R-2R ladder (not shown), to maintain the symmetry of the circuit.
It will be apparent that the values of the resistors in the resistance network are critical to generation of an accurate analog signal, and that the resistor of the invention is well suited to maintain the linearity and accuracy of a digital-to-analog converter.
It will be appreciated from the foregoing that the present invention represents a significant advance in the field of integrated circuitry. In particular, it provides a semi-conductor resistor of which the resistance value is practically independent of applied voltage. It will also be appreciated that, although specific embodiments of the invention has been described in detail for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be limited except as by the appended claims.
Claims (15)
1. A semiconductor resistor having a resistance value practically independent of applied voltage, said resistor comprising:
an isolation layer;
a resistance layer formed adjacent to and having a junction with said isolation layer;
a pair of electrical terminal contacts spaced apart in said resistance layer, to provide resistor terminals;
a third electrical contact disposed in said resistance layer at an intermediate point between said terminal contacts;
and conductive means connecting said isolation layer to said third electrical contact;
whereby the junction between said isolation layer and said resistance layer is always zero-biased at the intermediate point, and the average effective depth of said resistance layer is maintained approximately constant, independent of terminal voltage.
an isolation layer;
a resistance layer formed adjacent to and having a junction with said isolation layer;
a pair of electrical terminal contacts spaced apart in said resistance layer, to provide resistor terminals;
a third electrical contact disposed in said resistance layer at an intermediate point between said terminal contacts;
and conductive means connecting said isolation layer to said third electrical contact;
whereby the junction between said isolation layer and said resistance layer is always zero-biased at the intermediate point, and the average effective depth of said resistance layer is maintained approximately constant, independent of terminal voltage.
2. A semiconductor resistor as set forth in claim 1, wherein said resistor is connected in series with at least one other similarly constructed resistor, to minimize the forward-bias voltage applied across the junctions between said isolation and resistance layers.
3. A semiconductor resistor as set forth in claim 1, wherein said third electrical contact is approximately midway between said terminal contacts.
4. A semiconductor resistor having a resistance value practically independent of applied voltage, said resistor comprising:
an isolation layer;
a resistance layer formed adjacent to and having a junction with said isolation layer, and having two resistor terminal contacts; and means for maintaining a depletion region of approximately constant average thickness along the junction between said isolation layer and said resistance layer, and thereby maintain-ing an approximately constant average effective depth of said resistance layer.
an isolation layer;
a resistance layer formed adjacent to and having a junction with said isolation layer, and having two resistor terminal contacts; and means for maintaining a depletion region of approximately constant average thickness along the junction between said isolation layer and said resistance layer, and thereby maintain-ing an approximately constant average effective depth of said resistance layer.
5. A semiconductor resistor as set forth in claim 3, wherein said means for maintaining a depletion region of approximately constant average thickness includes conductive means for electrically connecting said isolation layer to said resistance layer at an intermediate point between said terminal contacts, whereby the junction is always zero-biased at the intermediate point.
6. A semiconductor resistor as set forth in claim 5, wherein the intermediate point is approximately midway between said terminal contacts.
7. A semiconductor resistor having a resistance value practically independent of applied voltage, said resistor comprising:
a portion of a substrate of a semiconductor material having a majority of charge carriers of a particular polarity;
an isolation layer diffused into said substrate and being of a semiconductor material having a majority of charge carriers of the opposite polarity to that of said substrate material;
a resistance layer diffused into said isolation layer and being of a semiconductor material having a majority of charge carriers of the opposite polarity to that of said isolation layer material;
two electrical contacts disposed in said resistance layer to provide resistor terminals;
a third electrical contact also disposed in said resistance layer, approximately midway between said first two electrical contacts; and conductive means connecting said third electrical contact electrically with said isolation layer;
whereby a zero-bias voltage is maintained between said resistance layer and said isolation layer, midway between the resistor terminals, and a depletion region of substantially con-stant average thickness is maintained at the junction between said resistance and isolation layers.
a portion of a substrate of a semiconductor material having a majority of charge carriers of a particular polarity;
an isolation layer diffused into said substrate and being of a semiconductor material having a majority of charge carriers of the opposite polarity to that of said substrate material;
a resistance layer diffused into said isolation layer and being of a semiconductor material having a majority of charge carriers of the opposite polarity to that of said isolation layer material;
two electrical contacts disposed in said resistance layer to provide resistor terminals;
a third electrical contact also disposed in said resistance layer, approximately midway between said first two electrical contacts; and conductive means connecting said third electrical contact electrically with said isolation layer;
whereby a zero-bias voltage is maintained between said resistance layer and said isolation layer, midway between the resistor terminals, and a depletion region of substantially con-stant average thickness is maintained at the junction between said resistance and isolation layers.
8. A semiconductor resistor having a resistance value practically independent of applied voltage, said resistor comprising:
a portion of a substrate of a semiconductor material having a majority of charge carriers of a particular polarity;
a first isolation layer diffused into said substrate and being of a semiconductor material having a majority of charge carriers of the opposite polarity to that of said substrate material;
a second isolation layer diffused into said first isolation layer and being of a semiconductor material having a majority of charge carriers of the opposite polarity to that of said first isolation layer material;
a resistance layer diffused into said second isolation layer and being of a semiconductor material having a majority of charge carriers of the opposite polarity to that of said second isolation layer material;
two electrical contacts disposed in said resistance layer to provide resistor terminals;
a third electrical contact also disposed in said resistance layer, approximately midway between said first two electrical contacts; and conductive means connecting said third electrical contact electrically with said second isolation layer;
whereby a zero-bias voltage is maintained between said resistance layer and said isolation layer, midway between the resistor terminals, and a depletion region of substantially constant average thickness is maintained at the junction between said resistance and isolation layers.
a portion of a substrate of a semiconductor material having a majority of charge carriers of a particular polarity;
a first isolation layer diffused into said substrate and being of a semiconductor material having a majority of charge carriers of the opposite polarity to that of said substrate material;
a second isolation layer diffused into said first isolation layer and being of a semiconductor material having a majority of charge carriers of the opposite polarity to that of said first isolation layer material;
a resistance layer diffused into said second isolation layer and being of a semiconductor material having a majority of charge carriers of the opposite polarity to that of said second isolation layer material;
two electrical contacts disposed in said resistance layer to provide resistor terminals;
a third electrical contact also disposed in said resistance layer, approximately midway between said first two electrical contacts; and conductive means connecting said third electrical contact electrically with said second isolation layer;
whereby a zero-bias voltage is maintained between said resistance layer and said isolation layer, midway between the resistor terminals, and a depletion region of substantially constant average thickness is maintained at the junction between said resistance and isolation layers.
9. A monolithic digital-to-analog converter, comprising:
digital register means for receiving digital input signals to be converted to analog signals;
constant-current generator means switchable in accordance with the states of the digital input signals in said digital register means;
resistance ladder means coupled to said constant-current generator means, for generating an analog signal corresponding to the digital input signals, said resistance ladder means having semiconductor resistors each of which includes a semiconductor isolation layer, a resistance semiconductor layer having a junction with said isolation layer, a pair of electrical contacts disposed in said resistance layer to form resistor terminals, and means for electrically connecting said isolation layer to said resistance layer at an intermediate point between said electrical contacts, whereby said resistors have resistance values that are practically independent of applied voltage.
digital register means for receiving digital input signals to be converted to analog signals;
constant-current generator means switchable in accordance with the states of the digital input signals in said digital register means;
resistance ladder means coupled to said constant-current generator means, for generating an analog signal corresponding to the digital input signals, said resistance ladder means having semiconductor resistors each of which includes a semiconductor isolation layer, a resistance semiconductor layer having a junction with said isolation layer, a pair of electrical contacts disposed in said resistance layer to form resistor terminals, and means for electrically connecting said isolation layer to said resistance layer at an intermediate point between said electrical contacts, whereby said resistors have resistance values that are practically independent of applied voltage.
10. A monolithic digital-to-analog converter as set forth in claim 9, wherein the intermediate point is approximately mid-way between said electrical contacts.
11. A monolithic digital-to-analog converter as set forth in claim 9, wherein:
said isolation layer is of n type semiconductor material, diffused into a p type substrate; and said resistance layer is of p+ type semiconductor material, diffused into said isolation layer.
said isolation layer is of n type semiconductor material, diffused into a p type substrate; and said resistance layer is of p+ type semiconductor material, diffused into said isolation layer.
12. A semiconductor resistor having a resistance value practically independent of applied voltage, said resistor comprising:
an isolation layer;
a resistance layer formed adjacent to and having a junction with said isolation layer; and means coupling said isolation layer and said resistance layer in such a manner as to maintain a constant average effective depth of said resistance layer.
an isolation layer;
a resistance layer formed adjacent to and having a junction with said isolation layer; and means coupling said isolation layer and said resistance layer in such a manner as to maintain a constant average effective depth of said resistance layer.
13. A method of fabricating a semiconductor resistor having a resistance value that is practically independent of applied voltage, said method comprising the steps of:
forming a semiconductor isolation layer having a junction with a semiconductor substrate;
forming a semiconductor resistance layer having a junction with the isolation layer;
forming a first and second of electrical contacts in the resistance layer, to provide resistor terminals;
forming a third electrical contact in the resistance layer at an intermediate point between the first and second electrical contacts, and a fourth electrical contact in the isolation layer; and electrically connecting the third and fourth electrical contacts, to provide a zero-bias condition at an intermediate point along the junction between the isolation layer and the resistance layer.
forming a semiconductor isolation layer having a junction with a semiconductor substrate;
forming a semiconductor resistance layer having a junction with the isolation layer;
forming a first and second of electrical contacts in the resistance layer, to provide resistor terminals;
forming a third electrical contact in the resistance layer at an intermediate point between the first and second electrical contacts, and a fourth electrical contact in the isolation layer; and electrically connecting the third and fourth electrical contacts, to provide a zero-bias condition at an intermediate point along the junction between the isolation layer and the resistance layer.
14. A method as set forth in claim 13, wherein said third electrical contact is formed approximately midway between said first and second electrical contacts.
15. A method as set forth in claim 14, wherein said steps of forming the isolation and resistance layers are diffusion steps.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US2182979A | 1979-03-19 | 1979-03-19 | |
| US021,829 | 1979-03-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1122721A true CA1122721A (en) | 1982-04-27 |
Family
ID=21806386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA347,882A Expired CA1122721A (en) | 1979-03-19 | 1980-03-18 | Linear semiconductor resistor |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS55146957A (en) |
| CA (1) | CA1122721A (en) |
| DE (1) | DE3009042A1 (en) |
| FR (1) | FR2452180A1 (en) |
| GB (1) | GB2044998A (en) |
| SE (1) | SE8002073L (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2054997B (en) * | 1979-05-23 | 1984-01-18 | Suwa Seikosha Kk | Temperature detecting circuit |
| JPS57162356A (en) * | 1981-03-30 | 1982-10-06 | Toshiba Corp | Integrated circuit device |
| JPS58141551A (en) * | 1982-02-17 | 1983-08-22 | Nec Corp | Semiconductor device |
| JPS59229857A (en) * | 1983-06-07 | 1984-12-24 | Rohm Co Ltd | resistance circuit |
| JPS60139306U (en) * | 1984-02-25 | 1985-09-14 | 株式会社村田製作所 | High frequency device using coaxial resonator |
| DE3443773A1 (en) * | 1984-11-30 | 1986-06-05 | Robert Bosch Gmbh, 7000 Stuttgart | Monolithically integrated voltage divider |
| DE3526461A1 (en) * | 1985-07-24 | 1987-01-29 | Telefunken Electronic Gmbh | RESISTANCE CHAIN |
| JPS61172364A (en) * | 1985-09-27 | 1986-08-04 | Nec Corp | Semiconductor device to which constant voltage circuit is formed |
| JPS63244765A (en) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | Integrated circuit with diffused resistance |
| JPH0434173Y2 (en) * | 1987-10-27 | 1992-08-14 | ||
| US6593869B1 (en) * | 2002-03-28 | 2003-07-15 | Hrl Laboratories, Llc | High efficiency, high output drive current switch with application to digital to analog conversion |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2351505A1 (en) * | 1976-05-13 | 1977-12-09 | Ibm France | PROCEDURE FOR CORRECTING THE TENSION COEFFICIENT OF SEMICONDUCTOR, IMPLANTED OR DIFFUSED RESISTORS |
-
1980
- 1980-03-08 DE DE19803009042 patent/DE3009042A1/en not_active Withdrawn
- 1980-03-12 GB GB8008322A patent/GB2044998A/en not_active Withdrawn
- 1980-03-17 SE SE8002073A patent/SE8002073L/en unknown
- 1980-03-18 CA CA347,882A patent/CA1122721A/en not_active Expired
- 1980-03-18 JP JP3468380A patent/JPS55146957A/en active Granted
- 1980-03-18 FR FR8006016A patent/FR2452180A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| GB2044998A (en) | 1980-10-22 |
| JPS55146957A (en) | 1980-11-15 |
| JPS6356707B2 (en) | 1988-11-09 |
| SE8002073L (en) | 1980-09-20 |
| FR2452180A1 (en) | 1980-10-17 |
| DE3009042A1 (en) | 1980-10-02 |
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