CA1117193A - Microminiature electrical delay line utilizing thin film inductor array with magnetic enhancement and coupling - Google Patents
Microminiature electrical delay line utilizing thin film inductor array with magnetic enhancement and couplingInfo
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- CA1117193A CA1117193A CA000323445A CA323445A CA1117193A CA 1117193 A CA1117193 A CA 1117193A CA 000323445 A CA000323445 A CA 000323445A CA 323445 A CA323445 A CA 323445A CA 1117193 A CA1117193 A CA 1117193A
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Abstract
1.
ABSTRACT OF THE DISCLOSURE
A microminiature electrical delay line utilizes an m-derived filter formed by depositing a film of per-malloy or other high permeability metal on a quartz or other dielectric substrate, then depositing a layer of quartz or other dielectric over the permalloy film, after which a plurality of microminiature thin film inductance coils are deposited on the dielectric layer and joined together electrically in series, a top layer of quartz or other dielectric then is deposited over the intercon-nected coils and a strip of permalloy or other high per-meability metal is deposited over the top dielectric lay-er to extend across the coils, a gap being provided in the strip of permalloy at the central axis of each coil.
ABSTRACT OF THE DISCLOSURE
A microminiature electrical delay line utilizes an m-derived filter formed by depositing a film of per-malloy or other high permeability metal on a quartz or other dielectric substrate, then depositing a layer of quartz or other dielectric over the permalloy film, after which a plurality of microminiature thin film inductance coils are deposited on the dielectric layer and joined together electrically in series, a top layer of quartz or other dielectric then is deposited over the intercon-nected coils and a strip of permalloy or other high per-meability metal is deposited over the top dielectric lay-er to extend across the coils, a gap being provided in the strip of permalloy at the central axis of each coil.
Description
1~L7193 MICROMINIATURE: ELECTRICAL DELAY LINE UTILIZING
T~IIN FILM INDUCTOR ARRAY WLTII MAGNETIC
ENHANCEMENT AND COUPLING
BACKGROUND OF I~E INVENTION
This invention relates to electrical delay lines, and more particularly to a delay line in micro-miniature form suitable for hybrid circuit applications.
There are available in the market place many electrical delay lines in the form of standard dual-in-line integrated circuit packages. However, there is not available a delay line in chip form suitable for hybrid circuit applications.
SUMMARY OF T~IE INVENTION
In its basic concept, this invention provides an electri/cal delay line in which at least one pair of ~ series-connected, microminiature, inductance coils is ;~; interposed between films of dielectric material which, in turn, are interposed between films of permalloy or 15 other high permeability metal, one of the latter fiLms forming a strip which extends across the inductance coils ~ ..
~' .
~17193 ancl ls lnterrl.lpted at each coil to form a gap a-t the central axls of each coi.:l.
Thus a microminiature elec-trical delay line suit-able for hybrid circuit applications comprises the solid, one piece, lnteyra-ted assembly of:
a) a Eirst film of high permeabili-ty metal, b) a Eirst film of dielectric material overlying and bonded to the first f:ilm of hiyh permeability metal, c) a plurali-ty of series connected microminature in-ductance coils overlying and bonded to the first film of dielectric material, d) a second film of dielectric material overlying and bonded to the inductance coils, and e) a second film of high permeability metal in the form of a narrow strip overlying and bonded to the second film of dielectric material and extend-ing along the center line of the series-connected coils, the second film being interrupted at each coil to form a gap at the axis of each coil.
BRIEF DESCRIPTION OF THE DRAWING
Fig. 1 is a fragmentary plan view, on an enlarged scale, of an electrical delay line embodying the features of this invention.
Fig. 2 is a fragmentary sectional view taken on the line 2-2 in Fig. 1. j'~
: - 3 -" ~
L7~L~3 Fiy. 3 is a sect.ional view shc)winy on an enlarged scale a preferrecl constructi.on Oe ~n inductance coil form- I
ing a part of the delay line.
Fig. 4 :is a plan view of a delay line in chip form, e~odying -the features of this invention.
Fiy. 5 is a schema-tic diagram of an interminate number of sections of an m derived filter utilized - 3a -.~
,, ~
~1~7~3 for the delay linc of this inventlun.
Figs. 6-15 are plan ~lews showlng, ln diagrammatic form, the preferred sequential steps in the ~ormation of the inductance coil shown in Fig. 3.
DESCRIPTION OF THE PRE~E~RED EMBO~IMENT
As illustrated ln ~ig. 5, the delay llne o~ thls invention utilizes an m-derived filter a sec~lon of whlch lncludes a pair of series-connected inductance coils 8 (Figs. 1-4) each providing an inductance L
and ha~ing mutual lnductance M between them, and a sllunting capacltance Cl. The delay line may include any number of such sectlons as desired, limited only by the attenuation or loss that can be tolerated, In accordance with this inventlon~ the delay line is constructed and supported upon a substrate 10 of quart~, glass or other dielectric material, preferably suitable Por the thin film deposition of the delay line components as described herelnafter, For purposes o~ this invention, thin film deposition is understood to include depositions by printed circuit techniques as well as vapor deposition techniques.
Preferred a~ong these is ~he vapor deposi~ion method described in U.S.
Letters Patent No. 3,785,046 issued January 15, 1974 to Thomas A. Jennings.
By this technique the various films are applied by means of masks which delineate the shapes of areas upon which the ~apors depositions o~
conductive metal and dielectric material are to be made.
A
i ' , I
~ ~ 4 ~ I
7~1l93 As illustrated~ a film 12 of permalloy, mu-metal) or other suitable high permeability metal, is de posited upon and bonded integrally to one entire surface of the substrate 10. This film serves as a return path of the magnetic circuit and also as the ground plane for the delay line capacita~ es. A suitable thickness for this film is approximately S,()00 Angstroms.
Deposited upon and bonded integrally to the ~entire area of film 12 of high permeability metal is a 10 film 14 of silicon oxide, silicon nitrite, quartz, or other suitable dielectric material. As discussed here~
inafter, the thickness of this film may be varied.
Next, a pair of electrically conductive termin-als 16 and 18 are deposited upon the dielectric film 14, 15 adjacent one side of the substrate, for use in connect-ing the delay line to associated hybrid circuits. If desired, these terminals may be extended to the back ~; side of the substrate 10 to accommodate the mounting of hybrid circuitry on said back side. The high permeabili-20 ty metal ground plane 12 serves effectively to isolate the hybrid circuitry from the delay line.
Next, at least one pair of microminiature in~
ductance coils 8 is mounted upon and bonded integrally to the dielectric layer 14. As illustrated in Fig. 4, ; 25 ten such inductance coils are spaced apart on the~sub-strate in two rows.
In Fig. 3, each coil is shown t~ include a ' .;
~ ~7 ~ 3 plurality of superlmposed coaxial turns 20 of electri- ;
cally conductive metal film with adjacent turns iso-lated electrically from each other by an interposed film 22 of dielectric material. The innermost and outer-most turns are extended laterally in opposite direct-ions to provide end terminals 24 and 26.
All of the inductance coils 8 forming the de-lay line, ten of them as exemplified in Fig. 4, are form-ed simultaneously, but spacecl apart in the desired pat-10 tern, by appropriately constructed masks. Figs. 6-15 il-lustrate diagrammatically the sequential steps utilized in the formation of the inductance coil illustrated in Fig. 3. Thus, a first mask is utilized to provide the vapor deposition of the initial electrically conductive 15 coil turn segment 30. In the illustrated embodiment,this segment includes the laterally projecting end terminal 24 a portion of which overlies a portion of one of the end terminals 16 and 18, for example terminal 18.
Next3 by appropriate masking, a film of quartz s 20 or other suitable dielectric material 32 is vapor depos-ited over an intermediate portion of the segment 30 (Fig. 6) 7 leaving a leading end portion of the segment exposed for conductive connection of a trailing end por-tion of the next conductive turn segment 34 (Fig. 7).
25 This latter segment overlies the dielectric film 32.
Next,~a second deposition of dielectric film 36 (Fig. 8) is applied over the trailing portion of the ¦ conductive segment 34. The mask providing this deposi-:i ~
~L~17~93 ~ion i5 substantially identical to the mask providing the ~irst dielectric deposition 32, with the patte~n rotated 180 so as to expose the lead:ing end portion o~ the un-derlying conductive segment 34 for conductive connection 5 to the trailing end portion of the next succeeding con-ductive segment 38. The shape of this latter segment is substantially identical to the shape of the next preced-ing conductive segment 34, bul rotated 180, as will be apparent.
Subsequent dielectric ~ilms 40, 44, 48, 52, 56, 60 and 64 and conductive segments 42, 46, 50, 54, 58 and 62 are deposited al~ernately (Fig. 9~14), utilizing the masks which provided the depositions of the dielect-ric films and conductive film segments described herein-15 before, to complete the desired number of turns for eachinductance coil 8. In the embodiment illustrated in Figs.
; 6-15, the sequence provides for the deposition of four and one-half turns of conductive metal, with each turn separa-ted electrically from each other by an interposed film of 20 dielectric material.
The coil is completed with the addition of ~ the final conductive turn segment 66 and integrated end ; terminal 26 opposite the starting end terminal 24. As in-dicated in Fig. 15, this is achieved by utilizing a mask 25 having an aperture shaped like that of the mask which pro-vided the first turn segment 30 and connected end termin-al 24, but rotated 180~.
It will be understood, of course, that in the production of the delay line illustrated in Fig.`4, where-9 ~
in ten spaced inductance coils are provided, the masks re-ferred to in describing the sequence illustrated in Figs.
6-15, contain shaped openings necessary for the simultane-ous depositions required for the production of the ten in- i ductance coils.
The end terminal 26 on the final induc~ance coil 8, opposite the initial coil, is deposited in over-lapping, conductive engagement with the second o~ the pair of terminals 16 and 18, for example terminal 16, initially deposited on the dielectric film 14, as will be understood.
The confronting end terminals 24, 26 of ad-jacent coils 8 are interconnected electrically by means of a link 68 of electrically conductive metal film, such as aluminum, gold, or other suitable metal. The plurality of coils thus are connected together electrically in ser-ies.
Next a second film 70 of silicon oxide,quartz, or other~suitable dielectric material, is deposited over the series-connected inductance coils 8, as well as t~e interconnecting links 68 and the adjacent first film 14 of dielectric materLa]. This film 70 terminates short of the end terminals 16 and 18, as illustrated in Fig. 4.
Finally, an elongated strip 72 of permalloy, or other high permeability metaL, is deposited as a film, also suitably about 5,000 Angstroms thick, over the se-cond layer 70 of dielectric material, extending along the centerline of the;series-connected coils 8. This narrow~
strip of high permeability metal lS interrupted at each 9.
coil to form a gap 74 at the axis of each coil. In this latter regard, it is to be noted that the coil. turns are stacked one upon another concentrically about a central axis which is disposed perpendicularly to the supporting : 5 surface of the substrate 10.
The strip 72 of permalloy or other high per-meability metal which extends between centers of adjacent inductance coil cooperates with the film 12 of high per-meability metal underlying the coils to provide the mutual lO inductance M required. The desired value of mutual induct-ance is obtained by varying the width of the strip 72 and the length of the gaps 74 at the centers of the coils.
The`thickness of the dielectric layers 14 and 70 also af-fects the mutual inductance.
The capacitance Cl per section of the delay - line is provided by the capacitance between the high pe~-- meability metal ground plane 12 and the underside of the - inductance coil, including the area of the end terminals ~: 24 and 26 and the link 68 interconnecting the confront-20 ing end terminals of a pair of adjacent inductance coils.
: This capacitance may be varied by changing the thickness ~ of the dielectric layer 14 above the ground plane and the ; area of the conductive link 68.
The following illustrates a typical delay 25 line: Let it he assumed that the inductance, Ll of the filter is 45 nh. For an m~derived filter having a char-~acteristic impedance, ZO~ the relationships among Ll, Cl, ànd ZO are as follows:
~l17~3 10, ~ZO ~ C; Ll= .515 L; Cl = ].~26 C; and M = .234 L.
wherein IJ and C are the inductance and capacitance, res-pectively, per section of a constant K filter. If we as-sume a value of ZooflOO ohms,then Cl~ 1.27z~ = 11.1 pf.
S When more than one section of the filter is con-nected in series to obtain the delay time required,every inductance coil 8 except the ones at each end o the series network will have the inductance value of 21.1.
There~ore, all the inductance coils except the two end ones should have an inductance of 90 nh. and the two end ones have an inductance of 45 nh. each.
As previously mentioned, the magnetic strip 72 and the film 12 of permalloy or other high permeability metal provide mutual coupling between two adjacent coils.
They also enhance the self-inductance of each coil.By choosing the appropriate width of magnetic strip 12 and the length of gap 74, the mutual inductance and self-in-ductance can be varied independently. Therefore, for ease of fabrication it is possible to have the same af number of turns for all the coils. By varying the degree of mag-netic enhancement the end coils can have half (Ll) the in-ductance of the others (2Ll).This is easily accomplished because of the fact ~hat the end coils have only one mag-netic strip 72 linking them instead of two for the other coils.
Let it also be assumed that the width of the links 68 are the same as the end terminals 24 and 26. They are shown narrower in Fig. 1 merely for clarity. The total area ' . . ~ . ,.. ,~ ..............
':
.~, .
11 .
Al of the coil, end terminals and link directly over the dielectric layer 14 of silicon oxide Ls 1,180 mil , or 7.61 x 10 cm. , and the area A2 of the portion of the second half turn 34 that overlies the dielectric layer 14 but no~ the first half turn 30 (Fig. 7) is identified as area ABCDEF and is 150 mil2, or 0.967 x 103 cm.2 . Thus, the required capacitance per section is Cl = 0.08842K (~ ~ ar2~ ) = 11.1 pf.
wherein K is the dielectric constant of silicon oxide, as-sumed to bé a value of 6; dl is the thickness of the sili-con oxide layer 14 above ground plane 12,and d2 is the thickness of 5 x 10 cm. of silicon oxide deposition be-tween coil turns.
Since A2 is smaller than Al and to avoid solv-ing the quadratic equation, the approximate value of dl can be obtained from dl = 0.08842~ 1 2 = 41,000 Angstroms From the foregoing, the delay time per section iS
tl = 1.20 LC = L.049 ns.
Thus, to provide a total delay time of 9 ns., the integral number of sections of the delay line is nine.
As illustrated in Fig. 4, this is provided by arranging ten microminiature inductanc~ coils 8 in two rows~of five
T~IIN FILM INDUCTOR ARRAY WLTII MAGNETIC
ENHANCEMENT AND COUPLING
BACKGROUND OF I~E INVENTION
This invention relates to electrical delay lines, and more particularly to a delay line in micro-miniature form suitable for hybrid circuit applications.
There are available in the market place many electrical delay lines in the form of standard dual-in-line integrated circuit packages. However, there is not available a delay line in chip form suitable for hybrid circuit applications.
SUMMARY OF T~IE INVENTION
In its basic concept, this invention provides an electri/cal delay line in which at least one pair of ~ series-connected, microminiature, inductance coils is ;~; interposed between films of dielectric material which, in turn, are interposed between films of permalloy or 15 other high permeability metal, one of the latter fiLms forming a strip which extends across the inductance coils ~ ..
~' .
~17193 ancl ls lnterrl.lpted at each coil to form a gap a-t the central axls of each coi.:l.
Thus a microminiature elec-trical delay line suit-able for hybrid circuit applications comprises the solid, one piece, lnteyra-ted assembly of:
a) a Eirst film of high permeabili-ty metal, b) a Eirst film of dielectric material overlying and bonded to the first f:ilm of hiyh permeability metal, c) a plurali-ty of series connected microminature in-ductance coils overlying and bonded to the first film of dielectric material, d) a second film of dielectric material overlying and bonded to the inductance coils, and e) a second film of high permeability metal in the form of a narrow strip overlying and bonded to the second film of dielectric material and extend-ing along the center line of the series-connected coils, the second film being interrupted at each coil to form a gap at the axis of each coil.
BRIEF DESCRIPTION OF THE DRAWING
Fig. 1 is a fragmentary plan view, on an enlarged scale, of an electrical delay line embodying the features of this invention.
Fig. 2 is a fragmentary sectional view taken on the line 2-2 in Fig. 1. j'~
: - 3 -" ~
L7~L~3 Fiy. 3 is a sect.ional view shc)winy on an enlarged scale a preferrecl constructi.on Oe ~n inductance coil form- I
ing a part of the delay line.
Fig. 4 :is a plan view of a delay line in chip form, e~odying -the features of this invention.
Fiy. 5 is a schema-tic diagram of an interminate number of sections of an m derived filter utilized - 3a -.~
,, ~
~1~7~3 for the delay linc of this inventlun.
Figs. 6-15 are plan ~lews showlng, ln diagrammatic form, the preferred sequential steps in the ~ormation of the inductance coil shown in Fig. 3.
DESCRIPTION OF THE PRE~E~RED EMBO~IMENT
As illustrated ln ~ig. 5, the delay llne o~ thls invention utilizes an m-derived filter a sec~lon of whlch lncludes a pair of series-connected inductance coils 8 (Figs. 1-4) each providing an inductance L
and ha~ing mutual lnductance M between them, and a sllunting capacltance Cl. The delay line may include any number of such sectlons as desired, limited only by the attenuation or loss that can be tolerated, In accordance with this inventlon~ the delay line is constructed and supported upon a substrate 10 of quart~, glass or other dielectric material, preferably suitable Por the thin film deposition of the delay line components as described herelnafter, For purposes o~ this invention, thin film deposition is understood to include depositions by printed circuit techniques as well as vapor deposition techniques.
Preferred a~ong these is ~he vapor deposi~ion method described in U.S.
Letters Patent No. 3,785,046 issued January 15, 1974 to Thomas A. Jennings.
By this technique the various films are applied by means of masks which delineate the shapes of areas upon which the ~apors depositions o~
conductive metal and dielectric material are to be made.
A
i ' , I
~ ~ 4 ~ I
7~1l93 As illustrated~ a film 12 of permalloy, mu-metal) or other suitable high permeability metal, is de posited upon and bonded integrally to one entire surface of the substrate 10. This film serves as a return path of the magnetic circuit and also as the ground plane for the delay line capacita~ es. A suitable thickness for this film is approximately S,()00 Angstroms.
Deposited upon and bonded integrally to the ~entire area of film 12 of high permeability metal is a 10 film 14 of silicon oxide, silicon nitrite, quartz, or other suitable dielectric material. As discussed here~
inafter, the thickness of this film may be varied.
Next, a pair of electrically conductive termin-als 16 and 18 are deposited upon the dielectric film 14, 15 adjacent one side of the substrate, for use in connect-ing the delay line to associated hybrid circuits. If desired, these terminals may be extended to the back ~; side of the substrate 10 to accommodate the mounting of hybrid circuitry on said back side. The high permeabili-20 ty metal ground plane 12 serves effectively to isolate the hybrid circuitry from the delay line.
Next, at least one pair of microminiature in~
ductance coils 8 is mounted upon and bonded integrally to the dielectric layer 14. As illustrated in Fig. 4, ; 25 ten such inductance coils are spaced apart on the~sub-strate in two rows.
In Fig. 3, each coil is shown t~ include a ' .;
~ ~7 ~ 3 plurality of superlmposed coaxial turns 20 of electri- ;
cally conductive metal film with adjacent turns iso-lated electrically from each other by an interposed film 22 of dielectric material. The innermost and outer-most turns are extended laterally in opposite direct-ions to provide end terminals 24 and 26.
All of the inductance coils 8 forming the de-lay line, ten of them as exemplified in Fig. 4, are form-ed simultaneously, but spacecl apart in the desired pat-10 tern, by appropriately constructed masks. Figs. 6-15 il-lustrate diagrammatically the sequential steps utilized in the formation of the inductance coil illustrated in Fig. 3. Thus, a first mask is utilized to provide the vapor deposition of the initial electrically conductive 15 coil turn segment 30. In the illustrated embodiment,this segment includes the laterally projecting end terminal 24 a portion of which overlies a portion of one of the end terminals 16 and 18, for example terminal 18.
Next3 by appropriate masking, a film of quartz s 20 or other suitable dielectric material 32 is vapor depos-ited over an intermediate portion of the segment 30 (Fig. 6) 7 leaving a leading end portion of the segment exposed for conductive connection of a trailing end por-tion of the next conductive turn segment 34 (Fig. 7).
25 This latter segment overlies the dielectric film 32.
Next,~a second deposition of dielectric film 36 (Fig. 8) is applied over the trailing portion of the ¦ conductive segment 34. The mask providing this deposi-:i ~
~L~17~93 ~ion i5 substantially identical to the mask providing the ~irst dielectric deposition 32, with the patte~n rotated 180 so as to expose the lead:ing end portion o~ the un-derlying conductive segment 34 for conductive connection 5 to the trailing end portion of the next succeeding con-ductive segment 38. The shape of this latter segment is substantially identical to the shape of the next preced-ing conductive segment 34, bul rotated 180, as will be apparent.
Subsequent dielectric ~ilms 40, 44, 48, 52, 56, 60 and 64 and conductive segments 42, 46, 50, 54, 58 and 62 are deposited al~ernately (Fig. 9~14), utilizing the masks which provided the depositions of the dielect-ric films and conductive film segments described herein-15 before, to complete the desired number of turns for eachinductance coil 8. In the embodiment illustrated in Figs.
; 6-15, the sequence provides for the deposition of four and one-half turns of conductive metal, with each turn separa-ted electrically from each other by an interposed film of 20 dielectric material.
The coil is completed with the addition of ~ the final conductive turn segment 66 and integrated end ; terminal 26 opposite the starting end terminal 24. As in-dicated in Fig. 15, this is achieved by utilizing a mask 25 having an aperture shaped like that of the mask which pro-vided the first turn segment 30 and connected end termin-al 24, but rotated 180~.
It will be understood, of course, that in the production of the delay line illustrated in Fig.`4, where-9 ~
in ten spaced inductance coils are provided, the masks re-ferred to in describing the sequence illustrated in Figs.
6-15, contain shaped openings necessary for the simultane-ous depositions required for the production of the ten in- i ductance coils.
The end terminal 26 on the final induc~ance coil 8, opposite the initial coil, is deposited in over-lapping, conductive engagement with the second o~ the pair of terminals 16 and 18, for example terminal 16, initially deposited on the dielectric film 14, as will be understood.
The confronting end terminals 24, 26 of ad-jacent coils 8 are interconnected electrically by means of a link 68 of electrically conductive metal film, such as aluminum, gold, or other suitable metal. The plurality of coils thus are connected together electrically in ser-ies.
Next a second film 70 of silicon oxide,quartz, or other~suitable dielectric material, is deposited over the series-connected inductance coils 8, as well as t~e interconnecting links 68 and the adjacent first film 14 of dielectric materLa]. This film 70 terminates short of the end terminals 16 and 18, as illustrated in Fig. 4.
Finally, an elongated strip 72 of permalloy, or other high permeability metaL, is deposited as a film, also suitably about 5,000 Angstroms thick, over the se-cond layer 70 of dielectric material, extending along the centerline of the;series-connected coils 8. This narrow~
strip of high permeability metal lS interrupted at each 9.
coil to form a gap 74 at the axis of each coil. In this latter regard, it is to be noted that the coil. turns are stacked one upon another concentrically about a central axis which is disposed perpendicularly to the supporting : 5 surface of the substrate 10.
The strip 72 of permalloy or other high per-meability metal which extends between centers of adjacent inductance coil cooperates with the film 12 of high per-meability metal underlying the coils to provide the mutual lO inductance M required. The desired value of mutual induct-ance is obtained by varying the width of the strip 72 and the length of the gaps 74 at the centers of the coils.
The`thickness of the dielectric layers 14 and 70 also af-fects the mutual inductance.
The capacitance Cl per section of the delay - line is provided by the capacitance between the high pe~-- meability metal ground plane 12 and the underside of the - inductance coil, including the area of the end terminals ~: 24 and 26 and the link 68 interconnecting the confront-20 ing end terminals of a pair of adjacent inductance coils.
: This capacitance may be varied by changing the thickness ~ of the dielectric layer 14 above the ground plane and the ; area of the conductive link 68.
The following illustrates a typical delay 25 line: Let it he assumed that the inductance, Ll of the filter is 45 nh. For an m~derived filter having a char-~acteristic impedance, ZO~ the relationships among Ll, Cl, ànd ZO are as follows:
~l17~3 10, ~ZO ~ C; Ll= .515 L; Cl = ].~26 C; and M = .234 L.
wherein IJ and C are the inductance and capacitance, res-pectively, per section of a constant K filter. If we as-sume a value of ZooflOO ohms,then Cl~ 1.27z~ = 11.1 pf.
S When more than one section of the filter is con-nected in series to obtain the delay time required,every inductance coil 8 except the ones at each end o the series network will have the inductance value of 21.1.
There~ore, all the inductance coils except the two end ones should have an inductance of 90 nh. and the two end ones have an inductance of 45 nh. each.
As previously mentioned, the magnetic strip 72 and the film 12 of permalloy or other high permeability metal provide mutual coupling between two adjacent coils.
They also enhance the self-inductance of each coil.By choosing the appropriate width of magnetic strip 12 and the length of gap 74, the mutual inductance and self-in-ductance can be varied independently. Therefore, for ease of fabrication it is possible to have the same af number of turns for all the coils. By varying the degree of mag-netic enhancement the end coils can have half (Ll) the in-ductance of the others (2Ll).This is easily accomplished because of the fact ~hat the end coils have only one mag-netic strip 72 linking them instead of two for the other coils.
Let it also be assumed that the width of the links 68 are the same as the end terminals 24 and 26. They are shown narrower in Fig. 1 merely for clarity. The total area ' . . ~ . ,.. ,~ ..............
':
.~, .
11 .
Al of the coil, end terminals and link directly over the dielectric layer 14 of silicon oxide Ls 1,180 mil , or 7.61 x 10 cm. , and the area A2 of the portion of the second half turn 34 that overlies the dielectric layer 14 but no~ the first half turn 30 (Fig. 7) is identified as area ABCDEF and is 150 mil2, or 0.967 x 103 cm.2 . Thus, the required capacitance per section is Cl = 0.08842K (~ ~ ar2~ ) = 11.1 pf.
wherein K is the dielectric constant of silicon oxide, as-sumed to bé a value of 6; dl is the thickness of the sili-con oxide layer 14 above ground plane 12,and d2 is the thickness of 5 x 10 cm. of silicon oxide deposition be-tween coil turns.
Since A2 is smaller than Al and to avoid solv-ing the quadratic equation, the approximate value of dl can be obtained from dl = 0.08842~ 1 2 = 41,000 Angstroms From the foregoing, the delay time per section iS
tl = 1.20 LC = L.049 ns.
Thus, to provide a total delay time of 9 ns., the integral number of sections of the delay line is nine.
As illustrated in Fig. 4, this is provided by arranging ten microminiature inductanc~ coils 8 in two rows~of five
2~ inductors each on a chip that is about one centimeter long and one-quarter centimer wide.
.
1~ 93 2 .
From the foregoing it will be appreciated that the present invention provides a microminature de-lay line which is of simplified construction for econom-ical manufacture, suitable for hybrid circuit applica-S tions, and wherein the values of mutual inductance andcapacitance per section may be varied as required by varying the physical dimensions of the components dur-ing manufacture, It will be apparent to those skilled in the 10 art that various changes may be made in the size, shape, type, number and arrangement of components described here-inbefore without departing from the spirit of this inven-tion.
Having now described my invention and the 15 manner in which it may be used, I claim:
~,
.
1~ 93 2 .
From the foregoing it will be appreciated that the present invention provides a microminature de-lay line which is of simplified construction for econom-ical manufacture, suitable for hybrid circuit applica-S tions, and wherein the values of mutual inductance andcapacitance per section may be varied as required by varying the physical dimensions of the components dur-ing manufacture, It will be apparent to those skilled in the 10 art that various changes may be made in the size, shape, type, number and arrangement of components described here-inbefore without departing from the spirit of this inven-tion.
Having now described my invention and the 15 manner in which it may be used, I claim:
~,
Claims
THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1.
A microminiature electrical delay line, com-prising the solid, one-piece, integrated assembly of:
a) a first film of high permeability metal, b) a first film of dielectric material overlying and bonded to the first film of high permeability metal, c) a plurality of series-connected microminiature in-ductance coils overlying and bonded to the first film of dielectric material, d) a second film of dielectric material overlying and bonded to the inductance coils, and e) a second film of high permeability metal in the form of a narrow strip overlying and bonded to the second film of dielectric material and extending along the center line of the series-connected coils, the second film of metal being interrupted at each coil to form a gap at the axis of each coil.
2.
The delay line of claim 1 including a substrate of dielectric material underlying and bonded to the first film of high permeability metal.
3.
The delay line of claim 1 wherein the coils are spaced apart in a line, each coil has a central axis extending perpendicular to the plane of the substrate and has opposite end terminals extending in opposite direct-ions from the coil on said line, and electrically conduct-ive metal interconnects the confronting end terminals of adjacent coils.
4.
The delay line of claim 2 wherein the sub-strate is quartz, the films of high permeability metal are permalloy and the films of dielectric material are silicon oxide.
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1.
A microminiature electrical delay line, com-prising the solid, one-piece, integrated assembly of:
a) a first film of high permeability metal, b) a first film of dielectric material overlying and bonded to the first film of high permeability metal, c) a plurality of series-connected microminiature in-ductance coils overlying and bonded to the first film of dielectric material, d) a second film of dielectric material overlying and bonded to the inductance coils, and e) a second film of high permeability metal in the form of a narrow strip overlying and bonded to the second film of dielectric material and extending along the center line of the series-connected coils, the second film of metal being interrupted at each coil to form a gap at the axis of each coil.
2.
The delay line of claim 1 including a substrate of dielectric material underlying and bonded to the first film of high permeability metal.
3.
The delay line of claim 1 wherein the coils are spaced apart in a line, each coil has a central axis extending perpendicular to the plane of the substrate and has opposite end terminals extending in opposite direct-ions from the coil on said line, and electrically conduct-ive metal interconnects the confronting end terminals of adjacent coils.
4.
The delay line of claim 2 wherein the sub-strate is quartz, the films of high permeability metal are permalloy and the films of dielectric material are silicon oxide.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA000323445A CA1117193A (en) | 1979-03-14 | 1979-03-14 | Microminiature electrical delay line utilizing thin film inductor array with magnetic enhancement and coupling |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA000323445A CA1117193A (en) | 1979-03-14 | 1979-03-14 | Microminiature electrical delay line utilizing thin film inductor array with magnetic enhancement and coupling |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1117193A true CA1117193A (en) | 1982-01-26 |
Family
ID=4113749
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA000323445A Expired CA1117193A (en) | 1979-03-14 | 1979-03-14 | Microminiature electrical delay line utilizing thin film inductor array with magnetic enhancement and coupling |
Country Status (1)
Country | Link |
---|---|
CA (1) | CA1117193A (en) |
-
1979
- 1979-03-14 CA CA000323445A patent/CA1117193A/en not_active Expired
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