CA1108246A - Timing-phase recovery circuit - Google Patents

Abstract

TIMING-PHASE RECOVERY CIRCUIT

ABSTRACT OF THE DISCLOSURE

A timing-phase recovery circuit, which is suitably mounted on a digital LSI, is disclosed. The timing-phase recovery circuit has a first device for extracting a digitial timing signal from a received input analogue singal, a second device for detecting a virtual zero crossing included in the digital timing signal in synchronous with a sampling signal and a third device for carring out a phase shift with respect to the sampling signal in order to tune the timing signal to the frequency of the virtual zero crossings in a very short time.

Description

TIMING-PHASE ~ECOVERY CIRCUIT

The present invention relates to a timing-phase recovery circuit, and more particularly a timing-phase recovery circuit located in a receiver station of a carrier--modulated data communication system.
In a carrier-modulated data communication system, a carrier-modulated analogue signal is transmitted from a ~ sender station to a receiver station, where a carrier--modulated analogue singnal is produced, in the sender station, based on a PSK (Phase Shift Keying) modulation mode, a QAM (Quadrature Amplitude Modulation) mode or AM
(Amplitude Modulation) mode. In order to establish any of the above mentioned modulation modes, the analogue signal to be transmitted from the sender station is modulated by data to be communicated, in synchronous with a predetermined timing signal having a constant frequency. ~hile, in the receiver station, which receives the analogue singal, the received input analogue signal is demodulated and then the original data is reproduced by means of a timing recovery circuit in synchronous with a timing signal. This timing signal should be identical with the aforesaid timing signal generated in the sender station. Accordingly, the timing signal of the receiver station is tuned to a timing signal which is extracted from the input analogue signal.
A tuning operation between the extracted timing signal and the timing signal generated in the receiver station must be promptly completed. This is because an automatic .,

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equalizer, an automatic gain control circuit and so on of the receiver station can start respective operations after the timing signal of the receiver station has correctly been tuned to the extracted timing signal. Further, according to world standards pertaining to the carrier--modulation data communication system, the receiver station must be set in normal operating conditlon in a very short period, such as 50 ms, from the time when the input analogue signal is applied thereto. Thus, the timing-phase recovery circuit of the receiver station must complete the tuning operation in a very short time.
In the prior art, the timing-phase recovery circùit consists of an analogue circuit. The timing-phase recovery analogue circuit has already been known, for example in IEEE TRANSACTIONS ON COMMUNICATIONS, VOL COM-22, No. 7, July 1974, on pages 913 through 919, entitled "Statistical Properties of Timing Jitter in a PAM Timing Recovery Scheme" and in IEEE TRANSACTIONS ON COMM~NICATIONS, November 1975, on pages 1327 through 1331, entitled "Envelope-Derived Timing Recovery in QAM and SQAM Systems". Since the timing-phase recovery analogue circuit deals with an analogue timing signal, the so-called zero crossing can be detected in a very short time, which zero crossing is very useful for tuning the timing signal of the receiver station to the extracted timing signal contained in the input analogue signal.
In recent years, a demand has arisen for constructing the timing-phase recovery circuit as a digital circuit.

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A timing-phase recovery digital circuit may easily be fabricated as an LSI (Large Scale Integraiton) circuit, and accordingly the timing-phase recovery digital circuit becomes cheaper in cost, more accurate in operation and smaller in size, when compared to those of the prior timing-phase recovery analogue circuit. In general, it is easy for a person skilled in the art to create the timing--phase recovery digital circuit according to the corre-sponding timing-phase recovery analogue circuit, merely by substituting the analogue circuit elements of the analogue circuit for the corresponding digital circuit elements comprising the digital circuit. However, the above mentioned timing-phase recovery digital circuit creates a serious defect on the aforesaid tuning operation. That is, the digital circuit cannot complete the tuning operation in a very short time. The reason why the tuning operation can not be completed in a very short time, will be clarified hereinafter; however, in short, the reason resides in the fact that, in the timing-phase recovery digital circuit, the aforesaid zero crossing cannot be detected from the input analogue signal in a very short time.
Therefore, it is an object of the present invention to provide a timing-phase recovery circuit comprised of digital circuit elements, which circuit creates no serious de~ect as mentioned above; that is, which circuit can complete the tuning operation in a very short time, as occurs in the prior art timing-phase recovery analogue circuit.

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The present invention will be more apparent from the ensuing description with reference to the accompanying drawings wherein:
Fig. 1 is a schematic block diagram of a typical 5 carrier-modulated data communication system;
Fig. 2 is a schematic block d:iagram of members which comprise a receiver station 14 shown in Fig. 1, according to the present invention;
Fig. 3 depicts a waveform of an analogue timing signal obtained in a prior art timing-phase recovery analogue circuit;
Fig. ~ depicts a wave~orm of a digital timing signal, illustrated in an imaginary analogue waveform, obtained in a timing-phase recovery circuit, according to the present invention;
Fig. 5 is a block diagram illustrating a first embodiment of a timing-phase recovery circuit, accoring to the present invention;
Fig. 6 is a circuit diagram illustrating details Of a virtual zero crossing detector 55 shown in Fig. 5;
Fig. 7 is a circuit diagram illustrating details of a pulse control circuit 53 shown in Fig. 5, according to the present invention;
Fig. 8 is a chart of times used for explaining the operation of a circuit 53 shown in Fig. 7;
Fig. 9 is a circuit diagram illustrating details of a sampling circuit 21 shown in Figs. 2 and 5;
Fig. 10 is a circuit diagram illust~ating details .. ~ :. . .
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2~ Eii of a timing signal extracting circuit 22 shown in Figs. 2 and 5;
Fig. 11 is a circuit diagram illustrating details of another type of the pulse control circuit 53 shown is Fig. 5, according to the present invention;
Fig. 12 is a chart of times used for explaining the operation of a circuit 53' shown in Fig. 11;
Fig. 13 is a circuit diagram illustra-ting a selection circuit which produces a selection signal se shown in Fig. 5, according to the present invention;
Fig. 14 is a block diagram illustxating a second embodiment of a timing-phase recovery circuit, according to the present invention;
Fig. 15 depicts imaginary analogue signals corresponding to the digital outputs produced from circuits 142 and 22, respectively, shown in Fig. 14;
Fig. 16 is a circuit diagram illustrating details of circuits 141 and 143 shown in Fig. 14, according to the present invention;
Fig. 17 is a circuit diagram illustrating details of a circuit 142 shwon in Fig. 14, according to the present invention;
Fig. 18 is a block diagram illustrating a modified arrangement of blocks 21, 142 and 22 shown in Fig. 14, accoring to the present invention;
Fig. 19 is a block diagram illustrating a third embodiment of a timing-phase recovery circuit, according to the present invention;

~ 6 -Fig. 20 depicts an imaginary analogue waveformof a timing shignal St produce~ from a circuit 22 shown in Fig. 19;
Fig. 21 is a circuit diagram illustrating details .. 5 of a circuit 191 shown in Fig. 19, according to present invention;
. Fig. 22 is a circuit diagram illustrating details ; of a circuit 192 shown in Fig. 19, according to the present invnetion, and;
10Fig. 23 is a circuit diayram illustrating a circuit for suppressing a timing jittex included in the timing signal.
In Fig. 1, a typical carrier-modulated data communi-cation system is comprised of a data terminal 11, a sender station 12, a transmission line 13, a receiver station 14 and a data terminal 15. Data supplied from the terminal 11 is applied to the sender station 12, and a carrier which is modulated by the data is transmitted, via the line 13, from the station 12, to the receiver station 14, in the form of an analogue signal, such as PSK, QAM or AM signal.
The station 14 receives the input analogue signal, and the input an.alogue signal is demodulated therein. The demodu-lated input analogue signal, that is the original data produced by the terminal 11 is supplied to the data terminal 15. Among the schematic blocks shown in Fig. 1, the present invention is directed to the receiver station 14.
The receiver station 14 is comprised of members illustrated in Fig. 2. In Fig. 2, members to which the .: - . : . : . . .

present invention apply are referred to by reference numerals 21, 22 and 23. The reference numeral 24 represents . . , a conventional data reproducing circuit which includes the automatic equalizer, the automatic gain control circuit, the digital processor and so on. This circuit 24 receives the input analogue signal Ain from the transmission line 13 (Fig. 1) by way of a sampling circuit 21 and reproduces the original data in synchronous with the timing signal.
The timing signal is generated in synchronous with a sampling signal Ss produced from a tuning circuit 23. The sampling signal Ss is derived from a reference clock signal CLK which is tuned to an extracted timing signal St produced from a timing signal extracting circuit 22. The circuit 22 receives a sampled input signal Sin and e~tracts the timing signal St therefrom. The signal St is originally included in the signal Ain, because the signal Ain has been modulated in the sender station 12 (see Fig. 1) in synchronous with an identical timing signal. The sampling signal S also applies to circuits 21 and 22.
In the prior art, a timing signal extracting analogue circuit which corresponds to the circuit 22, is comprised of analogue circuit elements. Accordingly, an analogue timing signal is obtained therefrom. This signal is illustrated, in Fig. 3, as a waveform 31. The analogue timing signal 31 is compared with a threshold level 32, and then zero crossings 33, 34, 35, 36 and so on are detected in a very short tlme. As mentioned above, these zero crossings are very useful for tuning the timing signal ... , .. :: -. ., ~.,.. ,: ~, .. :.. , : : .;,. :: :

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of the data reproducing circuit 24 Isee Fig. 2) to the input analogue signal Ain. Only the zero crossing which are located at the intersection of the level 32 and the right-upwardly inclined portions of the waveform 31, such as the zero crossings 33, 35, and so on, are utilized for carrying out the tuning operation in this embodiment.
Contrary to the above, the timing signal extracting circuit 22 tsee Fig. 2) receives the samples input signal Sin and extracts therefrom a sampled timing signal St through digital processing steps. The samples timing signal St is imaginarily represented, in Fig. 4, by arrows 41, 42 43, 44 and so on. It should be noted that each signal St represented by an arrow is not an analogue value but a digital value. Also, the imaginary timing signal illustrated by dotted line 31 in Fig. 4, shows the envelop of the available digital signal. The imaginary waveform and arrows of Fig. 4 are drawn only for facilitating the understanding o~ the present invention. The sampled timing signals St (41, 42, 43, and so on) are produced from the circuit 22 (see Fig. 2) with the same frequency as that of the sampling signal Ss (see Fig. 2). Since the sampled timing signal St is not produced continuously but inter-mittently, zero crossings which are imaginarily illustrated by circles in Fig. 4, cannot be detected instantaneously.
These zero crossings are not actually existing zero cross-ings, as are the zero crossings 33, 35 and so on shown in Fig. 3, but virtual zero crossings. If the signal St t41, 42, 43 and so on) appears at the virtual zero crossings, the - 9~

tuning opperation may be promptly completed. However, such probability that the signal St apprears just at the virtual zero crossings is very rare. Further, it takes an extremely long time to shift the signal St to its nearest 5 virtual zero crossing. The reason is as follows. The sampled timing signal St has a mean frequency ft ~ and the sampling signal Ss has a frequency fs. Usually, the sampling frequency fs is selected to be N~ft (N~2), that is fs ~ N ft ~ in accordance with the well-known sampling theorem. Accordingly, the signal St is shifted to its nearest virtual zero crossing by the value of 1~s ~ N~ftl.
If the value ¦fs ~ NJft¦ is relatively large, the signal St may soon be shifted to its nearest virtual crossing.
However, since the value ¦fs ~ N ft¦ is very small, for example 0.001~%~ o the frequency ft ~ it takes an extremely long time to shift the signal St to its nearest virtual zero crossing. Thus, in the timing-phase recovery digital circuit, the aforesaid tuning operation cannot be completed in a very short time.
In order to complete the tuning operation in a very short time, the timing-phase recovery circuit of the present invention is basically comprised of a flrst means for detecting the virtual zero crossing and a second means for shifting the sampled timing signal S~ to the detected virtual zero crossing. The present invention will be clarified by the following first through third embodiments.
In Fig. 5, which is a block diagram illustrating the first embodiment of the timing-phase recovery circuit, the members shown in this Fig. 5 correspond to the members 21, 22 and 23 shwon in Fig. 2. The timing-phase recovery circuit 50 receives the reference clock signal CLK, and the input analogue signal Ain, and the circuit 50 produces the tuned sampling signal Ss I as a timing signal,to the circuit 24. The above reference symbols CLK, Ain, Ss and the above reference numeral 24 are shown in Fig~ 2. Also, in Fig. 5, the sampling cirucit 21, the timing signal extracting circuit 22, the sampled signals Sin and the extracted signal St , are shown in Fig. 2. The input analogue signal Ain is sampled by the sampling circuit 21 with the sampling frequency fs defined by the sampling signal Ss. In this case, the signal Ss is not yet tuned to the timing signal included in the signal Ain. The sampled input signal Sin from the circuit 21 is applied to the timing signal extracting circuit 22, and then the timing signal included in the signal Sin (refer to the imaginary waveform 31 in Fig. 41 is extracted therefrom.
Therea~ter, the extracted timing signal St is applied to a virtual zero crossing detector 55. When the detector 55 does not detect the virtual zero crossing, the detector 55 produces a virtual zero crossing detecting signal Sv having logic 1l0ll. While, when the detector 55 detects the virtual zero crossing, the detector 55 produces the signal Sv having logic "1". As previously mentioned, the detector 55 detects only the crossings Z33 , Z35 and so on (see Fig 4). Since the zero crossings Z33 , Z35 a not actually exisiting zero crossings, the detector 55 .
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finds the existence of each virtual zero crossing by using a special logic circuit. Details of this special logic circuit will be desclosed hereinafter, by referring to Fig. 6.
On the other hand, in Fig. 5, the reference clock signal CLK having the frequency f0 is applied to both a first frequency divider (l/N) 51 and a second frequency divider (l/M) 52. The dividing number M equals to K times of the dividing number N, that is M = K N, where K is equal to or larger than 2. The divided clock signal having a frequency fl is appled to a third frequency divider (l/L~ 54 by way of a pulse control circuit 53.
The clock signal having a frequency f3 from the circuit 53 becomes, via the divider 54, the sampling signal Ss having the frequency f . The pulse control circuit 53 removes some clock pulses from the pulse train supplied from the divider 51 every time the rising edge of the clock signal having a frequency f2 is applied to the circuit 53, when the signal Sv having logic "0" is applied ; 20 to the circuit 53. This logic "0" of the signal Sv denotes that the virtual zero crossing is not yet detected.
During the period when the signal Sv is logic "0", the number of clock pulses is reduced, and accordingly the frequency of the clock signal from the divider 54, that is the sampling signal S is low. In this case, the following equations are obtained. That is, -fl = l/N~fo (1) ~ 3 fl f2 (2) ~: : . . .. .

and fs = l/L~f3 (3) Therefore, in Fig. 4, each period between each two adjacent timing signals St (41, 42, 43 and so on) is wide. In 5 other words, all the timing signals St are shifted very quickly in a rightward direction in Fig. 4. As a result, the timing signal St referenced by the numeral 44 approaches the nearest virtual zero crossing Z35 very quickly. When the signal St (44) is located either just at the zero crossing Z35 or very near the zero crossing Z35 , the phase of the sampling signal Ss and the phase oE the timing signal St become an in-phase condition. Here, the tuning operation is completed in a very short time, and the signal Sv becomes logic "1", which logic "1" denotes that the circuit 53 should stop removing the clock pulses from the pulse train produced from the divider 51.
Details of the above mentioned special logic circuit, that is the virtual zero crossing detector 55 shown in Fig. 5, wi]l be explained by referring to Fig. 6. In Fig. 6, the virtual zero crossing detector 55 receives the sampled -timing signal St (see Fig. 5), which is a digital signal, and then produces the zero crossing detecting signal Sv ~see Fig. 5) in synchronous with the signal Ss (see Fig. 5). The signal St is momentarily stored in a latch circuit 61 every time the signal Ss is applied thereto. If the signal St is composed of an 8-bit digital pulse, the circuit 61 may be comprised of eight flip flop circuits. Further, the signal St is expressed by the well . .

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known two's-complement indication. Therefore, when the signal St indicates the value of zero, the signal St is expressed by (00000000). When the signal St indicates positive value, the 8 bits of this signal St may vary from (00000001) to (01111111), via (00000011), (00000111) and SQ on. When the signal St is a negative value, the ~ bits of this signal St may vary from (11111111) to (10000000), via (11111110), (11111100) and so on. A most significant bit MSB, which represents whether the signal St is a positive value or a negative value, is applied, on one hand, to a delay flip-flop circuit 62, and, on the other hand, to a NAND gate 65 and a NOR gate 66. The upper 3 bits of data from the circuit 61 are applied to both the gates 63 and 64. The upper 3 bits of data indicate one--eighth of the peak amplitude level of the signal St.
Accordingly, when the upper 3 bits are logic (000), it is concluded that the signal St has a very low positive value. That is the signal St is located just at or close to the virtual zero crossing. When the upper 3 bits are logic (111), it is concluded that the signal St has a very low negative value. That is, the signal St is located just at or closed to the virtual zero crossing. If, in Fig. 4j the signal St is located on the arrow 44-, the upper 3 bits are logic ~111). Then, returning to Fig. 6, the output of the gate 63 becomes logic "0". Since the MSB is logic "1", the output of the gate 65 becomes logic "1". In this case, since the output of the gate 64 is logic "0" and the MSB is logic "1", the output o~ the gate ., . . , ,. ', ' ' ' . ' . " ' , '.'' " ' ' :': : ''.~ ' 66 is logic "0". Then the output of an inverter 67 is logic "1". Thus, the output of an AND gate 68, heing logic "1", is applied to the input of an AND gate 69. The gate 69 produces the signal Sv having logic "1", when a Q-output of the flip flop 6~ is logic "1". As previously mentioned, in Fig. 4, onl~ the virtual zero crossings Z33 , Z35 and so on, are available. That is, these ~ero crossings are located at the portions where the polarity ~ of the signal St changes from negative to positive. The flip flop 62 is useful for determining that the signal St is not located close to the virtual zero crossings Z34 , Z36 and so on, but at the available virtual zero crossings Z33 , Z35 and so on. This flip flop 62 provides information indicating that a preceding signal St is a negative value, and accordingly the Q-output thereof is logic "1". Then, the signal Sv having logic "1", which denotes that the virtual zero corssing has been detected, is produced from the gate 69. In the othex case, in Fig. 4, if the signal St is located on the arrow 44+, the upper 3 bits are logic (000). Then the output of the gate 64 becomes logic "1".
Since the MSB is logic "0", the output of the gate 66 becomes logic "0", and the output of the inverter 67 ; becomes "1". In this case, since the output of the gate .
63 is logic "1" and the MSB is logic "0", the output of the gate 65 is logic "1". Thus, the output of the gate 68 becomes logic "1". If the output of the flip flop is logic "1", then the signal Sv having logic "1" is produced from the gate 69.

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The virtual zero crossing detecting signal Sv is appl.ied to the pulse control circuit 53. In Fig. 7, which is a clrcuit diagram illustrating details of the pulse control circuit 53, the circuit 53 receives the clock signals having the frequencies of fl and f2 (see Fig. 5) and the signal.Sv (see Figs. 5 and 6), and then the circuit 53 produces the clock signal having the frequency f3 (see Fig. 5). During the application of the signal Sv having logic "0" to a delay flip flop 72, the frequency f3 of the clock signal from the ci.rcuit 53 is defined by the above recited equation (2), that is f3=fl-f2- When the logic of the.signal Sv is logic "0", the flip flop 72 is not reset, and when the clock signal (f2) is applied to an AND gate 71, a Q-output of the flip flop 72 changes from logic "0" to logic "1". Therefore, a NOR gate 73 closes, and accordinglvr the clock signal (fl~ is not supplied to an inverter 74 every time a rising edge of the clock signal (f2) appears. When the signal Sv having logic "1"
is applied to the flip flop 72, the Q-output is held to be logic "0". Thereafter, the NOR gate 73 is held to be open, and the following equation (4J is obtained.
f3 fl (4) A feedback line 75 is effective from removing only.one pulse from the clock signal (fl) every time the rising edge of the clock signal (f2) is applied to the AND gate 71.
The operation of the circuit 53 shown in Fig. 7 will be.
more apparent by referring to the time charts shown in Fig. 8. In Fig. 8, waveformes shown in items 1) through 5), . -: . . . .

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respectively correspond to the signal (fl), the signal (f2), the signal (Sv~, the signal from the Q-output of the circuit 53 and the signal -(f3)~
In Fig. 9, which is a circuit diagram illustrating details of the sampling circuit 21 shown in Figs. 2 and 5, the circuit 21 is comprised of a pre-amplifier 91 which receives the analogue input signal Ain , a sampling switch 92 for sampling the signal Ain in synchronous with the ~ freguency of the sampling signal Ss ~ a capacitor 93 which holds the sampled signal Ain and a post-amplifier 94. The amplifier 9~ produces the sampled and amplified analogue input signal Ain. An Analogue/Digital converter (A/D) 95 converts the signal Ain to the corresponding digital signal Sin.
In Fig. 10, which is a circuit diagram illustrating details of the timing signal extracting circuit 22 shown in Figs. 2 and 5, the circuit 22 is comprised of a squarer t 101 and a band pass filter (BPF) 102. The symbol ~
denotes the product of the sampled digital input signal 20 Sin itself from the sampling circuit 21. The sguarer 101 is constructed as an arithmetic logic circuit. The filter 102 is constructed as a narrow band digital filter. The filter 102 produces the timing signal St which has been included in the analogue input signal Ain. The combination 25 of the digital squarer 101 and -the digital filter 102 has equivalent functions (sampled version~ of analog squarer and analog filter as can be seen from the pulication, for example "Theory and Application of Digital Signal Processing"

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Prentice-Hall, 1975, by Rabiner Gold.
Returning to Fig. 4, as previously explained, the timing signal St is quickly shifted rightward until, for example the signal St (44) is located just at or closer to the nearest virtual zero crossing Z35. However, the timing signal St may also be ~uickly shifted leftward. If the signal St (45~ is located closer to the nearest virtual zero crossing Z35 than the signal St (44) is locatecl, it will be more preferable to shift the signal St (45~ leftward than to shift the signal St (44) rightward, in order to complete the tuning operation in a very short time. The above mentioned leftward shi~t of the signal St (45) cannot be achieved by removing the clock pulse from the output of the divider 51 (see Fig. 5), but can be achieved by inserting a further clock pulse thereto. In this case, the above recited equation (2), that is f3=fl-f2 is not satisfied, but the following equation (5) is satisfied.

f3 = fl + f2 (5~
; Therefore, each period between each two adjacent timing signals St (41, 42, 43, 44, 45, 46, 47 and so on) is caused to be short. In other words, all the timing signals St are shited le~tward on the drawing of Fig. 4 very quickly.
The pulse control circuit 53 shown in Fig. 7 is available only for achieving the aforesaid rightward shift of the timing signal St. Accordingly, if the aforesaid leftward shift of the timing signal St is also required in ; the pulse control circuit 53 of Fig. 5, this circuit 53 should also contain a circuit 53' shown in Fig. 11, other , , :, , ~ j . ............ : . ,: : .
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than the circuit 53 shown in Fig. 7. In this case, the circuit 55 of Fig. 5 should further include a selection circuit 130 shown in Fig. 13, which circuit 130 produces a selection signal S~1 (see Fig. 5) and applies to the pulse control circuit 53 (see Fig. 5). The signal SQ indicates whether the aforesaid rightward shft or leftward shift must be achieved in the timing-phase recovery circuit 50 (see Fig. 5). If, for example the absolute peak value of ~ the signal St (44) is larger than that of the signal St (45), the selection signal Se activates the circuit 53' (see Fig. 11). While, if the absolute peak value of the signal St ~44) is smaller than that of the signal St (45), the selection signal S~ activates the previously explained circuit 53 of Fig. 7.
In Fig. 11, which is a circuit diagram illustrating details of another type of the circuit 53 shown in Fig. 5, the members 51, 52, 54, the signals CLK, Ss / Sv ~ S and symbols fo ~ fl ~ f2 and f3 have already been e~plained hereinbefore. The pulse control circuit 53' is comprised of an inverter 111, a NOR gate 112, an AND gates 1]3 and 115, delay flip flops 114, 116 and 117 and an O~ ~ate 118.
The block 53 (Fig. 7) represents the pulse control circuit 53 shown in Fig. 7. The operation will be apparent by referring to the time charts shown in Fig. 12. The columns 1) through 7) shows, respectively the waveform of the signal ~f0), the signal (fl), the signal ~f2), the signal of the outpu-t from the AND gate 113, the signal of the Q-output from the flip flop 115, the signal of the Q-output :
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.~: .,. :~ . , from the flip flop 117 and the signal (f3). During the appllcation of -the signal Sv having logic "0" to the fiop flop 117, the above recited equation (5), that is f3=fl+f2 is satisfied every time the rising edge of the signal (f2) (see Fig. 12, line 3) is applied to the AND gate 113. The signals (~1) and (f2) are applied to the AND gate 113.
The output from the gate 113 is differentiated by means of both the flip flop 114 and the AND gate 115. Thus, ~ the output from the gate 115 has the frequency f2 and the pulse width is equal to the period of the signals (f0) (see Fig. 12, lines 1 and 5). The output from the gate 115 is delayed by the flip flops 116 and 117. Then both the Q-output of the flip flop 116 and the inverted signal (fl) are applied to the NOR gate 112. The output from this gate 112 is represented by the waveform shown in Fig. 12, line 7. Thus, the clock signal having the frequency f3 (=fl+f2) is produced frorn the circuit 53'. When the signal Sv having logic "1" is applied to the flip flop 117, the Q-output of the flip flop 117 becomes logic "0", ; 20 and accordingly the pulse insertion is stopped. Thereafter, the frequency f3 is held being the frequency which is equal to fl.
Fig. 13 is a circuit diagram illustrating details of the aforesaid selec-tion circuit 130. The selection circuit 130 discriminates the large and small of the absolute peak levels between the positive signal St (45) ~and the negative signal St (44) both being located close to their nearest virtual zero crossing Z35 (see Fig. 4), ::
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and the circuit 130 produces the selection signal SQ. The signal S having logic "l" indicates that the pulse insertion should be performed (corrësponding to f3=fl-~f2) and the circuit 53' of Fig. ll should be actuated. The signal sl~
having logic "0" indicates that the pulse removement should be performed (corresponding to f3=fl-f2)~ and accordingly the circuit 53 of Fig. 7 should be actuated.
The circuit 130 receives the timing signal St ~see Fig. 5).
- The signal St is applied to a first latch circuit 131 and stored momentarily therein in synchronous with the frequency of the sampling signal Ss. The most significant bit (MSB) of the signal St is directly applied to the circuit 131, while the other bits of the signal are applied thereto by way of EOR ~Exclusive OR) gates 133. Since the MSB, which indicates the polarity of the signal St , is commonly applied to the EOR gates 133, the outputs from the EOR
gates represent the absolute peak volue of each signal St.
The output from the circuit 131 is transferred to a second latch circuit 132 and stored therein in synchronous with the frequency of the sampling signal Ss. Accordingly, the circuit 131 stores the absolute peak value of the present signal St , while the circuit 132 stores the absolute peak value of one preceding signal St. The absolute peak value A from the circuit 132 is compared with the absolute value B from the circuit 131 by means of a comparator 134. The result from the comparator 134 is applied to a delay fllp flop 135, at its D-input~ The flip flop 135 produces the signal S~ , at its Q-output. However, the signal S~ is , . , . : ; :

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2~6 available only when a clock signal, which is identical with the sampling signal Ss ~ is applied to a CLK-input of the flip flop 135. ~his clock signal is produced from an AND gate 138 only when an AND gate 137 produces output having logic "1". The gate 137 receives both the MSBB
stored in the circuit 131 via an inverter 136 and the MSBA
stored in the circuit 132. Accordingly, the AND gate 137 produces logic "1" only when the MSBA is logic "1" and, at - the same time, the MSBB is logic "0". When the signals St (44) and St (45) (see Fig. 4) are stored, respectively in the circuits 132 and 131, the MSBB is logic "1" and the ~SB~ is logic "0". Therefore, the AND gate 137 and also the AND gate 138 become open, and then the result of the comparison, in the comparator 134, between the outputs A
and B is available. If the output A ~corresponding to the signal St (44)) is larger than the output B (corresponding to the signal St (45)), the signal SQ becomes logic "1".
If the output A is smaller than the output B, the signal S~ becomes logic "0", wherein these logics "1" and "0", respectively indicate the a:Eoresaid pulse insertion (corre-sponding to the equation f3=fl~f2) and the pulse removement (corresponding to the equation f3=fl-f2)-Now, a second embodiment of the timing-phase recovery circuit according to the present invention will be described.
In Fig. 14, which is a block diagram illustrating the second embodiment of the timing-phase recovery circuit of the present invention, a timing-phase recovery circuit 140 is comprised of a pulse control ci.rcuit 141, a pseudo : ~ ... .. . .

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sampling pulse insertion circuit 142, a pulse number setting circuit 143 and also the aforementioned circuits 21, 22, 51, 54 and 55. The meaning of the symbols CLK, fl , f3 , S5, Ain and Sv have already been explained.
The operation of this circuit 140 will be clari~ied by referring to Fig. 15. The imaginary pulse train of the digital output from the circuit 142 is depicted in line 1) of Fig. 15, and the imaginary pulse train of the timing signal from the timing signal extracting circuit 22 is depicted in line 2) of the Fig. 15. Referring to both Figs. 14 and 15, the pulses lSl and 152 represent the actual sampled signal. Accordingly, the period ~.r between the pulses 151 and 152 equals to l/fs ~ that is T=l/fs , where fs is the frequency of the sampling signal Ss.
Pulses 153-1, 153-2, 153-3 are pseudo sampling pulses generated by the pseudo sampling pulse insertion circuit 142.
Accordingly, each period ~; between each two adjacent pulses e~uals to ~ , where k is the number of pseudo sampling pulses 153-1, 153-2, 153-3. In this case, k is equal to 3. Each pseudo sampling pulse has a zero value.
Therefore, these pseudo sampling pulses do not cause any bad effects on the tuning operation. Since the sampling signal having a high frequency of (k~l)fs is applied to the timing signal extracting circuit 22, a timing signal St' having the frequency of (k+l)fs is produced from the circuit 22. The timing signal St' from the circuit 22 is depicted in line 2) in Fig. 15. It should be noted, in this line 2), that the hatched timing signal 154 is in-phase : : ~ : :.
,. ...
.- : :~
.. . .. .. ..

:.-~': :: ' with the sampliny p~llses 151, 152 and so on (see line 1)), while the non-hatched pulses 155 are in-phase with the .. . . .
pseudo sampling pulse 153-1, 153-2 and so on (see line 1)). Each period between each two adjacent timing signals (154, 155) is ~ . In this line 2), the virtual zero crossings are indicated by reference symbols Zo ~ Zl and so on. However, only the zero crossing Zl is available, as has already been explained by referring to Fig. 4 with regard to the virtual zero crossings Z33 , z35 and so on.
The advantage o~ the second embodiment shown in Fig. 14 resides in that the virtual zero crossing can be detected instantaneously. This is because, ~or example, the location of the virtual zero crossing Zl ~see line 2) in Fig. 15) can be detected by the nearest timing signal 156 or 157.
The detection of the zero crossing Zl can be achieved by means of the virtual zero crossing detector 55, which has already been explained hereinbefore. If the zero crossing Zl is detected by the real timing signal St' such as the signal 157, the tuning operation is completed instantane-ously. This is because the real timing signal is in-phase with the sampling signal Ss of the timing-phase recovery circuit~ Contrary to this, if the zero crossing Zl is detected by the pseudo timing signal (or interpolated timing signal) St' such as the signal 156, it is necessary to substitute the si~nal 156 for the real timing ~non-inter-polated) signal. This is because the non-hatched timing signal is not in-phase ~ith the sampling signal Ss.

Therefore, the pulse number setting circuit 143 and also , , , , . , /

~ ~f~

the pulse control circuit 141 ~see Fig. 14) are introduced into the timing-phase recovery circuit. The circuit 143 counts a different number of timing signals between the pseudo timing signal, which has detected the virtual zero crossing, and the nearest real timing signal. Then the different numbers counted ~rom the circuit 143 are supplied to the circuit 141. If the different number counted is zero, the clock signal (fl) from the divider 51 is not processed. If the counted number is not zero, the clock signal (fl) is transformed to the clock signal (f3) by means of the circuit 141, in order to cause the sampling signal Ss to be in-phase with the frequency of the virtual zero crossings. Specifically, the circuit 141 removes the same number of clock pulses as said different numbers counted from the clock signal (fl).
In Fig. 16, which is a circuit diagram illustrating details of the circuits 141 and 143 shown in Fig. 14, a block 141 is idenkical with the circuit 141 of Fig. 14 and a block 143 is identical with the circuit 143 of Fig. 14.
Signals Sp , Scl ~ Ss and Sv are also shown in Fig. 14.
The circuit 141 is comprised merely of a NOR gate 161 which receives both the clock signal Scl having the frequency o~ Fl ~fl = fo/N) and the signal Sp. The circuit 143 is comprised of the so-called bidirectional shift register 162, for example SN74198 products of Texas Instruments Co., ~td., and an AND gate 163. The register 162 is cleared to its initial state by the sampling signal S
whereby the logic all "0" is stored therein. Then the : , . . . . .

.. . .. ..

2~

logic "1" is supplied thereto from an Lin input one-by-one in a rightward direction during which the signal Sv is logic "0" which indicates the virtual zero crossing is not yet detected. In this time, the ~ND gate 163 is not open.
When the signal Sv changes from logic "0" to logic "1", the AND gate 163 i5 opened. At the same time, a shift in direction of the logic stored in the register 162 is ~ inverted, because logic "1" is applied to the register ; 162, at its L/R-input. Thereafter, logic "0" is supplied thereto from an Rin-input. Accordingly, each logic "1"
which has already been stored in the register 162 is poured one-by-one from a Q-output thereof, and then applied to the NOR gate 161 by way of the AND gate 163, in synchronous with the clock signal ~fl) which is applied to a CLK-input thereof. It should be noted that the number of logic "1"
which has been stored in the register 162 is the same as the aforesaid different number of timing signals the pseudo timing signal has detected between the virtual zero crossing and the nearest real timing signal. Consequently, the NOR
gate 161 is being closed during which a signal Sp having logic "1" is supplied one-by-one from the AND gate 163 to the NOR gate 161, and the clock signal (fl) is stopped being provided from the NOR gate 161. As a result, the sampling signal Ss from the divider 54 becomes in-phase with the frequency of the virtual zero crossings.
In Fig. 17, which is a circuit diagram illustrating details of the pseudo sampling pulse insertion circuit 142 of Fig. 14, the circuit 142 is comprised of an AND gate 171, . ..
..

... :. . .

82~
~ 2~ -a delay flip flop 172, AND gates 173 and a latch circuit 174. The flip flop 172 is driven by a clock signal HSS
having the frequency of (k+l)fs , where fs is the samplir~g frequency. ~he signal HSS ma~ be produced by a suitable freguency divider (not shown) which receives the reference clock signal CL~ (see Fig. 14). When the sampling signal Ss is applied, via the A~D gate 171, to the flip flop 172, the Q-output thereof changes logic "0" to "1". Then the ~ AND gates 173 opens, and the sampled signal from the sampling circuit 21 (see Fig. 14) is stored momentarily in the circuit 174. The stored sampling signal is then applied to the timing signal extracting circuit 22 ~see Fig. 14), and the circuit 22 produces the aforesaid real timing signal St'. When the Q-output changes logic lOI to "1", the Q-output changes logic "1" to "0". Accordingly, this causes the AND gate 171 to be close. At the same time, the AND gates 173 are closed and the circuit 174 sequentially s~ores logic "0" in synchronous with the application of the ~ISS. The sequentially stored logics "0" are then applied to the circuit 22 as the aforesaid pseudo timing signal St'.
A modified arrangement of the blocks 21, 142 and 22 shown in Fig. 14 will be proposed. Fig. 18 is a block diagram showing the above mentioned modified arrangement.
In Fig. 18, a pre-filter 181 is newly introduced, and the circuit 142 is located between the squarer 101 and the narrow band pass filter 102 (see Fig. 10). The advantages of the arrangement are as follows. First, a noise contained .:
: ~ . : .,, ~ ~ . :
:, .: : ~ , . .

2.~

in the anologue input signal Ai~ is extracted in advance from the filter 181 which has very narrow band pass frequency range, for example, one half of the frequency of the timing signal. Second, the pre-filter 181 and the squarer lOl can operate with relatively low operational speed, because the pseudo sampling pulse insertion circuit 142 follows after the circuits 181 and 101.
Now, a third embodiment of the timing-phase recovery circuit according to the present invention will be described by referring to Fig. 19. In Fig. l9, there is a frequency switching circuit 191 and a switch control circuit 192.
The operation of the circuit l90 will easily be clarified by reEerring to an imaginary analogue waveform of timing signal shown in Fig. 20. Referring to Fig. 20, in an initial interval To , a five timing signal 201 is produced, said signal 201 having a high frequency. Accordingly, the virtual zero crossing Zl is detected instantaneously by the corresponding fine timing signal 201'. Then a next interval Tl starts. In the interval Tl , a coarse timing signal 202 is produced, each signal 202 corresponds to the foresaid usual timing signal St. Thus, the tuning operation is completed in a very short time. Further, the frequency divider 54 is reset to its initial state by a reset signal Y (see Fig. l9) from the circuit 192, which signal Y is produced when the zero crossing Zl is detected by the signal 201'. Therefore, the sampling signal Ss is, instan-taneously, caused to be in-phase with the frequency of the ; zero crossings. Referring to both Figs. 19 and 20, the ::

~ ~ " ~ ~ , :; . . ~ .
....

- 28 ~

fine timing signal 201 is o~tained by sampling the signal Ain in synchronous with a clock signal Ss' having a high frequency. The signal Ss is produced from the divider 51. When the virtual zero crossing Zl is detected by the circuit 55, the switch control circuit 192 produces a switching signal X and applies this to the circuit 191.
Then the circuit 191 produces not the clock signal 5s' but rather the sampling signal Ss ~ and the interval T
~ starts.

In Fig. 21, which is a circuit diagram illustrating details of the freyuency switching circuit 191 of Fig. 20, the circuit 191 is comprised of an AND gate 211 which receives the signal Ss' , an AND gate 212 which receives the signal Ss and a OR gate 213. When the signal X having logic "0" is supplied from the circuit 192, only the AND
gate 211 opens due to the presence of an inverter 214.
The signal X havirg logic "0" indicates that the virtual zero crossing is not yet detected. Accordingly, the signal Ss' havlng a high fre~uency is produced from the OR gate 213. When the virtual zero crossing is detected, the logic of the signal ~ changes from "0" to "1". Accord-ingly, the usual sampling signal Ss is produced from the OR
gate 213~
In Fig. 22, which is a circuit diagram illustrating details of the circuit 192 shown in Fig. 19, the circuit 192 is comprised of a delay flip flop 221 and an AND gate 222. As seen from Fig. 22, -~he switching signal X is the same as the virtual zero crossing signal Sv from the s : ' . , ' . ' i ' '': ' : ' ' '; ' "' ' ' ' ' '': ' ;' "' : . ' ~ : : ' ' , "'' '". ' ' , " ' ' ' ' ~ ' ' "".' ' ' . ' 'i 2~

circuit 55 (see Feg. 19 and refer to Fig. 6). Since both the flip flop 221 and the AND gate 222 operate as a differen-tiating circuit, the reset signal Y is substantially the same as the rising edge of the signal X. Therefore, the pulse width of the signal Y is very narrow, and the divider 54 (see Fig. 19) is reset to its initial state with a capabilty of a very fine timing resolution which is compar-able with the narrow pulse width of the reference clock signal CLK.

As mentioned above, the tuning operation o~ the timing-phase can be completed in a very short time by utilizing either one of the timing-phase recovery circuits shown in Figs. 5, 14 and 19. However, since the timing signal St always includes the so-called timing jitter and small frequency offset, a steady state-tuning operation should be followed after the aforesaid tuning operation, in order to cancel the timing jitter and timing frequency offset. Once the tuning operation is completed, the sampling signal Ss is maintained to be in-phase with the frequency of the virtual zero crossings~ however, the actual sampling signal Ss is not correctly in-phase therewith due to the presence of the timing jitter. Therefore, it is further required to employ a circuit into each of the ; above mentioned timing-phase recovery circuits 50, 140 and 190 for suppressing the timiny jitter. Ir, Fig. 23, which is a circuit diagram illustrating the circuit for suppressing the timing jitter, the jitter suppressing circuit 230 is constructed as a part of a reference clock generator which ~ . . . . .

produces the aforesaid reference clock signal CLK (refer to Fig. 2, 5, 14, 19 or 22). The circuit 230 coopera-tes with a reference oscillator 231. The oscillator 231 produces a clock signal CLK' which has a frequency being slightly higher than the nominal frequency f0 by ~ f. The f is, for example about 100 Hz. The clock signal CLK' is applied to an AND gate 236 which produces the reference clock signal CLK. The AND gate 236 is caused to be closed ~ when the phase of the sampling signal leads with respect to the phase of the frequency of the virtual zero crossings.
In this case, the timing siynal St appears slightly before the appearence of the virtual zero crossing Irefer to the timing signal, for example the signal 44 shown in Fig. 4).
In such a case, the MSB of the timing signal St is logic "1", because the polarity of this signal is nega-tive. The MSB having a logic "1" is momentarily stored in a register 232, and then applied to a delay flip flop 233. Accordingly, a Q-output having a logic "1" of the flip flop 233 is applied to a NAND gate 234. At this time, a delay flip flop 235 produces a logic "1" at its Q-output, which logic "1" is also applied to the NAND gate 234. Therefore, the NAND gate 234 produces logic "0" when the logic "1"
of a clock signal CLKN is applied thereto. The logic "0"
from the Q-output of the flip flop 235 closes the AND gate 236. Since the AND gate 236 is caused to be close, the frequency of the reference clock signal CLK is reduced to (f0 - ~f). Once the Q-output of the flip flop 235 becomes logic "0", the NAND gate 234 is closed again. A clock , - -:-., : ,:. - , - .;

2~

signal CLKS is applied to the flip flop 233 at its CLK-input.
The signal CLKS has a frequency which is one fourth of the sampling frequency fs. That is, the signal CL~S is produced neary in-phase with the virtual zero crossings, for example Z33 , Z35 and so on as shown in Fig. 4. The clock signal CLKN has a frequency of 2 ~ f, for example about 200 H~.
The signal CLKN is derived from the clock signal CLK' (fO ~ ~ f) via a frequency divider 237. the signal CLKS
- is derived from the clock signal CLK' via the divider 237 and a frequency divider 238.
Contrary to the above, if the phase of the sampling ;
signal lags with respect to the phase of the timing signal, the Q-output of the flip flop 233 produces logic "0", and accordingly the AND gate 236 opens. Therefore, the clock signal CLK having the frequency of (fO ~ Gf) is provided.
Thus, the timing jitter included in the timing signal St , can be suppressed.
As explained above, the present invention is very useful for achieving a very quick tuning operation of the timing-phase recovery circuit.
While there has been described what is considered to be a preferred embodiment of the invention, variations and modifications in the invention may occur to those skilled in the art once they become acquainted with the invention.
Therefore, it is intended that the appended claims shall be cons-trued as including all such variations and modifications as would occur to one of ordinary skill in the art.

. , , , , , .......................... ,. , , :
.: ~ , .. ..
.~ , ,

Claims (19)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A timing-phase recovery circuit used for achieving a tuning operation between a phase of a sampling signal generated in a receiver and a phase of a timing signal included in a received input analogue signal, comprising:
a) a reference clock generating means for producing a reference clock signal;
b) a sampling signal generating means for producing the sampling signal which is derived from the reference clock signal;
c) a sampling means for producing a sampled input signal by using the sampling signal;
d) a timing signal extracting means for producing the timing signal from the sampled input analogue signal, and;
e) a virtual zero crossing detecting means for comparing the value of the timing signal with a zero value and producing a virtual zero crossing detecting signal by using the sampling signal;
wherein the sampling signal generating means operates to conduct a phase shift of the sampling signal in accordance with the existence or non-existence of the virtual zero crossing detecting signal.

2. A circuit as set forth in claim 1, wherein the virtual zero crossing detecting means is comprised of: a latch circuit which receives the timing signal and stores therein in synchronous with the sampling signal, which timing signal is expressed by a two's-complement indication;
a first NAND gate and a first NOR gate, each of which gates receives the upper few bits, other than a most significant bit, of the timing signal supplied from the latch circuit; a second NAND gate and a second NOR gate which receive the outputs from the first NAND gate and the first NOR gate, respectively, at respective first inputs, and also commonly receive said most significant bit, at respective second inputs; a first AND gate which receives, at respective inputs, both the output from the second NOR
gate via an inverter and the output from the second AND
gate; a delay flip flop which receives said most significant bit and the sampling signal, at its CLOCK-input and D-input respectively; and a second AND gate which receives both the output from the first AND gate and a signal from a Q-output of the delay flip flop and produces the virtual zero crossing detecting signal.

3. A circuit as set forth in claim 1, wherein the sampling signal generating means is comprised of both a frequency dividing means which divides the frequency of the reference clock signal and a pulse control means which cooperates with the frequency dividing means, and the phase shift of the sampling signal is conducted by removing some pulses from the pulse train of the divided reference clock signal, when the virtual zero crossing detecting signal exists.

4. A circuit as set forth in claim 1, wherein the sampling signal generating means is comprised of both a frequency dividing means which divides the frequency of the reference clock signal and a pulse control means which cooperates with the frequency dividing means, and the phase shift of the sampling signal is conducted by inserting some pulses into the pulse train of the divided reference clock signal, when the virtual zero crossing detecting signal exists.

5. A circuit as set forth in claim 1, wherein the sampling signal generating means is comprised of both a frequency dividing means which divides the frequency of the reference clock signal and a pulse control means which cooperates with the frequency dividing means, and the phase shift of the sampling signal is conducted by removing some pulses from the pulse train of the divided reference clock signal or inserting them into the pulse train when the virtual zero crossing detecting signal exists.

6. A circuit as set forth in claim 1, wherein the sampling signal generating means further includes a sampling signal insertion means for inserting a pseudo sampling signal having a zero value into a real sampling signal; a frequency dividing means which divides the reference clock signal and a pulse control means which cooperates with the frequency dividing means; and the zero corssing detecting means receives the digital timing signals which have been sampled by both the real and the pseudo sampling signals, the phase shift is conducted by removing pulses from the pulse train of the divided reference clock signal, the number of the pulses to be removed is determined by the number of the timing signals which exist between the pseudo sampling signal located at the virtual zero crossing and the nearest real sampling signal.

7. A circuit as set forth in claim 1, wherein the sampling signal generating means further includes a frequency dividing means which divides the frequency of the reference clock signal into a first divided clock signal and a second divided clock signal; and also includes a pulse control means which cooperates with the frequency dividing means, and the pulse control means provides, at first, the first divided clock signal, as a first sampling signal, to the sampling means; then the pulse control means provides the second divided clock signal thereto as a second sampling signal when the timing signal sampled by the first sampling signal is located at the virtual zero crossing; thereafter the frequency dividing means provides the second sampling signal as the usual sampling signal, where the frequency of the first sampling signal is higher than that of the second sampling signal.

8. A circuit as set forth in claim 3, wherein the timing-phase recovery circuit is comprised of.
a 1/N frequency divider which divides the frequency of the reference clock signal; a 1/M (M = k N, where N ? 2) frequency divider which also divides the frequency of the reference clock signal; a pulse control circuit which receives both divided clock signals from the 1/N and 1/M
frequency dividers; a 1/L frequency divider which produces the sampling signal; a sampling circuit which receives the input analogue signal and produces a sampled signal therefrom in synchronous with the sampling signal, and; a timing signal extracting circuit which extracts the timing signal from the sampled signal; a virtual zero crossing detecting circuit which receives the timing signal from the timing signal extracting circuit, wherein the pulse control circuit performs the phase shift with respect to the output from the 1/N frequency divider every time the output from the 1/M frequency divider is applied to the pulse control circuit during the time when the zero crossing detecting circuit provides no virtual zero crossing detecting signal thereto.

9. A circuit as set forth in claim 8, wherein the pulse control circuit is comprised of an AND gate which receives, at its first input, the output from an 1/M
frequency divider, a delay flip flop which receives, at its D-input, the output from the AND gate, a NOR gate which receives, at its first input, the signal from the output and also receives, at its second input, the output from the 1/N frequency divider, the output from which 1/N frequency devider is also applied to the delay flip flop, at its CLOCK-input, the delay flip flop applies, from its Q-output, the signal to a second input of the AND
gate, the delay flip flop is cleared by the application of the virtual zero crossing detecting signal thereto at its RESET-input, the output form the NOR gate being applied to the 1/L frequency divider.

10. A circuit as set forth in claim 8, wherein the pulse control circuit is comprised of a first AND gate which receives, at its first input, the output from the 1/N frequency divider and also, receives, at its second input, the output from the 1/M frequency divider; a first delay flip flop which receives, at its D-input the output from the first AND gate, a second AND gate which receives, at its first input the output from the first AND gate and also receives, at its second input, the signal from the Q-output of the first delay flip flop, a second delay flip flop which receives, at its D-input, the output from the second AND gate, a third delay flip flop which receives, at its D-input, the signal from the Q-output of the second delay flip flop, and OR gate which receives, at its first input, the output from the 1/N frequency divider and also receives, at its second input, the signal from the Q-output of the third delay flip flop, each CLOCK-input of the first, second and third delay flip flops receives the reference clock signal, the third delay flip flop being cleared by the application of the virtual zero crossing detecting signal thereto, the output from the OR gate being applied to the 1/L frequency divider.

11. A circuit as set forth in claim 5, whrein a selection circuit is further included, the selection circuit determines whether the phase shift should be conducted by removing or inserting the pulses in accordance with a result of a comparison of the values of the suceeding first and second timing signals, which exist, respectively before and after the appearence of the virtual zero crossing.

12. A circuit as set forth in claim 11, wherein the selection circuit is comprised of: EOR gates which receive, at their respective first inputs, corresponding bits of the timing signal other than a most significant bit indicating the polarity thereof, the timing signal being expressed by a two's-complement indication, second inputs of which EOR gates commonly receive the most signifi-cant bit; a first latch circuit which recieves the outputs from the EOR gates and the most significant bit in synchro-nous with the sampling signal; a second latch circuit which receives the output from the first latch circuit in synchronous with the sampling signal; a comparator which compares the output values of the first and second latch circuits; a delay flip flop which receives, at its D-input, the output from the comparator; a first AND gate which receives, at its first input, the most significant- bit stored in the second latch and also receives, at its second input, the most significant bit stored in the first latch circuit by way of an inverter; a second AND gate which receives, at its first input, the sampling signal and also receives, at its second input, the output from the first AND gate, and the CLOCK-input of the delay flip flop receives the output from the second AND gate.

13. A circuit as set forth in claim 6, wherein the timing-phase recivery circuit is comprised of: an 1/N
frequency divider which divides the frequency of the reference clock signal; a pulse control circuit which receives the output from the l/N frequency divider; an l/L

frequency divider which receives the output from the pulse control circuit and produces the sampling signal; a sampling circuit which receives the input analogue signal and produces sampled signal in synchronous with the sampling signal; a sampling signal insertion circuit which inserts a pseudo sampled signal which is sampled by a pseudo sampling signal having a zero value, into the real sampled signal; a timing signal extracting a circuit which extracts the timing signal from the output signal supplied from the pseudo sampling signal insertion circuit, which timing signal is a signal sampled by both the real and the pseudo sampling signals; a zero crossing detecting circuit which receives the timing signal from the timing signal extracting circuit in synchronous with the real sampling signal, and;
a pulse number setting circuit which is controlled by both the virtual zero crossing detecting signal and the real timing signal and produces a pulse number setting signal which represents the number of pulses between the pseudo timing signal located at the virtual zero crossing and the nearest real timing signal; wherein the pulse shift is conducted by the pulse control circuit in accordance with the pulse number setting signal.

14. A circuit as set forth in claim 13, wherein both the pulse control circuit and the pulse number setting circuit are comprised of a bidirectional shift register which receives, at its CLOCK-input, the output from the l/N frequency divider and also receives, at its CLEAR-input, the sampling signal; an AND gate which receives both a signal from the Q-output of the bidirectional shift register and the virtual zero crossing detecting signal; a NOR gate which receives both the outputs from the l/N frequency divider and the AND gate and produces the output to be applied to the l/L frequency divider, the virtual zero crossing detecting signal is also applied to the L/R-input of the bidirectional shift register, further a Lin-terminal and a Rin-terminal, respectively receive an input having logic "1" and an input having logic "0".

15. A circuit as set forth in claim 13, wherein the sampling signal insertion circuit is comprised of:
first AND gates which receive, at their respective first inputs, corresponding bits of the timing signal which is expressed by a two's-complement indication; a latch circuit which receives the output from the latch circuit and produces output to be applied to the timing signal extracting circuit, a delay flip flop which produces a signal from the Q-output to be applied commonly to the respective second inputs of the first AND gates; a second AND gate which receives at its first input, the sampling signal having a frequency fs and also receives, at its second input, the signal from the Q-output of the delay flip flop; wherein a sampling signal having a frequency fs' (fs' > fs) is applied to both the CLOCK-inputs of the delay flip flop and the latch circuit.

16. A circuit as set forth in claim 13, wherein the timing signal extracting circuit is comprised of a digital squarer and a digital narrow band pass filter.

17. A circuit as set forth in claim 15, wherein a pre-filter is further included, a series connection of the pre-filter and the digital squarer being located between the sampling circuit and the sampling signal insertion circuit, the digital narrow band pass filter follows at the output of the sampling signal insertion circuit and is connected to the virtual zero crossing detecting circuit.

18. A timing-phase recovery circuit as set forth in claim 1, wherein the reference clock generating means further cooperates with a circuit for suppressing a timing jitter and frequency offset included in the timing signal.

19. A timing-phase recovery circuit as set forth in claim 18, wherein the circuit for suppressing the timing jitter includes an oscillator which produces a clock signal, the frequency of the clock signal being slightly higher than a nominal frequency (f0) of the reference clock signal by a frequency (.DELTA. f), the frequency of the reference clock signal variable from (f0 - .DELTA. f) to (f0 + .DELTA. f) in accordance with difference between the phase of the sampling signal and the phase of the timing signal.