CA1088190A - Integrated photoelectrical conversion - Google Patents
Integrated photoelectrical conversionInfo
- Publication number
- CA1088190A CA1088190A CA288,213A CA288213A CA1088190A CA 1088190 A CA1088190 A CA 1088190A CA 288213 A CA288213 A CA 288213A CA 1088190 A CA1088190 A CA 1088190A
- Authority
- CA
- Canada
- Prior art keywords
- junction
- photoelectric conversion
- conversion cell
- cells
- heat sink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000002955 isolation Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical group [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 3
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 claims 2
- 229940000425 combination drug Drugs 0.000 claims 1
- 238000011065 in-situ storage Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 239000012777 electrically insulating material Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000002470 thermal conductor Substances 0.000 description 2
- 241000478345 Afer Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/60—Arrangements for cooling, heating, ventilating or compensating for temperature fluctuations
- H10F77/63—Arrangements for cooling directly associated or integrated with photovoltaic cells, e.g. heat sinks directly associated with the photovoltaic cells or integrated Peltier elements for active cooling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
- H10F19/20—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising photovoltaic cells in arrays in or on a single semiconductor substrate, the photovoltaic cells having planar junctions
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
INTEGRATED PHOTOELECTRICAL CONVERSION
ABSTRACT OF THE DISCLOSURE
Photoelectric conversion cells, wherein the individual cells are thermally connected to and electrically isolated from an electrically conducting heat sink, may be connected in integrated array form by forming individual planar devices and interconnecting in situ on an electrically insulating substrate which is thermally bonded to the heat sink.
ABSTRACT OF THE DISCLOSURE
Photoelectric conversion cells, wherein the individual cells are thermally connected to and electrically isolated from an electrically conducting heat sink, may be connected in integrated array form by forming individual planar devices and interconnecting in situ on an electrically insulating substrate which is thermally bonded to the heat sink.
Description
8 B~C~GROU~ OF THE I`rV~:'rLO;I
9 r~lere are man~ app.lications in the art requiri-.~ lar~er currents and vol~ages than indi-~idual cells can pro~ e. Sinc~ p,.otoelectric con-ll verters provide an output of only 0.5 to l.O volts it is often n~CesSar~J
1~ to connect sevPral converters in s~ri~s in order to get ~ ~esire(l outp~t 13 voltago. Ihe individual converters, ho-~e~er, lcse efEic_~ncy as the 1~ te~perature rises so that i~ is also desirable to bond each converter to a large heat sink which is usually formed cf an electrirally conducting 16 material but each cell must remain electrically isolated Lhere~rom.
17 The art of building devices for lar~er voltag~s thu~ h~ratofore has 18 involved co~plex assembly and material problems. An e~2~ple of ~uch an 19 assembly is sho~n in U. S. Patent ~o. 3,833,425 wh~rein sisc.ete con-verters are assembled with discrete electrical isolators and the combina-21 tion is bonded to a large metal substrate for te~peratu.~ contrcl.
23 In~application Serial No.~ ~75~IBM Docket Y09-76-024) filed 24 ~ p~ ~2~ 7~, there is disclosed a technique wherein discrete photo-electric converters are formed on an electrically insulating material, 26 which serves as both an electrical 3solator and a thermal conductor.
YOg-76-049 -1-:~131~
1 SUM~ Y OF T~IE II~VENTIOr~l
9 r~lere are man~ app.lications in the art requiri-.~ lar~er currents and vol~ages than indi-~idual cells can pro~ e. Sinc~ p,.otoelectric con-ll verters provide an output of only 0.5 to l.O volts it is often n~CesSar~J
1~ to connect sevPral converters in s~ri~s in order to get ~ ~esire(l outp~t 13 voltago. Ihe individual converters, ho-~e~er, lcse efEic_~ncy as the 1~ te~perature rises so that i~ is also desirable to bond each converter to a large heat sink which is usually formed cf an electrirally conducting 16 material but each cell must remain electrically isolated Lhere~rom.
17 The art of building devices for lar~er voltag~s thu~ h~ratofore has 18 involved co~plex assembly and material problems. An e~2~ple of ~uch an 19 assembly is sho~n in U. S. Patent ~o. 3,833,425 wh~rein sisc.ete con-verters are assembled with discrete electrical isolators and the combina-21 tion is bonded to a large metal substrate for te~peratu.~ contrcl.
23 In~application Serial No.~ ~75~IBM Docket Y09-76-024) filed 24 ~ p~ ~2~ 7~, there is disclosed a technique wherein discrete photo-electric converters are formed on an electrically insulating material, 26 which serves as both an electrical 3solator and a thermal conductor.
YOg-76-049 -1-:~131~
1 SUM~ Y OF T~IE II~VENTIOr~l
2 Photoelectrical conversion cell a~ra~s may be fabricated using
3 planar integrated circuit technology, i.e., epitaxial growth, lithographic
4 and masking techniques, diffusion and alloying steps on a substrate of electrically insulating material to provide an array in which optimum 6 control of heat conductivity, electrical isolation, cell combination 7 flexibility and cell electrode spacing are achieved.
9 FIG. 1 is a view of an integrated photoelectric conversion cell array.
11 FIG. 2 is a detailed view showing the vertical aspects of the 12 photoelectrical conversion cell.
13 FIG. 3 is a view showing the contact and isolation of the 14 photoelectrical conversion cell.
DETAILED DESCRIPTION
16 In accordance with the invention the cells are fabricated in 17 situ on a broad area substrate by such techniques, at this state of the 18 art, of masking, photochemical exposure, oxidation and/or nitridation 19 to control the precise horizontal introduction by diffusion or ion im-plantation fcr precise vertical control of conductivity type determining 21 i~purities, of isolation between cells, of positioning and depth of 22 penetration of contacts to the cells and of electrical configuration of 23 the array by vapor deposited metallurgy. The broad area substrate is 24 equipped with a region of insulating material having electrical resist-ivity properties sui~able for electrical isolation and having a thickness 26 dimension small enough to permit efficient thermal dissipation into a 27 broad area heat sink. The technique of the use of insulating epitaxial 2~ material has been shown in the raferenced copending application.
1 Referrin~ to FIG. 1 the broad area substrate 1 is sho~m 2 schematlcally as a single crys~al semlconductor wa~er. The ~"afer 15 a 3 standard e~tensively used semiconductor :intermediate manufacturinz 4 product. Much processing and handling manufacturing capital equipment is available in the art to facilitate building devices using this inter-6 mediate product. Other broad area manufacturing intermediate products 7 such as dendritic webs, ribbons and thin film semiconductor layers on 8 insulating substrates, currently receiving attention in the art, may be 9 employed. The broad area substrate has an active region lA in which the photoelectrical conversion takes place and an insulating region 13 11 which serves to electrically isolate the individual cells from a support-12 ing and heat sinking member 2. While the demarcation between the regi.ons13 1~ and lB is shown as a line, there are instances where a precise defini-14 tion would not take place. For example, we consider the case where a semiconductor material is employed, such as gallium arsenide (GaAs). This 16 material is capable of exhibiting insulating properties by control of the -17 impurity concentration therein, hence there would be a more or less con- ;
18 tinuous variation as the wafer is formed, from the required impurity 19 type and concentration adjacent the photoelectrical conversion region lA
to a dif~erent value in the lnsulating region lB, hence a precise line 21 may not occur. The high resistivity gallium arsenide (Ga~s) is kno~
22 in the art as semi-insulating gallium arsenide (GaAs).
23 The heat sinking member 2 serves both as a physical support 24 and a thermal conductor. Typically it is metallic in nature. The brcad ~ -area substrate 1 may be quite thin, of the order of 0.010 inches for some 26 materials so that physical support is needed. Good thermal conductivity 27 is essential to maintaining temperature control. These requirements are 28 satisfied with a metal which in turn may be equipped with further convec-:29 tion or radiation heat conducting capability such as fins or liquid tubes not shown. There should be reasonable expansion compatability between the Yo976-049 - 3 -',. ' .
- , , ; .
1 heat sink member 2 and the substrate 1, the requirement i9 not as 2 rigorous as it would be were the active region to be closer A low 3 melting metal bolld such as solder is generally satisfactory.
4 The individual device cells are shown schematically as arranged in rows and columns although with the flexibility of the integrated technology no specific conEiguration is required. Further, the array 7 may occupy only one portion of a broad area substrate member 1, the other 8 portions of which may be devoted to devices for other purposes.
9 In accordance with the invention, isolation 4 is provided between the device cells. There are various techniques of isolation prac-11 tised in the integrated semiconductor device technology such as the use 12 of p-n junctions, the introduction of dielectrics, the use of a differen-13 tial in substrate surface level and the use of diffused or implanted 14 impurity species. The isolation provides the ability for flexible inter-connection of wiring patterns.
16 In FIG. 1 the isolation 4 is shown as a channel to the depth 17 of the active region filled with a dielectric, for e~ample an oxide.
18 Where for example, the active region is at or closer to the surface such 19 as through the use of a Schottky barrier for the photoelectrical converter the isolation may not need to penetrate the surface deeper than one or 21 two microns.
22 Tne individual device cells are shown schematically in FIG. ].
23 as connected via electrodes 6 in series paths for voltage addition, the 24 paths in turn being connectable in parallel for current addition.
The details of cell structure may be seen in connection with ~ -26 FIGS. 2 and 3. FIG. 2 shows the contact metallization and cell passivation.
27 In FIG. 3 a cross section of the individual cell is shown illustrating the 2~ active region, the passivation, the surface electrode and the reach through29 connection techniques.
Y0976-049 - 4 - `~
, 1 Referring tO FIG. 2 the phol:oelectrical conversion cell is 2 designed for the efficient uti.li~ation of hole-electron pairs produced 3 by incident light to produce a voltage betweerL the terrni.nals. T~e 4 op~imum is to have the semiconductor junction within the diffusion len~th of the average light produced carrier in the material chosen. The in-6 tegrated circuit technology provides approaches to this goal by making 7 it possible to produce material of such a quality that by diffusion or 8 ion implantation a p-n junction can be provided within the diffusion ~, 9 length of the average light pro.duced carrier below the surface, or, in the alternatïve, by a junction contact such.as a Schottky barrier at .. ' 11 the surface. This is illustrated in FIG. 2 by elemcnt 7. The element 7 12 is shown as a p-n ,junction positioned for example,.by diffusion precicely ' 13 at the optimum plane below the surface 8 for maximum photoelectric con-14 version efficiency. A reach through contact 6A is shown providing an -' ohmic connection to the n region 9. This contact is made by depositing an :~
16 n impurity doped melting metal and temperature cycling to alloy through "'~
17 the p region 10 to the n region 9 or by ion implantati.on of a suitable 18 imyurity. ~.
19 , A portion of surface contact 6B labelled 11 is illustrated as having a plurality of fingers the purpose of which is to minimize series ':
21 resistance. A passivating coating 12 covers and encapsulates the surface. :~. . ' 22 Referring next to FIG. 3 the metallization is shown wherein ...
23 conductors 6 connect to the reach through contact 6A and the surface :
24 contact 6B. The conductors 6 go over the isolation 4 and the passiva- ' ':ting layer 12 and go through into the contacts 6~ and 6B. The conductors 26 6 may be laid down by standard vacuum deposition metallization techniques ~ . .
~7 with care being taken to avoid too thin a conductor at points wh~re there 28 is a difference in level.
29 What has been described is a technique'of photoelectrical con- , ~. ...
Y0976-049 ~ 5 ~ '' '' ' 1 version device construction that fabricates planar cell devices by 2 integrated circuit assembly techniques to advantageou61y re601ve the sometimes conflic~ing constraints in photoelectrical conversion array 4 fabrication into a superior structure.
,
9 FIG. 1 is a view of an integrated photoelectric conversion cell array.
11 FIG. 2 is a detailed view showing the vertical aspects of the 12 photoelectrical conversion cell.
13 FIG. 3 is a view showing the contact and isolation of the 14 photoelectrical conversion cell.
DETAILED DESCRIPTION
16 In accordance with the invention the cells are fabricated in 17 situ on a broad area substrate by such techniques, at this state of the 18 art, of masking, photochemical exposure, oxidation and/or nitridation 19 to control the precise horizontal introduction by diffusion or ion im-plantation fcr precise vertical control of conductivity type determining 21 i~purities, of isolation between cells, of positioning and depth of 22 penetration of contacts to the cells and of electrical configuration of 23 the array by vapor deposited metallurgy. The broad area substrate is 24 equipped with a region of insulating material having electrical resist-ivity properties sui~able for electrical isolation and having a thickness 26 dimension small enough to permit efficient thermal dissipation into a 27 broad area heat sink. The technique of the use of insulating epitaxial 2~ material has been shown in the raferenced copending application.
1 Referrin~ to FIG. 1 the broad area substrate 1 is sho~m 2 schematlcally as a single crys~al semlconductor wa~er. The ~"afer 15 a 3 standard e~tensively used semiconductor :intermediate manufacturinz 4 product. Much processing and handling manufacturing capital equipment is available in the art to facilitate building devices using this inter-6 mediate product. Other broad area manufacturing intermediate products 7 such as dendritic webs, ribbons and thin film semiconductor layers on 8 insulating substrates, currently receiving attention in the art, may be 9 employed. The broad area substrate has an active region lA in which the photoelectrical conversion takes place and an insulating region 13 11 which serves to electrically isolate the individual cells from a support-12 ing and heat sinking member 2. While the demarcation between the regi.ons13 1~ and lB is shown as a line, there are instances where a precise defini-14 tion would not take place. For example, we consider the case where a semiconductor material is employed, such as gallium arsenide (GaAs). This 16 material is capable of exhibiting insulating properties by control of the -17 impurity concentration therein, hence there would be a more or less con- ;
18 tinuous variation as the wafer is formed, from the required impurity 19 type and concentration adjacent the photoelectrical conversion region lA
to a dif~erent value in the lnsulating region lB, hence a precise line 21 may not occur. The high resistivity gallium arsenide (Ga~s) is kno~
22 in the art as semi-insulating gallium arsenide (GaAs).
23 The heat sinking member 2 serves both as a physical support 24 and a thermal conductor. Typically it is metallic in nature. The brcad ~ -area substrate 1 may be quite thin, of the order of 0.010 inches for some 26 materials so that physical support is needed. Good thermal conductivity 27 is essential to maintaining temperature control. These requirements are 28 satisfied with a metal which in turn may be equipped with further convec-:29 tion or radiation heat conducting capability such as fins or liquid tubes not shown. There should be reasonable expansion compatability between the Yo976-049 - 3 -',. ' .
- , , ; .
1 heat sink member 2 and the substrate 1, the requirement i9 not as 2 rigorous as it would be were the active region to be closer A low 3 melting metal bolld such as solder is generally satisfactory.
4 The individual device cells are shown schematically as arranged in rows and columns although with the flexibility of the integrated technology no specific conEiguration is required. Further, the array 7 may occupy only one portion of a broad area substrate member 1, the other 8 portions of which may be devoted to devices for other purposes.
9 In accordance with the invention, isolation 4 is provided between the device cells. There are various techniques of isolation prac-11 tised in the integrated semiconductor device technology such as the use 12 of p-n junctions, the introduction of dielectrics, the use of a differen-13 tial in substrate surface level and the use of diffused or implanted 14 impurity species. The isolation provides the ability for flexible inter-connection of wiring patterns.
16 In FIG. 1 the isolation 4 is shown as a channel to the depth 17 of the active region filled with a dielectric, for e~ample an oxide.
18 Where for example, the active region is at or closer to the surface such 19 as through the use of a Schottky barrier for the photoelectrical converter the isolation may not need to penetrate the surface deeper than one or 21 two microns.
22 Tne individual device cells are shown schematically in FIG. ].
23 as connected via electrodes 6 in series paths for voltage addition, the 24 paths in turn being connectable in parallel for current addition.
The details of cell structure may be seen in connection with ~ -26 FIGS. 2 and 3. FIG. 2 shows the contact metallization and cell passivation.
27 In FIG. 3 a cross section of the individual cell is shown illustrating the 2~ active region, the passivation, the surface electrode and the reach through29 connection techniques.
Y0976-049 - 4 - `~
, 1 Referring tO FIG. 2 the phol:oelectrical conversion cell is 2 designed for the efficient uti.li~ation of hole-electron pairs produced 3 by incident light to produce a voltage betweerL the terrni.nals. T~e 4 op~imum is to have the semiconductor junction within the diffusion len~th of the average light produced carrier in the material chosen. The in-6 tegrated circuit technology provides approaches to this goal by making 7 it possible to produce material of such a quality that by diffusion or 8 ion implantation a p-n junction can be provided within the diffusion ~, 9 length of the average light pro.duced carrier below the surface, or, in the alternatïve, by a junction contact such.as a Schottky barrier at .. ' 11 the surface. This is illustrated in FIG. 2 by elemcnt 7. The element 7 12 is shown as a p-n ,junction positioned for example,.by diffusion precicely ' 13 at the optimum plane below the surface 8 for maximum photoelectric con-14 version efficiency. A reach through contact 6A is shown providing an -' ohmic connection to the n region 9. This contact is made by depositing an :~
16 n impurity doped melting metal and temperature cycling to alloy through "'~
17 the p region 10 to the n region 9 or by ion implantati.on of a suitable 18 imyurity. ~.
19 , A portion of surface contact 6B labelled 11 is illustrated as having a plurality of fingers the purpose of which is to minimize series ':
21 resistance. A passivating coating 12 covers and encapsulates the surface. :~. . ' 22 Referring next to FIG. 3 the metallization is shown wherein ...
23 conductors 6 connect to the reach through contact 6A and the surface :
24 contact 6B. The conductors 6 go over the isolation 4 and the passiva- ' ':ting layer 12 and go through into the contacts 6~ and 6B. The conductors 26 6 may be laid down by standard vacuum deposition metallization techniques ~ . .
~7 with care being taken to avoid too thin a conductor at points wh~re there 28 is a difference in level.
29 What has been described is a technique'of photoelectrical con- , ~. ...
Y0976-049 ~ 5 ~ '' '' ' 1 version device construction that fabricates planar cell devices by 2 integrated circuit assembly techniques to advantageou61y re601ve the sometimes conflic~ing constraints in photoelectrical conversion array 4 fabrication into a superior structure.
,
Claims (8)
1. A photoelectric conversion cell array comprising in combina-tion a heat sink member, a broad area device member having first and second major surfaces said first major surface being bonded to said heat sink for good thermal transfer; said broad area device member having a first insulating region adjacent to the bond to said heat sink, isolation means dividing said second major surface of said sub-strate member into a plurality of photoelectrical conversion cells each said cell having a photoelectrical conversion junction with two electrical sides, epitaxial with said insulating region, electrical contact means contacting each said electrical side of each said photo-electrical conversion junction and conductor means operable to connect said cells in series and parallel group relationship.
2. The photoelectrical conversion cell array for Claim 1 wherein said substrate member is gallium arsenide (GaAs).
3. The photoelectric conversion cell array of Claim 2 wherein each said conversion cell is formed of layers of gallium aluminum arsenide (Ga1-xA1xAs) where 0 ? x ? 1.
4. A photoelectric conversion cell array comprising in combination a broad area insulating substrate having a first major face thereof thermally bonded to a heat sink and having a second major face thereof divided by isolation into a plurality of individual photoelectrical conversion cells epitaxial with the insulating substrate and each said electrical conversion cell having a photoelectrical conversion junction with two terminals and conductor means for interconnecting the terminals of said cells to produce series and parallel groups of cells.
5. The photoelectric conversion cell of Claim 4 wherein said substrate is semi-insulating gallium arsenide (GaAs).
6. The photoelectric conversion cell of Claim 5 wherein said junction is a p-n junction.
7. The photoelectric conversion cell of Claim 5 wherein said junction is a Schottky barrier.
8. The photoelectric conversion cell of Claim 5 wherein said photoelectric conversion junction is in the material gallium aluminum arsenide (Ga1-x AlxAs) where 0 ? x ? 1.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US73851476A | 1976-11-03 | 1976-11-03 | |
| US738,514 | 1976-11-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1088190A true CA1088190A (en) | 1980-10-21 |
Family
ID=24968338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA288,213A Expired CA1088190A (en) | 1976-11-03 | 1977-10-05 | Integrated photoelectrical conversion |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5357783A (en) |
| CA (1) | CA1088190A (en) |
| FR (1) | FR2370362A1 (en) |
| IT (1) | IT1113643B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4485264A (en) * | 1982-11-09 | 1984-11-27 | Energy Conversion Devices, Inc. | Isolation layer for photovoltaic device and method of producing same |
| WO2025016637A1 (en) * | 2023-07-14 | 2025-01-23 | Ams-Osram International Gmbh | Thin film optical voltage transformer |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1010476A (en) * | 1962-01-15 | 1965-11-17 | Secr Aviation | Improved photo-electric generators |
| DE1489033A1 (en) * | 1964-11-07 | 1969-05-14 | Ibm Deutschland | Photoelectrically acting semiconductor device |
| US3546542A (en) * | 1967-01-30 | 1970-12-08 | Westinghouse Electric Corp | Integrated high voltage solar cell panel |
-
1977
- 1977-09-14 FR FR7728526A patent/FR2370362A1/en active Granted
- 1977-09-14 JP JP11008477A patent/JPS5357783A/en active Pending
- 1977-10-05 CA CA288,213A patent/CA1088190A/en not_active Expired
- 1977-10-14 IT IT28591/77A patent/IT1113643B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| FR2370362B1 (en) | 1980-04-11 |
| FR2370362A1 (en) | 1978-06-02 |
| JPS5357783A (en) | 1978-05-25 |
| IT1113643B (en) | 1986-01-20 |
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