CA1061253A - Variable print speed control - Google Patents

Abstract

VARIABLE PRINT SPEED CONTROL
ABSTRACT OF THE DISCLOSURE
The carrier for the print head of a printer which is to be used at different operating speeds as a display printer, as a read-only printer, or as a keyboard display printer with asynchronous character rates over a wide range, is operated by a servo motor under the control of a digital/analog converter which continually sums the outputs of an up/down counter which is incremented by in-coming data and decremented by the output of a shift register advanced by the incoming data.

Description

`~

13 Field of the Invention 14The invention relates generally to print head carrier dri~es for variable speed serial printers.
16 Description of the Prior Art 17U. S. Patent No. 3,766,459 which issued on 18October 16, 1973 to Michael D. McIntosh, et al shows the use o~ an up/down counter controlling a machine tool motor through a digital/analog converter.
21U. S. Patent No. 3,793,511 which issued on 22February 19, 1974 to John L. Bala, et al discloses the 23 use o~ an input buffer with an up/down counter continu-24 ously compared with a count proportional to a desired motor velocity to regulate the Yelocity of a motor in 26 a machine tool system.
27U. S. Patent ~o. 3,798,524 which issued on 28March 19, 1974 to Kiyokazu Okamoto discloses the use 29 of a reversi~le counter and a digital/analog converter for controlling a machine tool motor in accordance with 31 input signals and a direction command.

~."~.

~LO~
SUMMARY OF THE INVENTION

2 Generally stated it is an object of the invention

3 to provide an improved type head carrier drive for a printer.
Nbre specifically it is an object of the mYention 6 to provide for operating the print head carrier o a printer at various rates in accordance wit~ the rate of 8 input data to be printed.
g Another object of the invention is to provide for moving the print head carrier in a printer at a rate 11 which is proportional to how far the printer is ~ehind 12 the incoming data.
13 Ye~ another object of the invention is to provide '~
14 for measuring how far a serial printer is behind the incoming data to be printed and using analog means to 16 control the print head carrier drive accordingly.
17 It is also an object o~ the invention to provide 18 for controlling the print head carrier of a serial 19 printer over a wide range of operating rates in accord-ance with the lag of the printer behind the incoming data 21 through the utilization of digital control means.
22 The foregoing and other objects, features and 23 advantages of the invention will be app~rent from the 24 following more particular description o~ pre~erred embodiments of the invention as illustrated in the 26 accompanying drawing.

28 In the drawing;
29 FIG. 1 is a schematic isometric view in part of a printer mechanism with which the invention may be used.
31 FIG. 2 is a schematic circuit diagram of a print 0~5~

1 head carrier control embodying the invention in a preferred form.
FIGS. 3a, 3b and 3c taken together are a schematic circuit diagram of a print head carrier control system embodying the invention in an alternate form.
FIG. 4 is a block diagram showing the arrangement of FIGS 3a, 3b ; and 3c and FIG. 5 is a curve showing the relative displacement for different lag bus values.
i DESCRIPTION OF A PREFERRED EMBODIMENT
As shown in FIG. 1 a print head 10 comprising a plurality of spaced apart and electrically insulated electrodes lOa-g are mounted on ; a carrier 12 for movement along a guide support 14 for printing on a document 16 which is backed up by a conductive platen 18. The electrodes lOa-g are connected by a flexible cable 20 to a source of electrical pulses which selectively energize the electrodes lOa-g to form a matrix pattern characters on the document which may be of the metalized foil type.
The carrier 12 is moved along the guide 14 by means of a toothed belt 22 driven by a servo motor 24 having an emitter disc 26 on the motor ~ -shaft provided with a transducer 28 providing pulses to determine thecarrier position along the print line of the document 16.
The particular control implementation for the motor 24 herein assumes total insensitivity to velocity so that displacements before and after printing are only necessary to assure adequate printing displace-ment, and further that printing is done in one direction with carrier .. ,....... , . . . ,. ...................... ,, . ' . . . . ,: , . . .. . ... .

'` ~

1 return at any desired Yelocity within the system - 2 capability.
3 Basic printing rateq that may be desired are:

4 (1) as a display printer with the rate as fast as the printer is capable, (21 as a read-only printer with the 6 rate slaved to the incoming data rate, pro~ided it is no 7 greater than printer capability, (3) as a keyboard display 8 printer where the data is highly asynchronous from one g character at a time to 15 or 20 characters/sec., short bursts with an average of less than 5 characters/sec. and 11 (4) as a combined form of (21 and (3) as a terminal 12 printer such that any terminal replies would be printed 13 at the line receive rate, as limited by printer maximum 14 capability.
This design incorporates a scheme for automatically 1~ forcing the maximum "TAB/carrier return" velocities of 17 which the drive system is capable by utilizing "blank"
18 charaoters which force the desired velocity profiles but 19 do not cause a printed output.
FIG. 2 is a schematic circuit diagram of the perti-21 nent portions of the system in which AND 31 has input 22 controls which (a~ determine that the incoming data is 23 to be printed and (b) condition the data as to source 24 (keyboard, linej display, etc.l. It is assumed that the size of the buffer 34 and the print rates are such 26 that the buffer 34 will not oYerflow so that no data is 27 lost.
28 AND 32 ha~ input controls Cal that determine ~he 29 incoming data is not to be printed but rather a pre-- 30 determined number of print positions are to be skipped 31 as guickly as possible (b) that provide a source of 1 "blank" characters at a rate far exceeding print rate 2 capability and ~c~ that reduce the receipt of these - 3 high-rate "blanks" if the buffer should become full.
4 OR 33 combines these exclusive data sources and presents this data to the FIFO 34 (a FIRST IN/FIRST OUT data buffer) 6 and increments the up/down counter 35 once for each input 7 characker. The FIFO 34 ha~ an output FULL 36 which thru 8 inverter 37 prevents receipt of more blanks than it can 9 handle, an output EMPTY 51 which assures that the up/
down counter 35 maintains long term synchronism with the -~ 11 correct data depth count in the FIFO 34 and the actual 12 DATA OUT 39 that is to be printed. FIFO 34 input data 13 rates are controlled by ~NDS 31 and 32 while D~TA OUT 39 14 is withdrawn at the particular rate the printer happens to be running at any given time. The DATA OUT 39 may be 16 fed to suitable decode means not shown which provide for 17 selective energization of the electrodes 10a through 10g 18 for forming characters as the print head 10 moves along I9 the print line. Each time a character is extracted from FIFO 34, it decrements the up/down counter 35 so that the 21 counter 35 is a measure of the depth (number of charac-22 ters) of data in the FIFO 34. This amounts to a determi-23 nation of how far the printer is behind the incoming data.
24 The maximum binary sum o~ the up/down counter 35 positions must equal or exceed (x3 where (x) is the length of ~26 FIFO 34 or a very high data rate would cause loss of 27 print velocity control.
28 Outputs from the up/do~n counter 35 are continually 29 summed by a D~A (digital-analog) converter 38 except that, as required by the design, counter values in excess 31 of a particular value c,ause no further increase in the ' . . . . . . .

5~
1 analog output of the converter 38 but rather keep it at 2 the maximum intended ~alue via OR 50. Amplifier 39 3 operationally follows the converter 38 outpu~ at a gain 4 determined by the resistors 40 and 41. Amplifier 39 draws power from the (+) power supply 42 and deliYers it

6 to the servo motor 24 through current switches 44 and 45

7 if the carrier is to run to the right or through current

8 switches 46 and 47 if the carrier is to return to the

9 left. Emitter 26 and transducer 28 are utilized to sense printing position and determine printing synchronism 11 within a position for sense velocity. The cixcle 49 12 represents the load of the carrier 12 through the drive 13 system. r 14 This print velocity control prints behind the reception of data by a number of characters that is pro-16 portional to the data rate up to the maximum print capa-17 bility without additional control complexity.
18 The permissible output levels from the converter 38 19 are such that one character in the buffer 34 will apply a small voltage to the servo motor 24 and that character 21 will print very slowly. This would be typical o~ keyboard 22 input data printing. Since the buffer is nearly empty, 23 there is no need to hurry the printing process which 24 would only cause additional (a) power dissipation in the system, ~b) strain and wear on the mechanical drive system, 26 (c) audible noise and (d~ reduction of motor brush life 27 due to higher currents.
28 Another preferred em~odiment of the ~ariable print 29 speed control system utili~es digital pulse width control of the servo motor 24. The frequency of drive pulses 31 is fixed at a rate much higher than the inverse of the 2~;~
1 system mechanical time constant so th~t the velocity does 2 not change appreciably during each ~ulse time. Velocity 3 is checked once each pulse interval and the following 4 motor drive pulse width i~ incrementally changed to keep the velocity at approxLmately the desired value.
6 The circuitry of FIG. 3a extracts from FIG. 2 ~the - 7 analog control~ the digital controls and adds detail to 8 show data control for manually caused, as well as powered, g motion of the print carrier 12. AND 31 gates character bus data to the FIFO buffer 34 as before, while OR 115 11 creates a character received pulse 102 fxom the FIFO
12 input bus and, through OR 33 a FIFO read-in cycle is 13 taken so the character is stored in sequence in the r 14 asynchronous buffer. A non-print instruction (space or 1~ tab right~ or a manual move left 114 through OR 113 and 16 AND 32 and OR 33 will cause a blank character to read-in 17 the buffer 34 provided full signal 36 is not active so 18 that the inverter 37 is OFF. If a non~print instruction 19 places a blank character in the buffer 34, it will, through AND 118 and OR 117, increment the data position counter 21 103. I,ikewise a character received pulse-102 will 22 ~increment the counter through OR 117. The counter is 23 decremented by non-print left blanks 104 which occur once 24 each column on carrier return or backspace operations.
FIFO read-out 116 occurs once for each column move to the 26 right and it causes the buffer 34 to yate out the next 27 character to be printed 39.
28 In FIG. 3b, the servo motor 24 rotates the two~track 29 quadrature optical transducer 26 and the load 49.
Transducer 26 si~nals are amplified at 88 and detected 31 at 89 ~here they become quadrature related feedback :- . .

,t~ 3 - 1 p~llses 90.
2 In FIG.3b the quadrature phase sense 94 uses the 3 quadrature feedback pulses 90 to determine the actual - 4 direction of carrier motion right or left. The pulses t 90 are delayed by delay 95 and gated through AND 96 or 6 AND 97 to cause the one column counter 98 to increment ; 7 if right motion or decrement if left motion. The counter 8 98 modulus equals the number of quadrature pulses 90 per g print column. When the counter 98 overflows, a one-column right siynal 99 is generated and a column counter 11 101 incremented; when the counter 98 underflows, a one 12 column left signal 100 is generated and counter 101 is 13 decremented. The column counter 101 is used in conjunction 14 with the data position counter 103 in FIG. 3a and both are shown only to indicate uses of the signals used in the 16 velocity control logic. `
17 The logic in FIG. 3c keeps track of how far the 18 printer motion is behind incoming information for each 19 direction and performs the velocity measurement function.
When a character received pulse 102 increments right lag 21 counter 120 through OR 119, the right lag = 0 signal 76 22 goes OFY and in FIG. 3a inverter 80 is turned OFF so 23 that the run control trigger 78 will be set through OR 81 24 and AND 126. Single-shot 83 is set through OR 82.
Left lag = 0, 77 is ON so direction control trigger 85 is 26 set through AND 84 and direction right signal 57 is pro-27 vided. In FIG. 3b clock 53 is continuously incrementing ~8 drive period counter 52 so that the next time counter 52 29 goes to zero, motor drive trigger 56 will be set through AND 55 with run control 54 ON. Motor drivers 44 and 45 31 will turn ON immediately through AND 58 the motor 24 oEN974017 -8-j ~ :

` ~

1 will turn ON and move the printer carrier 12 to the right.
2 In FIG. 3c when right lag counter 120 was incremented to 3 one its bus output will pass through bus AND 121 as soon 4 as run control 54 and direction right 57 are active and that bus signal will applear on the common lag bus through 6 bus OR 122. The counter 120 increment signal through OR
7 123 and the direction right signal pass through AND 124 8 and OR 125 to provide a lag change signal 65. The common 9 lag bus low-order bits 1 through 4 become lag bus 66 so that when counter 52 next goes to zero, they will be gated 11 through bus AND 105 at zero TB time 93 from AND 92 and 12 pre-set velocity measure counter 106 to the value of 13 lag bus 66 which is in this case a one from the right 14 lag counter 120.
In FIG. 3b when lag change 65 and lag bus 66 are on, 16 duty cycle counter 61 will preset to the lag bus value 17 (a one in this case) through bus AND 67. The first time 18 counter 52 goes to zero it not only sets trigger 56 but 19 at time TA through AND 91 it will test the VMC = 0 (68) line to see if the measured velocity is higher or lower 21 than it should be. Initially VMC = 0 (68) is OFF at this 22 time because counter 106 was just preset to one so inverter 23 69 is OFF and counter 61 will be incremented by 1 through 24 AND 70; counter 61 now is at two and counter 52 is at zero.
The development of signals clock 53, TA and TB in 26 FIG. 3b is not shown because it would be evident to those 27 skilled in the art. Typical values and conditions for 28 those signals would be as follows: a 2 mhz oscillator 29 would drlve an 8-bit binary counter and clock 53 is the last stage of that counter so that drive period counter 31 52 would advance once each 256 microseconds and have a EN974017 _9_ : . : ,. ~

1 period o~ 4.096 milliseconds. Pulses TA and TB would be 2 one microsecond wide with three microseconds between them 3 (TA followed by TB~; further, they occur only once each 4 period o~ counter 52 ~when counter 52 has ~-ust become zero).
6 Status at this time is: motor drive trigger 56 is ON
7 and the drive motor 24 is powered to the right. As time 8 progresses, clock 53 advances counter 52 and when its 9 value e~uals the value in duty cycle counter 61 as detected by comparator 62, the motor drive trigger 56 will be reset 11 through AND 64; since the lag bus value is one, the 12 Lag < 16 line 63 i~ ON. Motor drivers 44 and 45 will be 13 turned OF~ so that the servo motors 24 and the load will r 14 coast until the trigger 56 is turned on again the next time counter 52 goes to zero and run control 54 is ON.
16 When counter 52 and pulse TA switch gate in AND 91 17 each time, the zero TA pulse tests the VMC - 0 line 68.
18 If the line is not zero, the measured average velocity 19 over the last measurement period was slower than desired so, with inverter 69 OFF, coincidence at AND 70 will in-21 crement counter 61 and the next drive pulse width to the 22 motor will be longer because the counter 52 must advance 23 to a higher value to match counter 61 before trigger 56 24 will termi~ate the motor pulse; the motor 24 will speed up slightly~ Conversely, if VMC = 0 (68~ is ON, the 26 measured average velocity over the last period was faster 27 than desired so that inverter 69 will be ON and block AND
28 70 so that the zero TA signal will switch with VMC = 0 ~68) 29 ON through AND 71 to decrement counter 61; the motor pulse will be more narrow ne~t time and the motor will 31 slow down slightly. It can be appreciated that it is .. .. . ~ - . . ~ , . . .

1 rather easy to alter this circuit such that a small band 2 of velocities is categorized as neither fast nor slow and 3 the duty cycle counter 61 would not change each zero TA
4 test time; such change would not depart from the claimed velocity control concept.
6 From the relationship of (velocity = displacement 7 - time), different controlled velocities are obtained 8 by measuring displacement over a constant time interval 9 (the time between trailing and leading edges of pulse zero TA). In FIG. 3c, displacement feedback pulses 90 11 increment the velocity slope counter 110; each counter 12 carry pulse then decrements velocity measure counter 106. - ;~
13 The distance that must be travelled each test period is 14 then given by the displacement per feedback pulse times the number of feedback pulses per test period required 16 to decrement counter 106 to zero; that number is the 17 product of the counter 110 counter divide factor (1, 2 or 4) 18 and the lag bus 66 value at time zero TB 93. FIG. 5 is a graph of the relative displacement, thus velocity for any particular lag bus 66 value. Curve slope A is con-21 trolled by decode lag less than 4 (107), slope B is con-22 trolled by decode lag 4 through 7 -108, slope C is con- ~
23 trolled by decode lag 8 through 15 and curve D is the ` r 29 uncontrolled maximum open-loop response of the system when the lag bus value exceeds 15. When the lag bus value 26 exceeds 15 the entire velocity measurement and correction ~`
27 logic contains erroneous values which are not relevant 28 because decode lag equal or greater than 16 ~111) will be 29 ON, inverter 112 will be ON and the lag less than 16 line 63 will be OPF so that the reset to motor drive trigger 56 ,`
31 through AND 64 is prevented; the motor duty cycle then ., ~ -;

.
'- ~
.. . .

1 becomes 100% giving the velocity response curve D of FIG. S.
The previous discussion is based on a required motion to the right from a stopped position. In FIG. 3a when right lag = O (76) goes ON
(indicating all required right motion has taken place), the run control trigger 78 will reset through AND 79 if the left lag = O (77) is also zero (no left motion is required either). When right lag - O goes ON, single shot 83 is fired through OR 82. If the left lag = O (77) is ON
inverter 87 will block AND 86 so that direction control trigger 85 will not change state. If left lag = O (77) is OFF, AND's 79 and 84 are blocked ;
so run control 78 will stay ON while direction control trigger 85 will reset to direction left 59 through AND 86. In FIG. 3b with direction left 59 ON, the motor drive 56 will turn ON AND 60 and motor drivers 46 and 47 so that the power will be supplied for counterclockwise or left motor . :
motion if still going right, dynamic braking occurs. The converse is ~ :
true with the opposite set of conditions.
Since this particular embodiment is for a unidirectional printer, FIG. 3c shows the logic that controls the print carrier return to the left margin. ~hen a non-print left command is received and the DPC Not O (127) is ON, blank characters are gated through AND 129 at a very high rate relative to mechanical motion. The signal non-print left blanks 104 simultaneously increments the left 1ag counter 130 through OR 131 and decrements the data position counter 103 until counter 103 value matches the left margin value appearing on the margin/tab bus as determined by comparator 128 output DPC unequal 127 going OFF. The end of this signal will terminate the . ' `

, ,1 ~

~3 ..... . . .. .. . .. - - ~ . --1 non-print left instruction and block AND 129.
2 When any right motioll is completed, direction right 3 57 goes OFF and direction left 59 goes ON. AND 133 now 4 gates the left lag countex 130 onto the lag buR and direc-: 5 tion test 132 provides a lag change signal 65 through OR
i6 125. Left motion is controlled identically to right motion 7 although decodes 127, 128, 129 and 111 could be gated for 8 right motion and'have a companion set with different 9 velocity control profile for left motion if desired.
Any time the left lag counter 130 changes while 11 direction left 59 is ON, OR 134 output is gated through 12 AND 135 and OR 125 to give a lag change signal 65.
13 To keep track of carrier position when the motor is '' 14 not being driven, motion to the left of the stopped posi~ion is saved in the right lag counter 120. If the 16 left lag counter 130 is at zero and one column lef* 100 17 occurs, AND 136 increments counter 120 through.OR 119;
18 it also provides a manual move left signal 114 that 19 forces a blank character into FIFO bu~fer 34 through OR 113, AND 32 and OR 33 because the character data bus 21 out of AND 31 is OFF. As the carrier moves right (but .22 still lef.t of the stopped position), counter. 120 is not 23 zero, inverter 137 is OFF so one column right s,ignal 9g 24 gates through AND 138 where it decrements the counter 120 and removes the blank put in FIFO buffer 34 by giving 26 a FIFO read-out 1160 If the carrier is then pushed to 27 the right through the stopped position, the counter 120 28 goes to zero and its input AND's 136 and'138 become 29 degated. As right motion continues, one column right 99 incremen~s the left lag counter 130 through AND 139 and 31 OR 131. If left motion to the right of the stopped 1 position occurs, one column left decrements the left lag 2 counter 130 through AND 140 because counter 130 is not 3 zero and inverter 141 if OFF.
4 It can be apprec:iated that this velocity control S system can have a var:iety of changes that fall within 6 the scope of this disclosure. These are (a) there can 7 be any number of feedback pulses per test period as 8 opposed to the one illustrated, (b) there can be an 9 arbitrary number of velocity slope transfer functions which can ~hange slope at any desired lag value, (c) 11 there can be any desired pulse width resolution within ' 12 the drive period counter interval, (d) that pulse width ; ~ 13 resolution bears no needul relationship to the lag 14 function even though they show a 1:1 ratio in this example and (e) this design can control a bidirectional 16 printer by having two FIFO buffers and making the appro-17 priate minor logic control changes.
18 While the invention has been particularly shown and 19 described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that - 21 various changes in form and details may be made therein 22 without departing from the spirit and scope of the - ?3 invention, 24 What is claimed is: .

Claims (11)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. In a control system for a printer having a carrier with a print head moveable along the print line of a document to print thereon in response to incoming print data, drive means including a motor operable to move said carrier along said print line, counter means connected to said drive means to vary the speed of said drive means in accordance with the lag of the printer behind the print data input, buffer means for receiving data to be printed and having means to read data out and decrement said counter means, circuit means supplying print data connected to said buffer means and to said counter means to increment said counter means.

2. The invention as defined in claim 1 characterized by said drive means including a digital/analog converter.

3. The invention as defined in claim 2 characterized by said counter means comprising a reversible up/down counter.

4. The invention as defined in claim 3 characterized by said buffer means comprising a shift register.

5. The invention as defined in claim 4 characterized by said drive means including a differential amplifier connected to said motor and controlled by said digital/
analog converter.

6. The invention as defined in claim 1 characterized by said drive means including a clock pulse source for operating said motor through said drive means.

7. The invention as defined in claim 6 characterized by said drive means including control means to control the connection of said clock pulse source to said motor for different predetermined intervals of time.

8. The invention as defined in claim 7 characterized by said control means including a motor drive trigger connecting said clock pulse source to said drive means.

9. The invention as defined in claim 8 characterized by said control means including gate means connecting said clock pulse source to said motor drive trigger, said gate means being connected to said counter means to activate said motor drive trigger for different numbers of clock pulses in accordance with the lag of the printer behind the print data input.

10. The invention as defined in claim 9 characterized by said control means including a drive period counter connected to count pulses from said clock pulse source, and compare means connected to both said counter means and said drive period counter to control the operating time of said motor drive trigger.

11. The invention as defined in claim 1 character-ized by said circuit means including means to supply blank characters to said buffer means to advance said print head with the printing.