CA1056068A

CA1056068A - Semiconductor device

Info

Publication number: CA1056068A
Application number: CA237,952A
Authority: CA
Inventors: Hajime Yagi; Tadaharu Tsuyuki
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 1974-10-31
Filing date: 1975-10-20
Publication date: 1979-06-05
Also published as: DE2547303A1; IT1044307B; GB1514578A; JPS5724659B2; FR2290039A1; FR2290039B3; NL7512681A; JPS5151286A

Abstract

ABSTRACT OF THE DISCLOSURE

A semiconductor device having a high emitter-grounded current gain which includes an emitter region with the minority carrier diffusion length greater than its width and an additional region adjacent to the emitter region with the minority carrier diffusion length of this additional region greater than its width. The surface recombina-tion velocity of the additional region is small. The minority carrier current injected from the additional region into the emitter balances that injected from the base into the emitter.

Description

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FIELD OF THE lN~ENTlON

It has been common practice in fabricating conventional bipolar transistors to employ double diffusion technique to form an e~utter-base junction in which the dcping concentration of the emitter is made higher than the base. As this difference becomes larger, the emitter efficiency becomes greater and is more nearly unity.
However, heavy doping increases lattice defects and dislocations in the semiconductor substrate. As a result of the heavy doping, the diffusion length of the minority carriers is decreased in the doped area.
Decreasing the doping in prior art forms of transistors has been accompanied by a decrease in gain.
Stieltjes et al United States Patent No. 2,822,310 issued February 4, 1958 to North American Philips Corp. discloses an emitter of high resistivity in which the diffusion length is greater than the width and a floating region of opposite conductivity type forms a P-N junction with the emitter. ~s described in Stielties, the minority carriers in either o~ the emitter and the floating region are below the equilibrium concentration, and both minority carrier currents across the P-N junctions compensate each other lt is indicated in Stieltjes that the width of the floating region is larger than the diffusion length therein, and that hence the minority carrier current in the ernitter can be minimum by minimizing the gradient of the minority carrier concentration in the floating region. It is also described that the P-N junction must not be forwardly biased, otherwise the minority carrier current in either o~ them is increased.
An article in Solid State Electronics, Vot. 13 (1970), p.
102S discloses a semiconductor transistor having an additional ~egion .' ~
'~ -2-l~S~8 in the emitter of the opposite conductivity type from the emitter ~nd within the diffusion length of minority carriers in the emitter, The input signal is app~ied between the emilter and the additional region while the base is floating.

BRIEF SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semi-conductor device having greatly improved characteristics, including a ~, very substantial increase in the gain factor.
Ie is a still further object of the present invention to pro- ~'" ' vide a novel semiconductor device having improved low noise character-istics.
It is a,still further ob~ect of the present invention to pro-vide a novel semiconductor device having a high breakdown voltage and which prevents thermal run away.
~ nother and further object of the present invention is to provide a novel semiconductor device which m'ay be employed as part ~ ' of an integrated circuit along with conventional transistors including complemèntary transistors.
This invention relates to a semiconductor device, such for example, as a bipolar transistor or a thyristor, and particularly to a ~' '' .

10~ 8 device having an emitter region with a minority carrier diffusion length Lp greater than its width and an additional region contig-uous with the emitter region with the minority carrier diffusion length L'n greater than the width of the additional region. The surface recombination velocity of the additional region is smaller than Dn'/Ln'. Surface recombination is usually defined in reference to a recombination velocity. This is the effective velocity at which all the minority carriers appear to be swept into the surface, where they are lost in surface trapping levels.
The minority carrier diffusion length in the emitter of a conventional transistor is believed to be on the order of 1 to 2 microns. The present invention provides a semiconductor device having a minority carrier diffusion length of 50 to 100 microns. The current amplification factor of a conventional transistor is roughly 500, while that of the present invention is 10000 or more.
It is an object of the present invention to provide a novel semiconductor device having a high hFE (current gain factor) and a low noise characteristic.
In accordance with the foregoing, the invention more specifically provides a semiconductor device comprising a first semiconductor region of a first conductivity type; a second semiconductor region of a ~econd conductivity type forming a first P-N junction with said first region; a third semicon-ductor region of said first CQnductivity type forming a second P-N junction with said second region which is spaced from said ~irst P-~ junction by said second region; a fourth semiconductor region of said second conductivity type forming a third P-N
junction with said first region which is spaced from said first P-N junction by said first region; and means for biasing said first junction forwardly and transporting the majority carriers in said first region to said third region; the current of minor-~ _4_ i~S~i~

ity carriers in said first region injected from said third junction being substantially equal to that from said first junction; and the distance between said first and third junc-tions being smaller than the diffusion length of minority carriers in said first region.
There is also provided, a semiconductor device com-prising a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type forming a first P-N junction with said first region; a third semiconductor region of said first conductivity type forming a second P-N junction with said second region which is spaced from said first P-N junction by said second region;
voltage applying means for transporting majority carriers in said first region to said third region; the width of said first region being smaller than the diffusion length of minority carriers therein: and a Schottky barrier interfaced with said first region.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a diagrammatic fragmentary sectional view of an NPN transistor embodying the novel features and character-istics of the present invention.
Figure 2 shows the minority carrier concentration in the emitter region and in the additional region of the device shown in Figure l;

-4a-~OS~0~8 Figure 3 is a fragmentary sectional view of an integrated circuit chip having an NPN transistor embodying the present invention and additionally a PNP transistor of a conventional design, thus pro~iding a complementary pair of transistors in the integrated circuit chip;

Figures 4, 5 and 6 are fragmentary sectional views similar to ~igure 1, but showing other embodiments of the present invention; and ~ igure 7 diagrammatically illustrates how the biasing means and the input signal may be applied to the structure of ~igure 1.

DESCRIPTION OF THE PREFE~RRED EMBODIMENTS

A preferred embodiment of the present invention, as embodied in an NPN transistor, is shown in Figure 1. As shown, a substrate 1 heavily doped with N-type impurities or more specifically, a ~ubstrate 1 may be formed of silicon heavily doped with antimony.
The doping is preferably 4 x 1018 atoms/cm 3. This gives a resisti-vity of approximately 0.01 ohm-cm. lt has been found that this doping may vary between 0.008 and 0.012 ohm-cm. The thickness of the substrate i9 preferably approximately 250 rnicrons.
An N-type silicon epitaxial layer 2 is formed on the ~ubstrate 1 to be used as a collector together with the N+ substrate 1.
This epitaxial layer 2 hereinafter referred to as the third region, is lightly doped with antimony sufficient to provide a doping concentration o~ 7 x 1014 atoms/cm 3. The resistivity is approximately 8 to 10 ohm-cm. The epitaxial layer is preferably appro~imately 20 microns thick.

0~8 A P-type base region 3, hereinafter referred to as the second region, is then diffused or ion-implanted on the N- layer 2 to provide an active base for the transistor. The doping may be boron in sufficient quantity to ~ve a doping concentration of 1 x 1016 atoms/
cm 3 An n-type silicon epitaxial layer 4, hereinafter referred to as the first re~ion, is then formed on said N- layer 2 to provide an emitter. The layer 4 is lightly doped with antimony, the doping concentration being approximately 5.5 x 1015 atOms/cm 3. The resistivity is approximately 1 ohm-cm. The thickness of the layer 4 is approximately 2 to 5 microns.
An N+ -type diffused layer 5, hereinafter referred to as the fifth region, is formed in the N- layer 4 to provide an emitter contact area. This layer 5 is doped with phosphor with a surface impurity concentration of 5 x 102 atoms/cm 3, and has a depth of about 1. 0 micron.
~ heavily doped diffused region 6 is provided surrounding the collector region and this region 6 penetrates into the N- collector layer 2. The impurity i9 phosphor and the doping is appro~imately 3 x 1019 atoms/cm 3 as a surface concentration.
A P-type diffused region 7 penetrates through the N-emitter layer 4 into the P- ba~e layer 3 which limits and surrounds the emitter 4. The dopant is boron and has a surface concentration of 7 x 1019 atoms/cm 3. A P-type diffused region 8 is formed in the region 7 to provide a base contact area, the diffused region 8 being heavily doped with boron with a surface concentration of approximately S x 1018 a~oms/cm 3, and the penetration of the region 8 is approxi-mately 1. 8 microns.
A silicon dioxide layer 206 for passivation covers the upper sur~ace of the device.
A collector electrode 9, formed of alùminum, is provided on the N+ substrate 1. A base electrode 10 of aluminum is formed on the base contact area 8. An emitter electrode 11 of aluminum is formed on the emitter contact area 5. A P-type region 200, sometimes hereinafter referred to as the additional region and somelimes as the ~loating region, is diffused in the N- emitter 4 to provide a PN
junction between it and the emitter 4. The region 200 is doped with boron and is formed simultaneously with the forming of the base contact area 8. The doping concentration is 5 x 1018 atoms/cm 3, and the depth of the layer 200 is approximately 1. 8 rn~crons.
Prom the above, it will be apparent that the N- layer 2 and the P region 3 form a collector-base junction 12. The P re~on 3 and the N- layer 4 form an em~tter-base junction 13 and the N-layer 4 and the P additional region 200, as explained ahove, form an additional PN junction 14. The distance between the emitter-base junction 13 and the additional PN junction 14 is preferably 2 to 5 microns, An emitter configuration formed in a lightly doped epitaxial layer is disclosed in Schlegel United State~ Patent No.
3,591,430 issued July 6, 1971 to Philco-Ford corp. see also French Patent No. 2,130,399 issued November 3, 1972 to Philips Corp.
~igure 3 illustrates a second embodiment of the present .
invention, where the NPN transistor described in Figure 1 is formed .. ~

,~ . - ' ~6~

in an integrated circuit with other semiconductor elements such, for e~ample, as a PNP transistor. The integrated circuit, as shown, includes tWO different types of transistors such, for example, as com-plementary transistors, namely, an NPN transistor 21 and a PNP tran-sistor 22. These two transistors are formed in a~ substrate 20 o~
P-type silicon. As hereinbefore explained in connection with Figure 1, the NPN transistor 21 includes a heavily doped collector region 1, a lightly doped collector region 2, a lightly doped base Tegion 3, a lightly doped emitter 4, a heavily doped emitter contact area 5, a collector lead area 6, a collector contact area 15, a base lead area 7, a base contact area 8, an additional area 200~ a collector electrode 9, a ba~e electrode 10, and an emitter electrode 11.
The PNP transistor 22 has a P-type collector 33, an N-type base 34, a P-type emitter 38, a P-type collector lead 37, a P-type c~llector contact area 48, an N-type base contact area 35, a collector electrode 39, a base electrode 40, and an emitter electrode 41.
The transistors 21 and 22 are electrically isolated by PN
junctions. A P-type isolation region 50 is connected to the P substrate 20 and surrounds both the NPN and the PNP transistors 21 and 22.
Three N-type reglons 31, 32 and 36 form a cup-shaped isolation area surrounding only the PNP transistor 22. In this integrated circuit, a plurality of couples or trios are formed simultaneously, for example, the N~ regions 1 and 31 are formed by selective diffusion into the P substrate 20. The N- regions 2 and 32 are formed by N-type epitaxial growth. The P- region 3 of the NPN transistor 21 ., - . -.. . . . . . , . . . . , ~ .

~(~5tiOti~

and the P- region 33 of the PNP transistor 22 are formed by either an epitaxial growth or by selective diffusion. The N- region 4 of the NPN transistor 21 and the N- region 34 of the PNP transistor 22 are formed by an epitaxial growth. The N+ regions 6 and 36 are formed by an N-type diffusion. The P regions 7 and 37 are formed by a P-type diffusion. The P~ region 8 of the NPN transistor 21, the additional region 200 of the transistor 21, and the P+ region 38 of the PNP transistor 22 are formed by P-type diffusion. The N+ regions 5, 15 and 35 are formed by diffusion.
Figure 4 shows a third embodiment of the invention wherein an additional area 201 is connected to the base-lead area 7 and the base 3. The base electrode 10 can be located on the additionai area 201 but not widely.
~ igure 5 shows a fourth embodiment of this invention wherein an MIS (metal-insulator-semiconductor) structure is employed on the surface of the lightly doped emitter 4. An aluminum gate electrode 42 and a silicon dioxide layer 41 together with the emitter 4 form the MIS structure. By applying a predetermined voltage to the gate electrode 42, a barrier 202 occur~ beneath the insulating layer 41. This is a reverse layer, a depletion layer, or an accumulation layer.
Figure 6 illustrates a fifth embodiment of the present invention wherein a Schottky barrier layer 203 is created on a surface of the lightly doped emitter 4. A suitable metal 51, such for example, as platinum is deposited on the N- emitter 4 to form the Schottky barrier.

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Figure 2 is a visual showing of the minority carrier concentration in the emitter ~f the device shown in Figure 1. The tOp portion of the figure loca~es the emitter 4 and the P region 200.
The graph shows the injected minority carrier concentration in the emitter and the P region 200 respectively. The components caused by injected holes in the emitter 4 from the emitter-base junction 13 and the additional junction 14 are shown by the gradient lines lOl and 102, respectively. The component caused by injected electrons in the P region 200 from the additional junction 14 is shown by the gradient line 103. The composite gradient line 104 is substantially constant when the gradient line 103 is substantially level. This will be understood by a consideration of the equation Ip2 = Ipl - Inl where Ip2 is the hole reinjection from region 200 to emitter 4, where Ipl is the hole injection from the emitter 4 to the additional region 200, and Inl is electron injection from emitter 4 to the additional region 200.
Since Inl ls very small it can be neglected. Hence Ip2 = Ipl, and this makes the curve 104 substantially flat. To explain this in a morc detailed fashion, it will be noted that the minority carriers (the holes) in~ected through the emitter-base iunction 13 reach the additional ~unction 14 and enter into the additional region 200. The additional junction 14 is forwardly biased and the P region 200 also injects holes into the N-type emitter 4 and these holes pass through the emitter and reach the emitter-base junction 13 because the width of the emitter (W~) is smaller than the diffusion length in the N-1 ()--~OS~0~8 emitter 4. The holes injected from the additional junction 14 decreasein number from junction 14 to junction 13. Holes injected from the base-emltter junction 13 decrease in number from junction 13 to junction 14. The hole concentration across the emitter is thus the sum of the minority carrier concentration gradien~ lines 101 and 102.
When the hole injection from the P region 200 is large enough, the sum of the gradient lines 101 and 102 will result in a substantially constant carrier concentration across the emitter, as shown by line 104 in the graph of ~igure 2, and this decreases the hole current from the base 3 to the emitter 4.
The structure of Figure 1, above described, provides a high hFE characteristic and l~w noise. In explanation of why this result is obtained, it will be noted that the emitter-grounded current gain (hFE) is one of the important parameters of the transistor This is generally given as hFE I - q' (1) where, O~ is a base-gra~nded current-gain. The current gain l is given a9 *.,~ (2~

where o~ * is a collector multiplication ratio,,~ is a base-transport factor, and y is a emitter efficiency.
In an NPN transistor, for example, the emitter efficiency Y is givenaF

Y = ~ = 1 + Jp~Jn (3~

~()S6~1t;8 where Jn is the electron current density resulting from the electrons which are injected through the emitter-base junction from the emitter to the base, and Jp is a hole current density of the holes which are injected through the same junction from the base to emitter reversely.

The electron current density Jn is given as qv Jn = q DLn np (ekT-l~ (4) qv Jp q Dp Pn (ekT- 1) (5) where Ln is the electron diffusion length in the P-type base, Lp is the hole diffusion length in the N-type emitter, Dn is the electron diffusion constant, Dp is the hole diffusion constant, np ls the minority electron concentration in P-type base in a state of equilibrium, Pn is the minority hole concentration in N-type emitter in a state o~ equilibrium, is the voltage applied to the emitter-base junction, T is the temperature, q is the charge on the electron, and k is Boltzmann's constant.
The carrier diffusion constants Dn and Dp are functions of a carrier mobility and the temperature and they can be substantially constant.
ln the present invention, the minority carrier diffusion Iength Ln' in the additional region is selected larger than its width Wp and the surface recombination velocity of the additional region is selected smaller than Dn'/Ln'. Dn' is the electron diffusion constant in the additional region. Ln' depends on the impurity concentration and can be over 10 microns. ln this case, the minority carrier current injected in the additional region is smaller than the case where .

;... . ~ . ; .-; ~ - - .. - . - ~ - . , -~S~0~8 Wp is larger than Ln', since it is multiplied by the term Wp/Ln'.
As the loss in the additional region is very small ~he holes current in the emitter injected ~rom the additional region is substantially equal to that injected from the emitter-base junction. The minority carrier concentration in the emitter is much abo~7e equilib~ium.
In the present invention, Jp is amended as q Dp Pn WE (ekT 1) (6) Thus, the decrease of 3p makes the value Y close to unity according to equation (3), the value I high by equation (2), and the value hpE high by equation (1).
The low noise characteristics may be explained as follows.
The lattice defect or the dislocation is largely decreased because the emitter~base junction 13 is formed by the lightly doped emitter 4 and also lightly doped base 3. The impurity concentration of the lightly doped emitter 4 should be limited by consideration of the noise characteristics, the life time ~p and the minority carrier diffusion length Lp, to a value where the impurity concentration is approximately less than 1018 atoms/cm 3.
Another factor causing a la~ noise level is that the emltter current flows almost in a vertical direction in the lightly doped emitter 4 and the lightly doped base 3.
In this invention, an L-H junction is formed by the lightly doped region 4 and the heavily doped region 5. The distance between the L-H junction and the emitter-base junction is smaller than the minority carrier ~iffusion length Lp. The difference in impurity 1~)S~8 concentrations between the fffth and first regions is selected tO provide an energy barrier higher than the energy level of the injected minority carriers injected into said first region from said second region and reaching the I,-H junction. A built-in-field thus is formed adjacent said L-H junction and acts in such a direction that the hole current from the emitter-base junction 13 is reflected toward the junction 13.
When the built-in-field is large enough, the diffusion current of holes `
towards the layer S is effectively decreased.
Figure 7 of the drawings diagrammatically illustrates one way in which the transistor of Figure 1 may be biased and have the input signal applied. The configuration shown is an emitter grounded configuration. It is, of course, also possible to have a base grounded conSguration.
While the invention is exemplified in Figure 1 as being an NPN transistor, it will, of course, be understood that it may be a PNP
tranqistor with comparable structure and characteristics. It will further be understood that the invention may be embodied as a semi-conductor thyristor of the NPNP type.

Claims

WE CLAIM AS OUR INVENTION:

1. A semiconductor device comprising:
a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type forming a first P-N junction with said first region;
a third semiconductor region of said first conductivity type forming a second P-N junction with said second region which is spaced from said first P-N junction by said second region;
a fourth semiconductor region of said second conductivity type forming a third P-N junction with said first region which is spaced from said first P-N
junction by said first region; and means for biasing said first junction forwardly and transporting the majority carriers in said first region to said third region;
the current of minority carriers in said first region injected from said third junction being substantially equal to that from said first junction; and the distance between said first and third junctions being smaller than the diffusion length of minority carriers in said first region.

2. A semiconductor device comprising:
a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type interfaced with said first region;
a third semiconductor region of a first conductivity type interfaced with said second region, opposite said first region;
a fourth semiconductor region of a second conductivity type interfaced with said first region, opposite said second region;
voltage applying means between said first and second regions for transporting the majority carriers in said first region to said third region;
the minority carrier diffusion length in said first region being larger than the width thereof; and the minority carrier diffusion length in said fourth region being larger than the width thereof.

3. A semiconductor device comprising:
a semiconductor substrate having a major face;
a first semiconductor region of a first conductivity type formed in said major face of said substrate and interfaced with said substrate;
a second semiconductor region of a second conductivity type interfaced with said first region, at least a portion of said second region being below said major face;
a third semiconductor region of a first conductivity type interfaced with said second region, and on the opposite side of said second region from said first region;
means for transporting the majority carriers in said first region to said third region;
a portion of said second region partially extending between said face and said first region; and the minority carrier diffusion length in said first region being larger than the width thereof.

4. A semiconductor device comprising:
a semiconductor substrate having a major face;
a first semiconductor region of a first conductivity type formed in said major face of said substrate and interfaced with said substrate;
a second semiconductor region of a second conductivity type interfaced with said first region, at least a portion of said second region being below said major face;
a third semiconductor region of a first conductivity type interfaced with said second region and on the opposite side of said second region from said first region;
means for transporting the majority carriers in said first region to said third region;
a portion of said second region partially extending between said face and said first region;
the minority carrier diffusion length in said first region is larger than the width thereof; and the minority carrier diffusion length in said portion is larger than the width thereof.

5. A semiconductor device according to claim 2, in which the surface recombination velocity of said fourth region is smaller than D/L, where D and L are the minority carrier diffusion constant and the minority carrier diffusion length in said fourth region, respectively.

6. A semiconductor device according to claim 4, in which the surface recombination velocity of said portion is smaller than D/L, where D and L are the minority carrier diffusion constant and the minority carrier diffusion length in said portion, respectively.

7. A semiconductor device comprising:
a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type forming a first P-N junction with said first region;
a third semiconductor region of said first conductivity type forming a second P-N junction with said second region which is spaced from said first P-N junction by said second region;
voltage applying means for transporting majority carriers in said first region to said third region;
the width of said first region being smaller than the diffusion length of minority carriers therein; and gate means on said first region and insulated therefrom.

8. A semiconductor device comprising:
a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type forming a first P-N junction with said first region;
a third semiconductor region of said first conductivity type forming a second P-N junction with said second region which is spaced from said first P-N junction by said second region;
voltage applying means for transporting majority carriers in said first region to said third region;
the width of said first region being smaller than the diffusion length of minority carriers therein; and a Schottky barrier interfaced with said first region.