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CA1013867A - Integrated circuit isolation structure and manufacture - Google Patents

Integrated circuit isolation structure and manufacture

Info

Publication number
CA1013867A
CA1013867A CA192,912A CA192912A CA1013867A CA 1013867 A CA1013867 A CA 1013867A CA 192912 A CA192912 A CA 192912A CA 1013867 A CA1013867 A CA 1013867A
Authority
CA
Canada
Prior art keywords
manufacture
integrated circuit
isolation structure
circuit isolation
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA192,912A
Other versions
CA192912S (en
Inventor
Dan R. Boyd
Anthony G. Dervan
Jerry W. Zimmer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Application granted granted Critical
Publication of CA1013867A publication Critical patent/CA1013867A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • H01L21/30608Anisotropic liquid etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
CA192,912A 1973-02-21 1974-02-19 Integrated circuit isolation structure and manufacture Expired CA1013867A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US33449873A 1973-02-21 1973-02-21

Publications (1)

Publication Number Publication Date
CA1013867A true CA1013867A (en) 1977-07-12

Family

ID=23307490

Family Applications (1)

Application Number Title Priority Date Filing Date
CA192,912A Expired CA1013867A (en) 1973-02-21 1974-02-19 Integrated circuit isolation structure and manufacture

Country Status (4)

Country Link
JP (1) JPS49115688A (en)
CA (1) CA1013867A (en)
DE (1) DE2408402A1 (en)
GB (1) GB1461943A (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55153345A (en) * 1979-05-18 1980-11-29 Fujitsu Ltd Manufacture of semiconductor device
JPS56160050A (en) * 1980-05-14 1981-12-09 Fujitsu Ltd Semiconductor device and manufacture thereof
US4394196A (en) * 1980-07-16 1983-07-19 Tokyo Shibaura Denki Kabushiki Kaisha Method of etching, refilling and etching dielectric grooves for isolating micron size device regions
JPS5743438A (en) * 1980-08-29 1982-03-11 Toshiba Corp Semiconductor device and manufacture thereof
US4630343A (en) * 1981-03-16 1986-12-23 Fairchild Camera & Instrument Corp. Product for making isolated semiconductor structure
DE3273863D1 (en) * 1981-03-16 1986-11-20 Fairchild Camera Instr Co Low temperature melting binary glasses for leveling surfaces of integrated circuits containing isolation grooves
US4492717A (en) * 1981-07-27 1985-01-08 International Business Machines Corporation Method for forming a planarized integrated circuit
WO1996024161A1 (en) * 1995-01-30 1996-08-08 The Whitaker Corporation Electronic device and process for making same

Also Published As

Publication number Publication date
JPS49115688A (en) 1974-11-05
GB1461943A (en) 1977-01-19
DE2408402A1 (en) 1974-08-22

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