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BR8602717A - Aparelho para efetuar adicao de binarios - Google Patents

Aparelho para efetuar adicao de binarios

Info

Publication number
BR8602717A
BR8602717A BR8602717A BR8602717A BR8602717A BR 8602717 A BR8602717 A BR 8602717A BR 8602717 A BR8602717 A BR 8602717A BR 8602717 A BR8602717 A BR 8602717A BR 8602717 A BR8602717 A BR 8602717A
Authority
BR
Brazil
Prior art keywords
appliance
add binary
binary
add
Prior art date
Application number
BR8602717A
Other languages
English (en)
Inventor
Bruce Michael Anderson
Brian Edward Brodrick
Original Assignee
Sperry Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Corp filed Critical Sperry Corp
Publication of BR8602717A publication Critical patent/BR8602717A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Networks Using Active Elements (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
  • Complex Calculations (AREA)
BR8602717A 1985-09-11 1986-06-11 Aparelho para efetuar adicao de binarios BR8602717A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US77469585A 1985-09-11 1985-09-11

Publications (1)

Publication Number Publication Date
BR8602717A true BR8602717A (pt) 1987-04-14

Family

ID=25101986

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8602717A BR8602717A (pt) 1985-09-11 1986-06-11 Aparelho para efetuar adicao de binarios

Country Status (4)

Country Link
EP (1) EP0214836A1 (pt)
JP (1) JPS6261120A (pt)
BR (1) BR8602717A (pt)
ES (1) ES2001127A6 (pt)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02501242A (ja) * 1987-08-25 1990-04-26 ヒユーズ・エアクラフト・カンパニー 高速デジタル計算システム
US5136539A (en) * 1988-12-16 1992-08-04 Intel Corporation Adder with intermediate carry circuit
KR100224278B1 (ko) * 1996-12-18 1999-10-15 윤종용 패스 트랜지스터 로직을 사용하는 조건 합 가산기 및 그것을 구비한 집적 회로
US5852568A (en) * 1997-01-27 1998-12-22 S3 Incorporated System and method for a fast carry/sum select adder
US20030088602A1 (en) * 2001-11-08 2003-05-08 Koninklijke Philips Electronics N.V. High-speed computation in arithmetic logic circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3100835A (en) * 1960-01-06 1963-08-13 Ibm Selecting adder

Also Published As

Publication number Publication date
JPS6261120A (ja) 1987-03-17
EP0214836A1 (en) 1987-03-18
ES2001127A6 (es) 1988-04-16

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