AU674444B2

AU674444B2 - Phase detector

Info

Publication number: AU674444B2
Application number: AU75885/94A
Authority: AU
Inventors: Klaus-Hartwig Rieder
Original assignee: Alcatel NV
Current assignee: Alcatel Lucent NV
Priority date: 1993-10-23
Filing date: 1994-10-17
Publication date: 1996-12-19
Anticipated expiration: 2014-10-17
Also published as: DE4336240A1; AU7588594A

Description

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P/00/01i1 28/5/91 Regulation 3.2

AUSTRALIA

Patents Act 1990

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ORIGINAL

COMPLETE SPECIFICATION STANDARD PATENT Invention Title: "PHASE DETECTOR" The following statement is a full description of this invention, including the best method of performing it known to us:- 450*

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5.5555 This invention relates to a circuit arrangement for a digital phase detector which is used in digital phase-locked loops. These phase-locked loops are significant components of clock generators, such as are used, for example, in digital communication networks. The distortion-free transmission of data requires a high constancy of the clock supplies in the individual exchanges, which are synchronised via the trunk system from a centralised standard frequency equipment in the top level of the hierarchic arrangement. The synchronisation of the clock signal with an external reference signal is customarily achieved with a phase-locked loop which, in accordance with CCITT, is required to have a low bandwidth, less than 100 mHz, in order to be able to filter the jitter of the external reference signal. A digital phase detector is used for comparing the external reference signal with the clock signal derived from a quartz oscillator. It is well known, with an arrangement for the digital determination of the phase difference between two signals, to determine the phase difference of the zero crossings of two signals, see DE 40 25 307 Al.

For this purpose, a counter is started with the edge of a first clock pulse, and stopped again with the edge of a second clock pulse. The counter is controlled by a clock frequency which is a multiple of the frequency of the clock signals, so that the count is a measure of the phase difference between the first and second clock frequencies. The resultant count is evaluated, the counter is S cleared and the next pulse edge is awaited. The measuring accuracy with this solution is determined by the clock frequency of the counter. Although an :2S increase of the accuracy be achieved by increasing the clock frequency of the counter, there art~ Lechnical limits to this. Furthermore, implementation of the phase detector described requires considerable expenditure on the circuitry.

Thus it is an object of the present invention to describe a circuit arrangement for a digital phase detector which can be easily implemented with digital circuits and permits a high phase resolution with great linearity in a large measurement range.

According to the invention there is provided a circuit arrangement for a digital phase detector in a digital phase-locked loop which is used to 3 synchronise an oscillator in phase and frequency to a reference frequency, wherein the output of the oscillator is connected to the clock input of a counter whose counter-stage outputs are connected to the data inputs of a register, the clock input of the register being connected to a reference clock generator and the register output is connected via a loop filter to the control input of the oscillator.

The invention is based on the notion that functions and components which are in any case implemented in a phase-locked loop, are used for the measurement of the phase difference between the system clock and the reference clock signal, so that the circuit cost for the digital phase detector is considerably reduced, compared to known solutions.

In order that the invention may be readily carried into effect, g sembodiments thereof will now be described in relation to the accompanying drawings, in which: Figure 1 shows a block diagram of a phase-locked loop in accordance with the prior art, Figure 2 shows a block diagram of a phase-locked loop with a phase detector according to the invention and S:'g Figure 3 shows a block diagram of a phase-locked loop with a variation of the phase detector according to the invention.

According to Figure 1, a generally well known nhase-locked loop according to the prior art consists basically of a voltage- controlled crystal oscillator 1, a phase detector 2 and a loop filter 3. This configuration applies for a digital as well as for an analogue phase-locked loop. The following implementations refer to a digital phase-locked loop. In this case, in order to fulfil the relevant frequency requirements, the digital phase-locked loop is augmented with a first counter 4, a second counter 5 and a divider 6. The voltage- controlled crystal oscillator 1 is driven by a digital signal and therefore either contains a digital/analogue converter, or it is designed as a numericallycontrolled oscillator. The loop filter is designed as a digital circuit and implemented as an integrated circuit. Since the reference clock signal and the output signal of the voltage-controlled crystal oscillator have different frequencies in practical cases, a first counter 4 and a second counter 5 are provided to deliver input signals of the same frequency to the phase detector 2.

As shown in Figure 2, the phase detector circuit according to the invention consists of a register 21 whose clock input c is connected to a first counter 4, whose data input d is connected to a second counter 51 and whose data output q is connected via a loop filter 31 to the numerically-controlled crystal oscillator 1. The frequency divider 6 which follows the numericallycontrolled crystal oscillator 1 only serves to divide the oscillator output down to the required system frequency. The method of operation of the circuit arrangement depends on the fact that the state of the second counter 51 is a measure of the phase difference between the reference frequency and the frequency of the numerically-controlled crystal oscillator 1, and that, if phase i: differences exist, a control of the numerically-controlled crystal oscillator 1 takes place by means of the digital value which appears at the data output q of the register 21. The method of operation will be explained in more detail by means of a numerical example. The frequency of the reference signal f 2.048 MHz is divided down to a frequency f 2 2 kHz by the first counter 4, which is used to clock the register 21 clock input c. The count capacity of the second counter 51 should be 256 so that an 8-bit-wide data signal is always available at the outputs of the counter. The second counter 51 is driven by the "o numerically-controlled crystal oscillator 1 with its output frequency f 3 16.384 S MHz, which corresponds to a pulse spacing of 61 ns. With the reference frequency and the crystal oscillator 1 output frequency synchronised, the output value of the second counter 51 can, for example, be 128, by way of definition.

If now the oscillator frequency f 3 changes to higher values compared to the reference frequency f then the output value of the second counter 51 becomes greater than 128, or the output value becomes less than 128 if the change is to a lower value of frequency. In time with the output signal of the first counter 4, the current count of the second counter 51 is entered into the register 21, whose output value is a measure of the phase difference between the reference frequency and the oscillator. This output value is used to control the numerically-controlled crystal oscillator 1. With the numerical example chosen above, the resolution of the phase detector is 61 ns, and the measurement range becomes t 15.616 ps for an 8-bit-wide data signal from the second counter 51. Accordingly the resolution can be increased by increasing the clock frequency of the oscillator, and the measurement range can be increased by widening the data signal of the second counter 51, as needed by the technical requirements. The fact that the counter 51 overflows several times during a period of the 2 kHz signal before the count is evaluated, does not interfere with the operation of the phase detector. The maximum data width of the counter is determined by the ratio of the crystal oscillator frequency f 3 16.384 MHz to the reference frequency f 2 2 kHz, and in the present example is 13 bits.

With the circuit arrangement according to the invention, a phase detector is realised merely with one register of the simplest construction, by using S° components which are already provided in a digital phase-locked loop.

In order to prevent the data being entered into the register 21 just at that *eo* instant when the data content of the second counter 51 changes, it is expedient to insert a D flip-flop 8 between the first counter 4 and the register 21, as shown in Figure 3. In this way, the reference signal is delayed by the D flip-flop 8 until the clock signal at the input of the second counter 51 changes from high to low. An inverter 7 is required to provide the necessary voltage change from low to high of the clock pulse edge for the D flip-flop 8.

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ABSTRACT

A digital phase detector is part of a clock generator in a phase-locked loop and serves for the frequency and phase comparison between a reference clock signal and the oscillator signal. It is the object of the invention to describe a phase detector which can be easily implemented with digital circuits and which permits a high phase resolution with great linearity in a large measurement range. To solve this task, functions and components which are in any case implemented, or provided, in a phase-locked loop, are used for the measurement of the phase difference. According to the invention, the circuit arrangement consists of a counter (51) driven by an oscillator with the counter value being applied, in time with the reference signal, to a register (21) at whose output a digital value is available as a measure of the phase difference. Since the counter (51) is usually a component of a phase-locked loop, in the present case only a register (21) of simple construction is required instead of a conventional phase detector, The resolution of the phase detector can be increased by increasing the clock frequency, and the measurement range can be increased by widening the data signal of the counter (51).

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Claims

1. A circuit arrangement for a digital phase detector in a digital phase-locked loop which is used to synchronise an oscillator in phase and frequency to a reference frequency, wherein the output of the oscillator is connected to the clock input of a counter whose counter-stage outputs are connected to the data inputs of a register, the clock input of the register being connected to a reference clock generator and the register output is connected via a loop filter to the control input of the oscillator.

2. A circuit arrangement as claimed in Claim 1, wherein a counter is clocked with the output frequency of the oscillator where the count of the counter is entered into a register at the rate of the reference frequency, the register output signal being evaluated 3s a measure of the phase angle difference between the oscillator frequency and the reference frequency and oo S. then used to control the oscillator.

3. A circuit arrangement as claimed in Claim 1, wherein the clock input of the register is connected to the output of a D flip-flop whose clock input is connected with the reference clock generator and whose data input can be connected, if required, to the output of the oscillator via an inverter.

4. A circuit arrangement substantially as herein described will reference to 20 Figures 2 and 3 of the accompanying drawings. too.• too•• Sto DATED THIS FIRST DAY OF SEPTEMBER 1994 Vt• ~ALCATEL N.V ABSTRACT A digital phase detector is part of a clock generator in a phase-locked loop and serves for the frequency and phase comparison between a reference clock signal and the oscillator signal. It is the object of the invention to describe a phase detector which can be easily implemented with digital circuits and which permits a high phase resolution with great linearity in a large measurement range. To solve this task, functions and components which are in any case implemented, or provided, in a phase-locked loop, are used for the measurement of the phase difference. According to the invention, the circuit arrangement consists of a counter (51) driven by an oscillator with the S counter value being applied, in time with the reference signal, to a register (21) at whose output a digital value is available as a measure of the phase difference. Since the counter (51) is usually a component of a phase-locked loop, in the present case only a register (21) of simple construction is required instead of a conventional phase detector. The resolution of the phase detector can be increased by increasing the clock frequency, and the measurement range can be increased by widening the data signal of the counter (51). Figure 2 Soo a