AU6622294A - Two speed bus clock allowing operation of high speed peripherals - Google Patents
Two speed bus clock allowing operation of high speed peripheralsInfo
- Publication number
- AU6622294A AU6622294A AU66222/94A AU6622294A AU6622294A AU 6622294 A AU6622294 A AU 6622294A AU 66222/94 A AU66222/94 A AU 66222/94A AU 6622294 A AU6622294 A AU 6622294A AU 6622294 A AU6622294 A AU 6622294A
- Authority
- AU
- Australia
- Prior art keywords
- bus clock
- peripherals
- allowing operation
- high speed
- speed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US041994 | 1987-04-24 | ||
| US4199493A | 1993-04-02 | 1993-04-02 | |
| PCT/US1994/003424 WO1994023370A1 (en) | 1993-04-02 | 1994-04-01 | Two speed bus clock allowing operation of high speed peripherals |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AU6622294A true AU6622294A (en) | 1994-10-24 |
Family
ID=21919483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU66222/94A Abandoned AU6622294A (en) | 1993-04-02 | 1994-04-01 | Two speed bus clock allowing operation of high speed peripherals |
Country Status (2)
| Country | Link |
|---|---|
| AU (1) | AU6622294A (en) |
| WO (1) | WO1994023370A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5958033A (en) * | 1997-08-13 | 1999-09-28 | Hewlett Packard Company | On- the-fly partitionable computer bus for enhanced operation with varying bus clock frequencies |
| US6134621A (en) * | 1998-06-05 | 2000-10-17 | International Business Machines Corporation | Variable slot configuration for multi-speed bus |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5237676A (en) * | 1989-01-13 | 1993-08-17 | International Business Machines Corp. | High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected device |
| US5191657A (en) * | 1989-11-09 | 1993-03-02 | Ast Research, Inc. | Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus |
| US5263172A (en) * | 1990-04-16 | 1993-11-16 | International Business Machines Corporation | Multiple speed synchronous bus having single clock path for providing first or second clock speed based upon speed indication signals |
| US5191581A (en) * | 1990-12-07 | 1993-03-02 | Digital Equipment Corporation | Method and apparatus for providing high performance interconnection between interface circuits coupled to information buses |
-
1994
- 1994-04-01 AU AU66222/94A patent/AU6622294A/en not_active Abandoned
- 1994-04-01 WO PCT/US1994/003424 patent/WO1994023370A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO1994023370A1 (en) | 1994-10-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| AU6398594A (en) | De-skewer for serial data bus | |
| AU7315494A (en) | High speed dominant mode bus for differential signals | |
| AU1510497A (en) | Laptop computer | |
| AU5196690A (en) | Docking module | |
| GB2279473B (en) | Distributed clock signal and clock signal interrupt | |
| AU4175489A (en) | Transparent coatings for graphics application | |
| AU6378396A (en) | Glitch-free clock enable circuit | |
| EP0649087A3 (en) | Computer system | |
| AU1435595A (en) | Wearable personal computer system | |
| AU6834394A (en) | Computer keyboard | |
| AU3156095A (en) | High speed deadlock free bridge circuit | |
| AU1063792A (en) | Computer having function of resume process | |
| AU4238093A (en) | Novel retinol derivatives and uses thereof | |
| GB2258069B (en) | High speed computer graphics bus | |
| AU3456093A (en) | Computer backplane having line switches | |
| AU3593689A (en) | Cyclopentane derivatives | |
| AU6622294A (en) | Two speed bus clock allowing operation of high speed peripherals | |
| AU7528191A (en) | High speed bus system | |
| AU663823B2 (en) | Clock generator | |
| AU3437193A (en) | Expansion bus | |
| AU2553592A (en) | Computer graphics system | |
| AU7072091A (en) | Computer bus system | |
| AU118472S (en) | Notebook computer | |
| AU5988494A (en) | Graphic state processing | |
| AU7338894A (en) | Computer assembly |