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AU2002364854A1 - Method and device for converting a quantized digital value - Google Patents

Method and device for converting a quantized digital value

Info

Publication number
AU2002364854A1
AU2002364854A1 AU2002364854A AU2002364854A AU2002364854A1 AU 2002364854 A1 AU2002364854 A1 AU 2002364854A1 AU 2002364854 A AU2002364854 A AU 2002364854A AU 2002364854 A AU2002364854 A AU 2002364854A AU 2002364854 A1 AU2002364854 A1 AU 2002364854A1
Authority
AU
Australia
Prior art keywords
converting
digital value
quantized digital
quantized
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002364854A
Inventor
Gael Champion
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EADS Telecom SAS
Original Assignee
EADS Telecom SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EADS Telecom SAS filed Critical EADS Telecom SAS
Publication of AU2002364854A1 publication Critical patent/AU2002364854A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • H03M7/3031—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path
    • H03M7/3042—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator being of the error feedback type, i.e. having loop filter stages in the feedback path only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M7/3024—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M7/3026—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
AU2002364854A 2001-12-26 2002-12-18 Method and device for converting a quantized digital value Abandoned AU2002364854A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR01/16874 2001-12-26
FR0116874A FR2834145B1 (en) 2001-12-26 2001-12-26 METHOD AND DEVICE FOR CONVERTING A QUANTIFIED NUMERICAL VALUE
PCT/FR2002/004433 WO2003056702A1 (en) 2001-12-26 2002-12-18 Method and device for converting a quantized digital value

Publications (1)

Publication Number Publication Date
AU2002364854A1 true AU2002364854A1 (en) 2003-07-15

Family

ID=8870993

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002364854A Abandoned AU2002364854A1 (en) 2001-12-26 2002-12-18 Method and device for converting a quantized digital value

Country Status (5)

Country Link
EP (1) EP1459448A1 (en)
AU (1) AU2002364854A1 (en)
CA (1) CA2470176A1 (en)
FR (1) FR2834145B1 (en)
WO (1) WO2003056702A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1298109C (en) * 2004-06-25 2007-01-31 天津大学 Novel lock phase detection circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998038744A1 (en) * 1997-02-27 1998-09-03 Seiko Epson Corporation Oscillator and method for setting oscillation frequency of the same
US6504498B1 (en) * 1999-09-27 2003-01-07 Parthus Ireland Limited Method and apparatus for offset cancellation in a wireless receiver

Also Published As

Publication number Publication date
FR2834145B1 (en) 2004-03-12
WO2003056702A8 (en) 2003-10-30
EP1459448A1 (en) 2004-09-22
WO2003056702A1 (en) 2003-07-10
CA2470176A1 (en) 2003-07-10
FR2834145A1 (en) 2003-06-27

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase