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AU2002233977A1 - Method and apparatus for considering diagonal wiring in placement - Google Patents

Method and apparatus for considering diagonal wiring in placement

Info

Publication number
AU2002233977A1
AU2002233977A1 AU2002233977A AU3397702A AU2002233977A1 AU 2002233977 A1 AU2002233977 A1 AU 2002233977A1 AU 2002233977 A AU2002233977 A AU 2002233977A AU 3397702 A AU3397702 A AU 3397702A AU 2002233977 A1 AU2002233977 A1 AU 2002233977A1
Authority
AU
Australia
Prior art keywords
placement
diagonal wiring
considering
considering diagonal
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002233977A
Inventor
Joseph L. Ganley
Steven Teig
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Simplex Solutions Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/731,891 external-priority patent/US7024650B2/en
Priority claimed from US09/732,181 external-priority patent/US6826737B2/en
Application filed by Simplex Solutions Inc filed Critical Simplex Solutions Inc
Publication of AU2002233977A1 publication Critical patent/AU2002233977A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B7/00—Recording or reproducing by optical means, e.g. recording using a thermal beam of optical radiation by modifying optical properties or the physical structure, reproducing using an optical beam at lower power by sensing optical properties; Record carriers therefor
    • G11B7/08—Disposition or mounting of heads or light sources relatively to record carriers
    • G11B7/085—Disposition or mounting of heads or light sources relatively to record carriers with provision for moving the light beam into, or out of, its operative position or across tracks, otherwise than during the transducing operation, e.g. for adjustment or preliminary positioning or track change or selection
    • G11B7/0857—Arrangements for mechanically moving the whole head
    • G11B7/08582—Sled-type positioners

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AU2002233977A 2000-12-06 2001-12-05 Method and apparatus for considering diagonal wiring in placement Abandoned AU2002233977A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US09/732,181 2000-12-06
US09/731,891 2000-12-06
US09/731,891 US7024650B2 (en) 2000-12-06 2000-12-06 Method and apparatus for considering diagonal wiring in placement
US09/732,181 US6826737B2 (en) 2000-12-06 2000-12-06 Recursive partitioning placement method and apparatus
PCT/US2001/046406 WO2002047165A2 (en) 2000-12-06 2001-12-05 Method and apparatus for considering diagonal wiring in placement

Publications (1)

Publication Number Publication Date
AU2002233977A1 true AU2002233977A1 (en) 2002-06-18

Family

ID=27112314

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002233977A Abandoned AU2002233977A1 (en) 2000-12-06 2001-12-05 Method and apparatus for considering diagonal wiring in placement

Country Status (7)

Country Link
US (1) US6904580B2 (en)
EP (1) EP1362373A2 (en)
JP (1) JP2004529402A (en)
CN (1) CN1529864B (en)
AU (1) AU2002233977A1 (en)
TW (1) TW564575B (en)
WO (1) WO2002047165A2 (en)

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US6957410B2 (en) 2000-12-07 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for adaptively selecting the wiring model for a design region
US7003754B2 (en) * 2000-12-07 2006-02-21 Cadence Design Systems, Inc. Routing method and apparatus that use of diagonal routes
US6826737B2 (en) 2000-12-06 2004-11-30 Cadence Design Systems, Inc. Recursive partitioning placement method and apparatus
US7024650B2 (en) 2000-12-06 2006-04-04 Cadence Design Systems, Inc. Method and apparatus for considering diagonal wiring in placement
US7055120B2 (en) * 2000-12-06 2006-05-30 Cadence Design Systems, Inc. Method and apparatus for placing circuit modules
US7080336B2 (en) 2000-12-06 2006-07-18 Cadence Design Systems, Inc. Method and apparatus for computing placement costs
US7073150B2 (en) 2000-12-07 2006-07-04 Cadence Design Systems, Inc. Hierarchical routing method and apparatus that use diagonal routes
US6915501B2 (en) 2001-01-19 2005-07-05 Cadence Design Systems, Inc. LP method and apparatus for identifying routes
US7096448B2 (en) * 2001-01-19 2006-08-22 Cadence Design Systems, Inc. Method and apparatus for diagonal routing by using several sets of lines
US7398498B2 (en) 2001-08-23 2008-07-08 Cadence Design Systems, Inc. Method and apparatus for storing routes for groups of related net configurations
US6877149B2 (en) * 2001-08-23 2005-04-05 Cadence Design Systems, Inc. Method and apparatus for pre-computing routes
US6795958B2 (en) 2001-08-23 2004-09-21 Cadence Design Systems, Inc. Method and apparatus for generating routes for groups of related node configurations
US6931616B2 (en) 2001-08-23 2005-08-16 Cadence Design Systems, Inc. Routing method and apparatus
US7143382B2 (en) 2001-08-23 2006-11-28 Cadence Design Systems, Inc. Method and apparatus for storing routes
US7058913B1 (en) * 2001-09-06 2006-06-06 Cadence Design Systems, Inc. Analytical placement method and apparatus
US7080342B2 (en) 2002-11-18 2006-07-18 Cadence Design Systems, Inc Method and apparatus for computing capacity of a region for non-Manhattan routing
US7480885B2 (en) 2002-11-18 2009-01-20 Cadence Design Systems, Inc. Method and apparatus for routing with independent goals on different layers
US6996789B2 (en) 2002-11-18 2006-02-07 Cadence Design Systems, Inc. Method and apparatus for performing an exponential path search
US6988257B2 (en) * 2002-11-18 2006-01-17 Cadence Design Systems, Inc. Method and apparatus for routing
US7010771B2 (en) 2002-11-18 2006-03-07 Cadence Design Systems, Inc. Method and apparatus for searching for a global path
US7624367B2 (en) 2002-11-18 2009-11-24 Cadence Design Systems, Inc. Method and system for routing
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US7047513B2 (en) 2002-11-18 2006-05-16 Cadence Design Systems, Inc. Method and apparatus for searching for a three-dimensional global path
US7171635B2 (en) 2002-11-18 2007-01-30 Cadence Design Systems, Inc. Method and apparatus for routing
US7089519B1 (en) 2002-12-31 2006-08-08 Cadence Design System, Inc. Method and system for performing placement on non Manhattan semiconductor integrated circuits
US7506295B1 (en) 2002-12-31 2009-03-17 Cadence Design Systems, Inc. Non manhattan floor plan architecture for integrated circuits
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CN102054068B (en) * 2009-10-30 2014-06-18 新思科技(上海)有限公司 Method and device for distributing line network in chip design
US20230267260A1 (en) * 2022-02-18 2023-08-24 Changxin Memory Technologies, Inc. Method for layout placement and routing, circuit layout, electronic device, and storage medium
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Also Published As

Publication number Publication date
WO2002047165A2 (en) 2002-06-13
CN1529864A (en) 2004-09-15
EP1362373A2 (en) 2003-11-19
TW564575B (en) 2003-12-01
US6904580B2 (en) 2005-06-07
JP2004529402A (en) 2004-09-24
WO2002047165A3 (en) 2003-08-21
US20020170027A1 (en) 2002-11-14
CN1529864B (en) 2010-05-05

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