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AU2001271901A1 - High speed packet processing architecture - Google Patents

High speed packet processing architecture

Info

Publication number
AU2001271901A1
AU2001271901A1 AU2001271901A AU7190101A AU2001271901A1 AU 2001271901 A1 AU2001271901 A1 AU 2001271901A1 AU 2001271901 A AU2001271901 A AU 2001271901A AU 7190101 A AU7190101 A AU 7190101A AU 2001271901 A1 AU2001271901 A1 AU 2001271901A1
Authority
AU
Australia
Prior art keywords
high speed
packet processing
speed packet
processing architecture
architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001271901A
Inventor
Emil Yu-Ming Chao
Nirav Pravinkumar Dagli
Alarabi Omar Hassen
Sriram Krishnan
Kwei-Yao Peng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Entridia Corp
Original Assignee
Entridia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Entridia Corp filed Critical Entridia Corp
Publication of AU2001271901A1 publication Critical patent/AU2001271901A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/32—Flow control; Congestion control by discarding or delaying data units, e.g. packets or frames
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/58—Association of routers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/58—Association of routers
    • H04L45/583—Stackable routers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/60—Router architectures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H04L45/745—Address table lookup; Address filtering
    • H04L45/7453—Address table lookup; Address filtering using hashing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/102—Packet switching elements characterised by the switching fabric construction using shared medium, e.g. bus or ring
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9047—Buffering arrangements including multiple buffers, e.g. buffer pools
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9078—Intermediate storage in different physical parts of a node or terminal using an external memory or storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
AU2001271901A 2000-07-07 2001-07-06 High speed packet processing architecture Abandoned AU2001271901A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US61161600A 2000-07-07 2000-07-07
US61199700A 2000-07-07 2000-07-07
US09611616 2000-07-07
US09611997 2000-07-07
PCT/US2001/021496 WO2002005494A1 (en) 2000-07-07 2001-07-06 High speed packet processing architecture

Publications (1)

Publication Number Publication Date
AU2001271901A1 true AU2001271901A1 (en) 2002-01-21

Family

ID=27086552

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001271901A Abandoned AU2001271901A1 (en) 2000-07-07 2001-07-06 High speed packet processing architecture

Country Status (2)

Country Link
AU (1) AU2001271901A1 (en)
WO (1) WO2002005494A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2396447A (en) * 2002-12-21 2004-06-23 Robert Clive Roust Data flow processing technique
US20040174872A1 (en) * 2003-03-03 2004-09-09 Nokia Corporation Apparatus and method for performing an address resolution protocol function
US8565092B2 (en) * 2010-11-18 2013-10-22 Cisco Technology, Inc. Dynamic flow redistribution for head of line blocking avoidance
US8705366B2 (en) 2012-01-23 2014-04-22 Cisco Technology, Inc. Dynamic load balancing without packet reordering
CN104184664B (en) * 2014-08-05 2017-07-04 新华三技术有限公司 Route forwarding table items generation method and device
WO2017209669A1 (en) * 2016-06-02 2017-12-07 Telefonaktiebolaget Lm Ericsson (Publ) Method and network node for handling sctp packets
US20230050279A1 (en) * 2021-08-12 2023-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit and method of operating same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07107990B2 (en) * 1992-11-12 1995-11-15 日本電気株式会社 ATM-based transmitter and communication system

Also Published As

Publication number Publication date
WO2002005494A1 (en) 2002-01-17

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