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AU1564801A - Maintenance of speculative state of parallel executed jobs in an information processing system - Google Patents

Maintenance of speculative state of parallel executed jobs in an information processing system

Info

Publication number
AU1564801A
AU1564801A AU15648/01A AU1564801A AU1564801A AU 1564801 A AU1564801 A AU 1564801A AU 15648/01 A AU15648/01 A AU 15648/01A AU 1564801 A AU1564801 A AU 1564801A AU 1564801 A AU1564801 A AU 1564801A
Authority
AU
Australia
Prior art keywords
maintenance
information processing
processing system
speculative state
executed jobs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU15648/01A
Inventor
Per Anders Holmberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of AU1564801A publication Critical patent/AU1564801A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)
AU15648/01A 1999-11-12 2000-11-10 Maintenance of speculative state of parallel executed jobs in an information processing system Abandoned AU1564801A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/438,325 US6345351B1 (en) 1999-11-12 1999-11-12 Maintenance of speculative state of parallel executed jobs in an information processing system
US09438325 1999-11-12
PCT/SE2000/002206 WO2001035225A1 (en) 1999-11-12 2000-11-10 Maintenance of speculative state of parallel executed jobs in an information processing system

Publications (1)

Publication Number Publication Date
AU1564801A true AU1564801A (en) 2001-06-06

Family

ID=23740212

Family Applications (1)

Application Number Title Priority Date Filing Date
AU15648/01A Abandoned AU1564801A (en) 1999-11-12 2000-11-10 Maintenance of speculative state of parallel executed jobs in an information processing system

Country Status (5)

Country Link
US (1) US6345351B1 (en)
AU (1) AU1564801A (en)
DE (1) DE10085187T1 (en)
GB (1) GB2371660B (en)
WO (1) WO2001035225A1 (en)

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US6804766B1 (en) * 1997-11-12 2004-10-12 Hewlett-Packard Development Company, L.P. Method for managing pages of a designated memory object according to selected memory management policies
JP3537356B2 (en) * 1998-12-09 2004-06-14 株式会社日立製作所 Delay factor analysis method in job system
US6665708B1 (en) * 1999-11-12 2003-12-16 Telefonaktiebolaget Lm Ericsson (Publ) Coarse grained determination of data dependence between parallel executed jobs in an information processing system
US6918028B1 (en) * 2000-03-28 2005-07-12 Analog Devices, Inc. Pipelined processor including a loosely coupled side pipe
US7051192B2 (en) * 2000-05-31 2006-05-23 Sun Microsystems, Inc. Facilitating value prediction to support speculative program execution
US6684398B2 (en) * 2000-05-31 2004-01-27 Sun Microsystems, Inc. Monitor entry and exit for a speculative thread during space and time dimensional execution
US7213098B2 (en) * 2000-11-28 2007-05-01 Sun Microsystems, Inc. Computer system and method providing a memory buffer for use with native and platform-independent software code
JP3729064B2 (en) * 2000-11-29 2005-12-21 日本電気株式会社 Data dependency detection device
FR2820222B1 (en) * 2001-01-26 2003-03-21 Schneider Automation METHOD FOR PROGRAMMING AN AUTOMATION APPLICATION
US6986006B2 (en) * 2002-04-17 2006-01-10 Microsoft Corporation Page granular curtained memory via mapping control
US7565509B2 (en) * 2002-04-17 2009-07-21 Microsoft Corporation Using limits on address translation to control access to an addressable entity
US9043194B2 (en) * 2002-09-17 2015-05-26 International Business Machines Corporation Method and system for efficient emulation of multiprocessor memory consistency
US8108843B2 (en) 2002-09-17 2012-01-31 International Business Machines Corporation Hybrid mechanism for more efficient emulation and method therefor
US7953588B2 (en) * 2002-09-17 2011-05-31 International Business Machines Corporation Method and system for efficient emulation of multiprocessor address translation on a multiprocessor host
US7076769B2 (en) * 2003-03-28 2006-07-11 Intel Corporation Apparatus and method for reproduction of a source ISA application state corresponding to a target ISA application state at an execution stop point
US7210127B1 (en) 2003-04-03 2007-04-24 Sun Microsystems Methods and apparatus for executing instructions in parallel
US7631314B2 (en) * 2003-08-26 2009-12-08 International Business Machines Corporation Method and system for dynamically associating type information and creating and processing meta-data in a service oriented architecture
US7600221B1 (en) 2003-10-06 2009-10-06 Sun Microsystems, Inc. Methods and apparatus of an architecture supporting execution of instructions in parallel
US7784060B2 (en) * 2003-11-06 2010-08-24 Intel Corporation Efficient virtual machine communication via virtual machine queues
US8621179B2 (en) * 2004-06-18 2013-12-31 Intel Corporation Method and system for partial evaluation of virtual address translations in a simulator
EP2115583A2 (en) * 2007-01-30 2009-11-11 Nema Labs Ab Speculative throughput computing
KR100864834B1 (en) * 2007-04-30 2008-10-23 한국전자통신연구원 Apparatus and method for data transfer between multiple processors using memory reallocation
US8429377B2 (en) * 2010-01-08 2013-04-23 International Business Machines Corporation Optimizing TLB entries for mixed page size storage in contiguous memory
US9311260B2 (en) * 2013-12-09 2016-04-12 Jack Mason Context preservation during thread level speculative execution
US10209997B2 (en) * 2015-06-02 2019-02-19 Wisconsin Alumni Research Foundation Computer architecture for speculative parallel execution
US11188367B2 (en) * 2017-08-21 2021-11-30 Nicira Inc. Guest operating system physical memory page protection using hypervisor

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5487156A (en) 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
US5339415A (en) 1990-06-11 1994-08-16 Cray Research, Inc. Dual level scheduling of processes to multiple parallel regions of a multi-threaded program on a tightly coupled multiprocessor computer system
US5751995A (en) 1994-01-04 1998-05-12 Intel Corporation Apparatus and method of maintaining processor ordering in a multiprocessor system which includes one or more processors that execute instructions speculatively
US5729710A (en) 1994-06-22 1998-03-17 International Business Machines Corporation Method and apparatus for management of mapped and unmapped regions of memory in a microkernel data processing system
US5812811A (en) 1995-02-03 1998-09-22 International Business Machines Corporation Executing speculative parallel instructions threads with forking and inter-thread communication
EP0829045B1 (en) 1995-06-01 2002-09-04 Fujitsu Limited Coordinating the issue of instructions in a parallel instruction processing system
US5751983A (en) 1995-10-03 1998-05-12 Abramson; Jeffrey M. Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations
US5754812A (en) 1995-10-06 1998-05-19 Advanced Micro Devices, Inc. Out-of-order load/store execution control
US5778210A (en) 1996-01-11 1998-07-07 Intel Corporation Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time
US5748934A (en) 1996-05-31 1998-05-05 Hewlett-Packard Company Operand dependency tracking system and method for a processor that executes instructions out of order and that permits multiple precision data words
US5781752A (en) 1996-12-26 1998-07-14 Wisconsin Alumni Research Foundation Table based data speculation circuit for parallel processing computer
US5838941A (en) 1996-12-30 1998-11-17 Intel Corporation Out-of-order superscalar microprocessor with a renaming device that maps instructions from memory to registers
US5913230A (en) * 1997-01-07 1999-06-15 Richardson; John J. Object and method for providing efficient multi-user access to shared operating system kernal code using instancing
US5887161A (en) 1997-03-31 1999-03-23 International Business Machines Corporation Issuing instructions in a processor supporting out-of-order execution

Also Published As

Publication number Publication date
GB2371660B (en) 2004-06-02
DE10085187T1 (en) 2002-10-31
WO2001035225A1 (en) 2001-05-17
US6345351B1 (en) 2002-02-05
GB0209869D0 (en) 2002-06-05
GB2371660A (en) 2002-07-31

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase