[go: up one dir, main page]

ATE493733T1 - Unterteilte inhaltsadressierbare speicherschaltung - Google Patents

Unterteilte inhaltsadressierbare speicherschaltung

Info

Publication number
ATE493733T1
ATE493733T1 AT01944411T AT01944411T ATE493733T1 AT E493733 T1 ATE493733 T1 AT E493733T1 AT 01944411 T AT01944411 T AT 01944411T AT 01944411 T AT01944411 T AT 01944411T AT E493733 T1 ATE493733 T1 AT E493733T1
Authority
AT
Austria
Prior art keywords
cam
cam blocks
blocks
block
block select
Prior art date
Application number
AT01944411T
Other languages
English (en)
Inventor
Jose Pereira
Original Assignee
Netlogic Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/590,775 external-priority patent/US6687785B1/en
Priority claimed from US09/590,428 external-priority patent/US6763425B1/en
Priority claimed from US09/590,642 external-priority patent/US6324087B1/en
Application filed by Netlogic Microsystems Inc filed Critical Netlogic Microsystems Inc
Application granted granted Critical
Publication of ATE493733T1 publication Critical patent/ATE493733T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90—Details of database functions independent of the retrieved data types
    • G06F16/903—Querying
    • G06F16/90335—Query processing
    • G06F16/90339—Query processing by using parallel associative memories or content-addressable memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Linguistics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Traffic Control Systems (AREA)
  • Photoreceptors In Electrophotography (AREA)
  • Lubrication Of Internal Combustion Engines (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Radio Relay Systems (AREA)
AT01944411T 2000-06-08 2001-06-08 Unterteilte inhaltsadressierbare speicherschaltung ATE493733T1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/590,775 US6687785B1 (en) 2000-06-08 2000-06-08 Method and apparatus for re-assigning priority in a partitioned content addressable memory device
US09/590,428 US6763425B1 (en) 2000-06-08 2000-06-08 Method and apparatus for address translation in a partitioned content addressable memory device
US09/590,642 US6324087B1 (en) 2000-06-08 2000-06-08 Method and apparatus for partitioning a content addressable memory device
PCT/US2001/018736 WO2001095336A2 (en) 2000-06-08 2001-06-08 Partitioned content addressable memory device

Publications (1)

Publication Number Publication Date
ATE493733T1 true ATE493733T1 (de) 2011-01-15

Family

ID=27416568

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01944411T ATE493733T1 (de) 2000-06-08 2001-06-08 Unterteilte inhaltsadressierbare speicherschaltung

Country Status (6)

Country Link
EP (1) EP1290697B1 (de)
JP (1) JP2003536197A (de)
AT (1) ATE493733T1 (de)
AU (1) AU2001266826A1 (de)
DE (1) DE60143745D1 (de)
WO (1) WO2001095336A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6542391B2 (en) * 2000-06-08 2003-04-01 Netlogic Microsystems, Inc. Content addressable memory with configurable class-based storage partition
JP2003303495A (ja) * 2002-04-09 2003-10-24 Fujitsu Ltd 半導体記憶装置
US6925464B2 (en) * 2002-06-13 2005-08-02 Intel Corporation Method and system for performing inserts and lookups in memory
US8243733B2 (en) * 2008-06-19 2012-08-14 Marvell World Trade Ltd. Cascaded memory tables for searching

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06251589A (ja) * 1993-03-02 1994-09-09 Hitachi Ltd 連想メモリ入出力制御回路
JPH0721785A (ja) * 1993-06-29 1995-01-24 Kawasaki Steel Corp 半導体メモリ
US5602795A (en) * 1994-01-12 1997-02-11 Sun Microsystems, Inc. Method and apparatus for implementing a high-speed dynamic line driver
JP3703518B2 (ja) * 1995-03-30 2005-10-05 川崎マイクロエレクトロニクス株式会社 連想メモリシステム
US5818350A (en) * 1995-04-11 1998-10-06 Lexar Microsystems Inc. High performance method of and system for selecting one of a plurality of IC chip while requiring minimal select lines
US6041389A (en) * 1995-11-16 2000-03-21 E Cirrus Logic, Inc. Memory architecture using content addressable memory, and systems and methods using the same
JP3816560B2 (ja) * 1995-12-25 2006-08-30 株式会社ルネサステクノロジ 連想メモリ回路のテスト方法及び連想メモリ回路のテスト回路
JP3190868B2 (ja) * 1997-11-21 2001-07-23 エヌイーシーマイクロシステム株式会社 連想メモリ装置
US6044005A (en) * 1999-02-03 2000-03-28 Sibercore Technologies Incorporated Content addressable memory storage device

Also Published As

Publication number Publication date
EP1290697B1 (de) 2010-12-29
WO2001095336A2 (en) 2001-12-13
AU2001266826A1 (en) 2001-12-17
EP1290697A2 (de) 2003-03-12
WO2001095336A3 (en) 2002-07-25
DE60143745D1 (de) 2011-02-10
JP2003536197A (ja) 2003-12-02

Similar Documents

Publication Publication Date Title
US6246601B1 (en) Method and apparatus for using an inter-row configurable content addressable memory
US6910097B1 (en) Classless interdomain routing using binary content addressable memory
US6252789B1 (en) Inter-row configurability of content addressable memory
US5706224A (en) Content addressable memory and random access memory partition circuit
US6502163B1 (en) Method and apparatus for ordering entries in a ternary content addressable memory
US6243281B1 (en) Method and apparatus for accessing a segment of CAM cells in an intra-row configurable CAM system
JP3773171B2 (ja) Ｃａｍおよびｒａｍのアドレス並列処理のための装置および方法
KR970071283A (ko) 캐쉬 메모리 및 그 동작 방법
US6374325B1 (en) Content addressable memory (CAM)
ATE362179T1 (de) Schaltung und verfahren zur ausführung von suchoperationen variabler breite in einem inhaltsadressierbaren speicher
GB1532278A (en) Data processing system and memory module therefor
ATE373307T1 (de) Simultaner mehrbank für flash-speicher
JPS635839B2 (de)
KR20130105393A (ko) 내용 참조 메모리 시스템
US7188211B2 (en) Block programmable priority encoder in a CAM
KR950030151A (ko) 반도체 기억장치
US6718432B1 (en) Method and apparatus for transparent cascading of multiple content addressable memory devices
US20180247694A1 (en) Data tables in content addressable memory
ATE406657T1 (de) SPEICHERANORDNUNG MIT UNTERSCHIEDLICHER ßBURSTß ADDRESSIERUNGSREIHEFOLGE FÜR LESE- UND SCHREIBVORGÄNGE
KR900012161A (ko) 집적된 매트릭스 메모리와 집적회로
JP2000353388A (ja) 内容参照可能メモリの改良
US7099992B2 (en) Distributed programmable priority encoder capable of finding the longest match in a single operation
KR930005025A (ko) 저전력용 블럭 선택 기능을 가지는 반도체 메모리 장치
ATE493733T1 (de) Unterteilte inhaltsadressierbare speicherschaltung
US6751701B1 (en) Method and apparatus for detecting a multiple match in an intra-row configurable CAM system

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties