[go: up one dir, main page]

ATE463786T1 - Hochleistungsfähiger benutzer-konfigurierbarer prozessor - Google Patents

Hochleistungsfähiger benutzer-konfigurierbarer prozessor

Info

Publication number
ATE463786T1
ATE463786T1 AT04016170T AT04016170T ATE463786T1 AT E463786 T1 ATE463786 T1 AT E463786T1 AT 04016170 T AT04016170 T AT 04016170T AT 04016170 T AT04016170 T AT 04016170T AT E463786 T1 ATE463786 T1 AT E463786T1
Authority
AT
Austria
Prior art keywords
coprocessors
high performance
user configurable
configurable processor
processor
Prior art date
Application number
AT04016170T
Other languages
English (en)
Inventor
Michael Colin George Chapman
Original Assignee
Michael Colin George Chapman
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Michael Colin George Chapman filed Critical Michael Colin George Chapman
Application granted granted Critical
Publication of ATE463786T1 publication Critical patent/ATE463786T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Saccharide Compounds (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
AT04016170T 2004-07-09 2004-07-09 Hochleistungsfähiger benutzer-konfigurierbarer prozessor ATE463786T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04016170A EP1615123B1 (de) 2004-07-09 2004-07-09 Hochleistungsfähiger benutzer-konfigurierbarer Prozessor

Publications (1)

Publication Number Publication Date
ATE463786T1 true ATE463786T1 (de) 2010-04-15

Family

ID=34925678

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04016170T ATE463786T1 (de) 2004-07-09 2004-07-09 Hochleistungsfähiger benutzer-konfigurierbarer prozessor

Country Status (3)

Country Link
EP (1) EP1615123B1 (de)
AT (1) ATE463786T1 (de)
DE (1) DE602004026431D1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8145882B1 (en) * 2006-05-25 2012-03-27 Mips Technologies, Inc. Apparatus and method for processing template based user defined instructions

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IN171198B (de) * 1987-02-24 1992-08-15 Digital Equipment Corp
GB8817911D0 (en) * 1988-07-27 1988-09-01 Int Computers Ltd Data processing apparatus
US6505290B1 (en) * 1997-09-05 2003-01-07 Motorola, Inc. Method and apparatus for interfacing a processor to a coprocessor
US6032252A (en) * 1997-10-28 2000-02-29 Advanced Micro Devices, Inc. Apparatus and method for efficient loop control in a superscalar microprocessor

Also Published As

Publication number Publication date
EP1615123B1 (de) 2010-04-07
EP1615123A1 (de) 2006-01-11
DE602004026431D1 (de) 2010-05-20

Similar Documents

Publication Publication Date Title
TW200739420A (en) Unified non-partitioned register file for a digital signal processor operating in an interleaved multi-threaded environment
JP6143872B2 (ja) 装置、方法、およびシステム
ATE514998T1 (de) Getaktete ports
TW200710718A (en) Register file for a digital signal processor operating in an interleaved multi-threaded environment
US10496413B2 (en) Efficient hardware-based extraction of program instructions for critical paths
MY147118A (en) High performance computing system and method
GB2436506A (en) Register file regions for a processing system
TW200701059A (en) Data access and permute unit
ATE416418T1 (de) Register für datenuebertragung in einem multithreaded prozessor
ATE475930T1 (de) Verzweigungsbefehl für einen mehrfachverarbeitungsprozessor
WO2004068339A3 (en) Multithreaded processor with recoupled data and instruction prefetch
DE602006010160D1 (de) Dynamisch erzeugtes Betriebssystem für Sensorennetze
TW200834333A (en) Methods and systems for configuring computers
WO2009037731A1 (ja) 翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ
TWI781588B (zh) 包含用於控制流向終止的模式特定結束分支之設備、系統及方法
TW200606717A (en) Conditional instruction for a single instruction, multiple data execution engine
WO2007008519A3 (en) Active element machine computation
DE602007013023D1 (de) Testzugangsportschalter
ATE510443T1 (de) Zugangspunkt und sensor eines drahtlosen computernetzes
ATE463786T1 (de) Hochleistungsfähiger benutzer-konfigurierbarer prozessor
JP7495422B2 (ja) 適応的な相互接続ルーティングのためのシステム、装置及び方法
US20110004879A1 (en) Method and apparatus for eliminating wait for boot-up
ATE463011T1 (de) Hierarchische prozessorarchitektur zur videoverarbeitung
Ranga ParrotPiton and ZynqParrot: FPGA Enablements for the BlackParrot RISC-V Processor
DE602005019180D1 (de) Datenverarbeitungsschaltung mit funktionseinheiten mit gemeinsamen leseports

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties