[go: up one dir, main page]

ATE425495T1 - Verfahren und system zum datentransfer - Google Patents

Verfahren und system zum datentransfer

Info

Publication number
ATE425495T1
ATE425495T1 AT04762138T AT04762138T ATE425495T1 AT E425495 T1 ATE425495 T1 AT E425495T1 AT 04762138 T AT04762138 T AT 04762138T AT 04762138 T AT04762138 T AT 04762138T AT E425495 T1 ATE425495 T1 AT E425495T1
Authority
AT
Austria
Prior art keywords
bus
signal
data transfer
master device
request
Prior art date
Application number
AT04762138T
Other languages
English (en)
Inventor
Jenya Chou
Minliang Sun
Original Assignee
Magima Digital Information Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Magima Digital Information Co filed Critical Magima Digital Information Co
Application granted granted Critical
Publication of ATE425495T1 publication Critical patent/ATE425495T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Small-Scale Networks (AREA)
AT04762138T 2004-08-30 2004-08-30 Verfahren und system zum datentransfer ATE425495T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2004/001003 WO2006024193A1 (fr) 2004-08-30 2004-08-30 Procede et systeme pour transfert de donnees

Publications (1)

Publication Number Publication Date
ATE425495T1 true ATE425495T1 (de) 2009-03-15

Family

ID=35999685

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04762138T ATE425495T1 (de) 2004-08-30 2004-08-30 Verfahren und system zum datentransfer

Country Status (5)

Country Link
US (1) US7543093B2 (de)
EP (1) EP1811393B1 (de)
AT (1) ATE425495T1 (de)
DE (1) DE602004019990D1 (de)
WO (1) WO2006024193A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8504992B2 (en) * 2003-10-31 2013-08-06 Sonics, Inc. Method and apparatus for establishing a quality of service model
US9087036B1 (en) 2004-08-12 2015-07-21 Sonics, Inc. Methods and apparatuses for time annotated transaction level modeling
KR100633773B1 (ko) * 2005-07-01 2006-10-13 삼성전자주식회사 버스 시스템 및 버스 중재 방법
US7478183B2 (en) * 2006-05-03 2009-01-13 Cisco Technology, Inc. Method and system for n dimension arbitration algorithm—scalable to any number of end points
US8868397B2 (en) * 2006-11-20 2014-10-21 Sonics, Inc. Transaction co-validation across abstraction layers
US8438320B2 (en) * 2007-06-25 2013-05-07 Sonics, Inc. Various methods and apparatus for address tiling and channel interleaving throughout the integrated system
US9495290B2 (en) * 2007-06-25 2016-11-15 Sonics, Inc. Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction ordering
US8108648B2 (en) * 2007-06-25 2012-01-31 Sonics, Inc. Various methods and apparatus for address tiling
TW201209820A (en) * 2010-05-07 2012-03-01 Mosaid Technologies Inc Method and apparatus for concurrently reading a plurality of memory devices using a single buffer
US8478920B2 (en) * 2010-06-24 2013-07-02 International Business Machines Corporation Controlling data stream interruptions on a shared interface
US8972995B2 (en) 2010-08-06 2015-03-03 Sonics, Inc. Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads
US20120089759A1 (en) * 2010-10-08 2012-04-12 Qualcomm Incorporated Arbitrating Stream Transactions Based on Information Related to the Stream Transaction(s)
CN106897281B (zh) 2015-12-17 2020-08-14 阿里巴巴集团控股有限公司 一种日志分片方法和装置
CN114661644B (zh) * 2022-02-17 2024-04-09 之江实验室 辅助3d架构近存计算加速器系统的预存储dma装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62138948A (ja) 1985-12-13 1987-06-22 Hitachi Ltd デ−タ転送装置
US5129090A (en) 1988-05-26 1992-07-07 Ibm Corporation System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration
US5293493A (en) * 1989-10-27 1994-03-08 International Business Machines Corporation Preemption control for central processor with cache
US5448704A (en) * 1994-03-07 1995-09-05 Vlsi Technology, Inc. Method for performing writes of non-contiguous bytes on a PCI bus in a minimum number of write cycles
US6081860A (en) 1997-11-20 2000-06-27 International Business Machines Corporation Address pipelining for data transfers
US6718422B1 (en) * 1999-07-29 2004-04-06 International Business Machines Corporation Enhanced bus arbiter utilizing variable priority and fairness
US6393500B1 (en) * 1999-08-12 2002-05-21 Mips Technologies, Inc. Burst-configurable data bus
US6775727B2 (en) * 2001-06-23 2004-08-10 Freescale Semiconductor, Inc. System and method for controlling bus arbitration during cache memory burst cycles
US6981073B2 (en) * 2001-07-31 2005-12-27 Wis Technologies, Inc. Multiple channel data bus control for video processing
US7337232B2 (en) * 2002-03-28 2008-02-26 Sony Corporation Method and system for providing and controlling sub-burst data transfers
US6981088B2 (en) * 2003-03-26 2005-12-27 Lsi Logic Corporation System and method of transferring data words between master and slave devices
ATE542181T1 (de) * 2004-10-28 2012-02-15 Magima Digital Information Co Ltd Arbitrierer und arbitrierungsverfahren dafür
KR100633773B1 (ko) * 2005-07-01 2006-10-13 삼성전자주식회사 버스 시스템 및 버스 중재 방법

Also Published As

Publication number Publication date
EP1811393A4 (de) 2008-01-23
WO2006024193A1 (fr) 2006-03-09
US7543093B2 (en) 2009-06-02
US20070260793A1 (en) 2007-11-08
EP1811393A1 (de) 2007-07-25
DE602004019990D1 (de) 2009-04-23
EP1811393B1 (de) 2009-03-11

Similar Documents

Publication Publication Date Title
ATE425495T1 (de) Verfahren und system zum datentransfer
HK1114213A1 (en) System-on-chip integrated circuit, electronic system and method of transferring data therein
WO2007106722A3 (en) System and method for determining a workload level of a driver
DE602007009290D1 (de) Verfahren zum aufrechterhalten eines usb-aktivzustands ohne datentransfer
ATE500698T1 (de) System und verfahren zur filterung von datentransfers in einem mobilgerät
WO2008021909A3 (en) Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem
WO2009148863A3 (en) Memory systems and methods for controlling the timing of receiving read data
SE0402573D0 (sv) Anordning vid bussförbindelse i CAN-system
GB2446997A (en) Memory access request arbitration
WO2009055103A3 (en) Low-power source-synchronous signaling
FR2972161B1 (fr) Dispositif, systeme et procede pour le partage de vehicules.
TW200609742A (en) Multiple apparatuses connection system and the method thereof
EP1793308A3 (de) Host-Gerät und denselben benutzendes Informationsverarbeitungssystem
FR2837628B3 (fr) Dispositif de commande pour prises maitre/esclave
WO2015041773A3 (en) System power management using communication bus protocols
TW200710819A (en) Data transfer control device and electronic instrument
WO2002041153A3 (en) System and method for implementing a multi-level interrupt scheme in a computer system
ATE460706T1 (de) Kommunikationssystem und -verfahren mit einer slave-einrichtung mit zwischengespeicherter service-anforderung
ATE468563T1 (de) Datenbus-interface für ein steuergerät und steuergerät mit einem datenbus-interface
SE0202372L (sv) Anordning vid distribuerat styrsystem, t ex för fordon
TW200629154A (en) Attitude insensitive flow device system and method
EP1723532A4 (de) Mehrfach-burst-protokoll-einrichtungssteuerung
TW200643797A (en) System and method for flexible multiple protocols
TW200710666A (en) System and method to reduce memory latency in microprocessor systems connected with a bus
TW200735575A (en) Method for determining connection status of wired network

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties