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ATE389948T1 - Verfahren zur herstellung einer halbleitervorrichtung - Google Patents

Verfahren zur herstellung einer halbleitervorrichtung

Info

Publication number
ATE389948T1
ATE389948T1 AT05774140T AT05774140T ATE389948T1 AT E389948 T1 ATE389948 T1 AT E389948T1 AT 05774140 T AT05774140 T AT 05774140T AT 05774140 T AT05774140 T AT 05774140T AT E389948 T1 ATE389948 T1 AT E389948T1
Authority
AT
Austria
Prior art keywords
region
gate
semiconductor body
conductivity type
opposite
Prior art date
Application number
AT05774140T
Other languages
English (en)
Inventor
Radu Surdeanu
Erwin Hijzen
T Zandt Michael In
Raymond Hueting
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE389948T1 publication Critical patent/ATE389948T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates

Landscapes

  • Thin Film Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
AT05774140T 2004-09-02 2005-08-10 Verfahren zur herstellung einer halbleitervorrichtung ATE389948T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04104206 2004-09-02

Publications (1)

Publication Number Publication Date
ATE389948T1 true ATE389948T1 (de) 2008-04-15

Family

ID=35501611

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05774140T ATE389948T1 (de) 2004-09-02 2005-08-10 Verfahren zur herstellung einer halbleitervorrichtung

Country Status (9)

Country Link
US (1) US7659169B2 (de)
EP (1) EP1790002B1 (de)
JP (1) JP2008511978A (de)
KR (1) KR20070052339A (de)
CN (1) CN100505185C (de)
AT (1) ATE389948T1 (de)
DE (1) DE602005005496T2 (de)
TW (1) TW200616097A (de)
WO (1) WO2006024979A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008526041A (ja) * 2004-12-28 2008-07-17 エヌエックスピー ビー ヴィ 半導体デバイスの製造方法およびこの方法で製造される半導体デバイス
US7923350B2 (en) 2008-09-09 2011-04-12 Infineon Technologies Ag Method of manufacturing a semiconductor device including etching to etch stop regions
US8999861B1 (en) * 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9466729B1 (en) * 2015-05-08 2016-10-11 Qualcomm Incorporated Etch stop region based fabrication of bonded semiconductor structures
US20170117417A1 (en) * 2015-07-13 2017-04-27 Board Of Regents, The University Of Texas System Integration of air-sensitive two-dimensional materials on arbitrary substrates for the manufacturing of electronic devices

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273921A (en) 1991-12-27 1993-12-28 Purdue Research Foundation Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor
TW215967B (en) 1992-01-17 1993-11-11 Seiko Electron Co Ltd MOS Poly-Si thin film transistor with a flattened channel interface and method of producing same
US5461250A (en) 1992-08-10 1995-10-24 International Business Machines Corporation SiGe thin film or SOI MOSFET and method for making the same
US5736435A (en) * 1995-07-03 1998-04-07 Motorola, Inc. Process for fabricating a fully self-aligned soi mosfet
US5773331A (en) 1996-12-17 1998-06-30 International Business Machines Corporation Method for making single and double gate field effect transistors with sidewall source-drain contacts
US20010017392A1 (en) 1997-05-19 2001-08-30 International Business Machines Corporation. Vertical transport MOSFETs and method for making the same
ATE378692T1 (de) * 2000-02-29 2007-11-15 Nxp Bv Halbleiterbauelement mit zweifachem gate und dessen herstellungsverfahren
JP3764401B2 (ja) 2002-04-18 2006-04-05 株式会社東芝 半導体装置の製造方法
US20060092695A1 (en) 2004-11-02 2006-05-04 Wing Malcolm J Hybrid memory array with single cycle access
DE102005004434A1 (de) 2005-01-31 2006-08-10 Infineon Technologies Ag Verfahren und Vorrichtung zur Ansteuerung von Festkörper-Elektrolytzellen
US7494849B2 (en) 2005-11-03 2009-02-24 Cswitch Inc. Methods for fabricating multi-terminal phase change devices

Also Published As

Publication number Publication date
CN101019216A (zh) 2007-08-15
EP1790002A1 (de) 2007-05-30
WO2006024979A1 (en) 2006-03-09
JP2008511978A (ja) 2008-04-17
TW200616097A (en) 2006-05-16
KR20070052339A (ko) 2007-05-21
CN100505185C (zh) 2009-06-24
US20080194069A1 (en) 2008-08-14
US7659169B2 (en) 2010-02-09
DE602005005496T2 (de) 2009-04-09
EP1790002B1 (de) 2008-03-19
DE602005005496D1 (de) 2008-04-30

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties