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ATE375519T1 - Verzögerungs-fehlertest-schaltkreise und diesbezügliches verfahren - Google Patents

Verzögerungs-fehlertest-schaltkreise und diesbezügliches verfahren

Info

Publication number
ATE375519T1
ATE375519T1 AT04820969T AT04820969T ATE375519T1 AT E375519 T1 ATE375519 T1 AT E375519T1 AT 04820969 T AT04820969 T AT 04820969T AT 04820969 T AT04820969 T AT 04820969T AT E375519 T1 ATE375519 T1 AT E375519T1
Authority
AT
Austria
Prior art keywords
clock pulses
threshold value
count value
clock
value reaches
Prior art date
Application number
AT04820969T
Other languages
English (en)
Inventor
Aviral Mittal
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE375519T1 publication Critical patent/ATE375519T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3016—Delay or race condition test, e.g. race hazard test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Pulse Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)
AT04820969T 2003-12-27 2004-12-17 Verzögerungs-fehlertest-schaltkreise und diesbezügliches verfahren ATE375519T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB0330076.1A GB0330076D0 (en) 2003-12-27 2003-12-27 Delay fault test circuitry and related method

Publications (1)

Publication Number Publication Date
ATE375519T1 true ATE375519T1 (de) 2007-10-15

Family

ID=31503217

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04820969T ATE375519T1 (de) 2003-12-27 2004-12-17 Verzögerungs-fehlertest-schaltkreise und diesbezügliches verfahren

Country Status (8)

Country Link
US (1) US7457992B2 (de)
EP (1) EP1702218B1 (de)
JP (1) JP2007518976A (de)
CN (1) CN1902502B (de)
AT (1) ATE375519T1 (de)
DE (1) DE602004009475T2 (de)
GB (1) GB0330076D0 (de)
WO (1) WO2005066645A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7024324B2 (en) * 2004-05-27 2006-04-04 Intel Corporation Delay element calibration
CN100366006C (zh) * 2005-12-26 2008-01-30 北京中星微电子有限公司 通用串行总线物理层收发器嵌入式自我测试的方法及装置
WO2019079116A1 (en) * 2017-10-16 2019-04-25 Microchip Technology Incorporated FOLLOWING TOLERANT CLOCK MONITOR SYSTEM
EP3799678B1 (de) * 2018-07-11 2024-09-11 Siemens Aktiengesellschaft Ausfallsicherer zählerauswerter zur sicheren zählung durch einen zähler
JP2020072549A (ja) * 2018-10-31 2020-05-07 株式会社豊田中央研究所 電源装置
US11092648B2 (en) 2019-04-15 2021-08-17 Grammatech, Inc. Systems and/or methods for anomaly detection and characterization in integrated circuits
CN112816858B (zh) * 2020-12-31 2022-09-16 成都华微电子科技股份有限公司 数字电路延时测试方法、测试电路和集成电路芯片

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5349587A (en) * 1992-03-26 1994-09-20 Northern Telecom Limited Multiple clock rate test apparatus for testing digital systems
US6081913A (en) * 1997-06-03 2000-06-27 Sun Microsystems, Inc. Method for ensuring mutual exclusivity of selected signals during application of test patterns
JP2953435B2 (ja) * 1997-06-09 1999-09-27 日本電気株式会社 遅延テスト方法および該遅延テスト方法に使用するフリップフロップ
US6966021B2 (en) * 1998-06-16 2005-11-15 Janusz Rajski Method and apparatus for at-speed testing of digital circuits
US6484294B1 (en) * 1999-04-23 2002-11-19 Hitachi, Ltd. Semiconductor integrated circuit and method of designing the same
US6510534B1 (en) * 2000-06-29 2003-01-21 Logicvision, Inc. Method and apparatus for testing high performance circuits
US6954887B2 (en) * 2001-03-22 2005-10-11 Syntest Technologies, Inc. Multiple-capture DFT system for scan-based integrated circuits
JP2003043109A (ja) * 2001-07-30 2003-02-13 Nec Corp 半導体集積回路装置及びその試験装置
GB0119300D0 (en) 2001-08-08 2001-10-03 Koninkl Philips Electronics Nv Delay fault test circuitry and related method
US7058866B2 (en) * 2002-04-24 2006-06-06 International Business Machines Corporation Method and system for an on-chip AC self-test controller

Also Published As

Publication number Publication date
JP2007518976A (ja) 2007-07-12
US20070168158A1 (en) 2007-07-19
CN1902502B (zh) 2010-06-09
GB0330076D0 (en) 2004-02-04
EP1702218B1 (de) 2007-10-10
CN1902502A (zh) 2007-01-24
EP1702218A1 (de) 2006-09-20
US7457992B2 (en) 2008-11-25
WO2005066645A1 (en) 2005-07-21
DE602004009475D1 (de) 2007-11-22
DE602004009475T2 (de) 2008-07-24

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Legal Events

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