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ATE120573T1 - Paralleles verarbeitungssystem und verfahren zu dessen anwendung. - Google Patents

Paralleles verarbeitungssystem und verfahren zu dessen anwendung.

Info

Publication number
ATE120573T1
ATE120573T1 AT87906244T AT87906244T ATE120573T1 AT E120573 T1 ATE120573 T1 AT E120573T1 AT 87906244 T AT87906244 T AT 87906244T AT 87906244 T AT87906244 T AT 87906244T AT E120573 T1 ATE120573 T1 AT E120573T1
Authority
AT
Austria
Prior art keywords
elements
registers
processing
processing system
parallel processing
Prior art date
Application number
AT87906244T
Other languages
English (en)
Inventor
Salvatore J Stolfo
Original Assignee
Univ Columbia
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25416823&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=ATE120573(T1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Univ Columbia filed Critical Univ Columbia
Application granted granted Critical
Publication of ATE120573T1 publication Critical patent/ATE120573T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Advance Control (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Communication Control (AREA)
  • Image Processing (AREA)
  • Multi-Process Working Machines And Systems (AREA)
AT87906244T 1986-09-02 1987-08-27 Paralleles verarbeitungssystem und verfahren zu dessen anwendung. ATE120573T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/903,031 US4843540A (en) 1986-09-02 1986-09-02 Parallel processing method

Publications (1)

Publication Number Publication Date
ATE120573T1 true ATE120573T1 (de) 1995-04-15

Family

ID=25416823

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87906244T ATE120573T1 (de) 1986-09-02 1987-08-27 Paralleles verarbeitungssystem und verfahren zu dessen anwendung.

Country Status (10)

Country Link
US (1) US4843540A (de)
EP (1) EP0280723B1 (de)
JP (1) JP2788727B2 (de)
KR (1) KR930006383B1 (de)
AT (1) ATE120573T1 (de)
AU (1) AU598877B2 (de)
CA (1) CA1289262C (de)
DE (1) DE3751205T2 (de)
IL (1) IL83733A (de)
WO (1) WO1988001769A1 (de)

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4985832A (en) * 1986-09-18 1991-01-15 Digital Equipment Corporation SIMD array processing system with routing networks having plurality of switching stages to transfer messages among processors
JP3039953B2 (ja) * 1989-04-28 2000-05-08 株式会社日立製作所 並列化装置
US5522083A (en) * 1989-11-17 1996-05-28 Texas Instruments Incorporated Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors
DE69132495T2 (de) * 1990-03-16 2001-06-13 Texas Instruments Inc., Dallas Verteilter Verarbeitungsspeicher
WO1991019259A1 (en) * 1990-05-30 1991-12-12 Adaptive Solutions, Inc. Distributive, digital maximization function architecture and method
IE920032A1 (en) * 1991-01-11 1992-07-15 Marconi Gec Ltd Parallel processing apparatus
JPH04248642A (ja) * 1991-01-18 1992-09-04 Kenneth W Iobst メモリ集積回路のｐｉｍチップおよびその制御方法
JP3047998B2 (ja) * 1991-02-13 2000-06-05 株式会社日立製作所 並列計算機におけるプロセッサ割り当て方法、及び装置
US5978831A (en) * 1991-03-07 1999-11-02 Lucent Technologies Inc. Synchronous multiprocessor using tasks directly proportional in size to the individual processors rates
US5410654A (en) * 1991-07-22 1995-04-25 International Business Machines Corporation Interface with address decoder for selectively generating first and second address and control signals respectively in response to received address and control signals
CA2078913A1 (en) * 1991-12-12 1993-06-13 John J. Reilly Interprocessor communication system and method for multiprocessor circuitry
CA2078912A1 (en) * 1992-01-07 1993-07-08 Robert Edward Cypher Hierarchical interconnection networks for parallel processing
JPH06208460A (ja) * 1993-01-11 1994-07-26 Hitachi Ltd マイクロプログラムメモリ制御方式
US5748780A (en) * 1994-04-07 1998-05-05 Stolfo; Salvatore J. Method and apparatus for imaging, image processing and data compression
US5848402A (en) * 1994-07-07 1998-12-08 Ai Ware, Inc. Universal system for artificial intelligence based learning, categorization, and optimization
US6061730A (en) * 1995-11-13 2000-05-09 Billings; Roger E. Methods and apparatus for communicating data in computer networks with separate packet assembly and packet broadcast channels
US6219717B1 (en) 1996-11-20 2001-04-17 Merrill Lynch & Co., Inc. Method and apparatus for implementing object transparent invocation
US5937194A (en) * 1997-03-12 1999-08-10 International Business Machines Corporation Method of, system for, and article of manufacture for providing a generic reduction object for data parallelism
US5991764A (en) * 1997-03-12 1999-11-23 International Business Machines Corporation Data structure specifying differing fan-in tree and fan-out tree computation patterns supporting a generic reduction object for data parallelism
US6237134B1 (en) 1997-03-12 2001-05-22 International Business Machines Corporation Method of, system for, and article of manufacture for providing a generic adaptor for converting from a non-future function pointer to a future function object
US5987255A (en) * 1997-03-12 1999-11-16 International Business Machines Corporation Method of, system for, and article of manufacture for providing a generic adaptor for converting from a sequential iterator to a pre-thread parallel iterator
US6000024A (en) 1997-10-15 1999-12-07 Fifth Generation Computer Corporation Parallel computing system
JP4127791B2 (ja) 2001-02-24 2008-07-30 インターナショナル・ビジネス・マシーンズ・コーポレーション コンピューティング構造のグローバル・ツリー・ネットワーク
US9330060B1 (en) * 2003-04-15 2016-05-03 Nvidia Corporation Method and device for encoding and decoding video image data
US6996470B2 (en) * 2003-08-01 2006-02-07 Moac Llc Systems and methods for geophysical imaging using amorphous computational processing
US7000048B2 (en) * 2003-12-18 2006-02-14 Intel Corporation Apparatus and method for parallel processing of network data on a single processing thread
WO2007050244A2 (en) 2005-10-27 2007-05-03 Georgia Tech Research Corporation Method and system for detecting and responding to attacking networks
US20080022079A1 (en) * 2006-07-24 2008-01-24 Archer Charles J Executing an allgather operation with an alltoallv operation in a parallel computer
US8140826B2 (en) * 2007-05-29 2012-03-20 International Business Machines Corporation Executing a gather operation on a parallel computer
US8161480B2 (en) * 2007-05-29 2012-04-17 International Business Machines Corporation Performing an allreduce operation using shared memory
US8156313B2 (en) * 2007-09-22 2012-04-10 Navosha Corporation Chained operation of functional units in integrated circuit by writing DONE/complete value and by reading as GO/start value from same memory location
US7991857B2 (en) 2008-03-24 2011-08-02 International Business Machines Corporation Broadcasting a message in a parallel computer
US8122228B2 (en) * 2008-03-24 2012-02-21 International Business Machines Corporation Broadcasting collective operation contributions throughout a parallel computer
US8422402B2 (en) 2008-04-01 2013-04-16 International Business Machines Corporation Broadcasting a message in a parallel computer
US8161268B2 (en) * 2008-05-21 2012-04-17 International Business Machines Corporation Performing an allreduce operation on a plurality of compute nodes of a parallel computer
US8375197B2 (en) * 2008-05-21 2013-02-12 International Business Machines Corporation Performing an allreduce operation on a plurality of compute nodes of a parallel computer
US8484440B2 (en) 2008-05-21 2013-07-09 International Business Machines Corporation Performing an allreduce operation on a plurality of compute nodes of a parallel computer
US8281053B2 (en) * 2008-07-21 2012-10-02 International Business Machines Corporation Performing an all-to-all data exchange on a plurality of data buffers by performing swap operations
US10027688B2 (en) * 2008-08-11 2018-07-17 Damballa, Inc. Method and system for detecting malicious and/or botnet-related domain names
JP4996654B2 (ja) * 2009-08-18 2012-08-08 株式会社東芝 プロセッサ
US8578497B2 (en) 2010-01-06 2013-11-05 Damballa, Inc. Method and system for detecting malware
US8826438B2 (en) 2010-01-19 2014-09-02 Damballa, Inc. Method and system for network-based detecting of malware from behavioral clustering
US8565089B2 (en) * 2010-03-29 2013-10-22 International Business Machines Corporation Performing a scatterv operation on a hierarchical tree network optimized for collective operations
US8332460B2 (en) 2010-04-14 2012-12-11 International Business Machines Corporation Performing a local reduction operation on a parallel computer
US9424087B2 (en) 2010-04-29 2016-08-23 International Business Machines Corporation Optimizing collective operations
US8346883B2 (en) 2010-05-19 2013-01-01 International Business Machines Corporation Effecting hardware acceleration of broadcast operations in a parallel computer
US8949577B2 (en) 2010-05-28 2015-02-03 International Business Machines Corporation Performing a deterministic reduction operation in a parallel computer
US8489859B2 (en) 2010-05-28 2013-07-16 International Business Machines Corporation Performing a deterministic reduction operation in a compute node organized into a branched tree topology
US9516058B2 (en) 2010-08-10 2016-12-06 Damballa, Inc. Method and system for determining whether domain names are legitimate or malicious
US8776081B2 (en) 2010-09-14 2014-07-08 International Business Machines Corporation Send-side matching of data communications messages
US8566841B2 (en) 2010-11-10 2013-10-22 International Business Machines Corporation Processing communications events in parallel active messaging interface by awakening thread from wait state
US8631489B2 (en) 2011-02-01 2014-01-14 Damballa, Inc. Method and system for detecting malicious domain names at an upper DNS hierarchy
US8893083B2 (en) 2011-08-09 2014-11-18 International Business Machines Coporation Collective operation protocol selection in a parallel computer
US8910178B2 (en) 2011-08-10 2014-12-09 International Business Machines Corporation Performing a global barrier operation in a parallel computer
US10474625B2 (en) * 2012-01-17 2019-11-12 International Business Machines Corporation Configuring compute nodes in a parallel computer using remote direct memory access (‘RDMA’)
US9495135B2 (en) 2012-02-09 2016-11-15 International Business Machines Corporation Developing collective operations for a parallel computer
US10547674B2 (en) 2012-08-27 2020-01-28 Help/Systems, Llc Methods and systems for network flow analysis
US10084806B2 (en) 2012-08-31 2018-09-25 Damballa, Inc. Traffic simulation to identify malicious activity
US9894088B2 (en) 2012-08-31 2018-02-13 Damballa, Inc. Data mining to identify malicious activity
US9166994B2 (en) 2012-08-31 2015-10-20 Damballa, Inc. Automation discovery to identify malicious activity
US9680861B2 (en) 2012-08-31 2017-06-13 Damballa, Inc. Historical analysis to identify malicious activity
US9571511B2 (en) 2013-06-14 2017-02-14 Damballa, Inc. Systems and methods for traffic classification
US9930065B2 (en) 2015-03-25 2018-03-27 University Of Georgia Research Foundation, Inc. Measuring, categorizing, and/or mitigating malware distribution paths
WO2024230937A1 (en) * 2023-05-11 2024-11-14 Abaxor Engineering Gmbh Multiple instruction multiple data processing unit

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4101960A (en) * 1977-03-29 1978-07-18 Burroughs Corporation Scientific processor
US4251861A (en) * 1978-10-27 1981-02-17 Mago Gyula A Cellular network of processors
US4435758A (en) * 1980-03-10 1984-03-06 International Business Machines Corporation Method for conditional branch execution in SIMD vector processors
US4344134A (en) * 1980-06-30 1982-08-10 Burroughs Corporation Partitionable parallel processor
JPS5723166A (en) * 1980-07-17 1982-02-06 Fujitsu Ltd Parallel data processing system driven by tree structure data
US4445171A (en) * 1981-04-01 1984-04-24 Teradata Corporation Data processing systems and methods
US4412285A (en) * 1981-04-01 1983-10-25 Teradata Corporation Multiprocessor intercommunication system and method
US4583164A (en) * 1981-08-19 1986-04-15 Tolle Donald M Syntactically self-structuring cellular computer
JPS58105370A (ja) * 1981-12-17 1983-06-23 Fujitsu Ltd デ−タ処理システム
US4622632A (en) * 1982-08-18 1986-11-11 Board Of Regents, University Of Washington Data processing system having a pyramidal array of processors
US4620276A (en) * 1983-06-02 1986-10-28 International Business Machines Corporation Method and apparatus for asynchronous processing of dynamic replication messages
US4591980A (en) * 1984-02-16 1986-05-27 Xerox Corporation Adaptive self-repairing processor array
US4860201A (en) * 1986-09-02 1989-08-22 The Trustees Of Columbia University In The City Of New York Binary tree parallel processor

Also Published As

Publication number Publication date
EP0280723A4 (de) 1990-02-22
WO1988001769A1 (en) 1988-03-10
AU7969387A (en) 1988-03-24
DE3751205D1 (de) 1995-05-04
EP0280723B1 (de) 1995-03-29
JPH01501180A (ja) 1989-04-20
CA1289262C (en) 1991-09-17
AU598877B2 (en) 1990-07-05
KR930006383B1 (ko) 1993-07-14
KR880701914A (ko) 1988-11-07
IL83733A0 (en) 1988-02-29
US4843540A (en) 1989-06-27
DE3751205T2 (de) 1995-11-09
EP0280723A1 (de) 1988-09-07
JP2788727B2 (ja) 1998-08-20
IL83733A (en) 1991-06-10

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee