Abstract
In Nano scale technology, Network on Chip (NoC) is recommended as a solution for increasing communication difficulties of System-on-Chip (SoC) design. Network-on-Chip (NoC) has better reliability and scalability compared to on-chip interconnects. An important phase in the NoC design with mesh based topologies requires core mapping for a given application. This paper proposes an energy efficient mapping algorithm (EMAP) that maps the cores onto the NoC under communication rate constraints to minimize the total communication energy. The EMAP algorithm has been applied and calculated for randomly generated benchmarks. Experimental results demonstrate that the EMAP algorithm can deal with large number of task graphs and significant saving communication energy when compared to existing algorithm. The proposed EMAP algorithm was simulated and verified on Kintex-7 (KC705) FPGA board. Which reduces hardware utilization and power consumption compared to existing mapping algorithms.
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Reddy, B.N.K., Sireesha (2019). An Energy-Efficient Core Mapping Algorithm on Network on Chip (NoC). In: Rajaram, S., Balamurugan, N., Gracia Nirmala Rani, D., Singh, V. (eds) VLSI Design and Test. VDAT 2018. Communications in Computer and Information Science, vol 892. Springer, Singapore. https://doi.org/10.1007/978-981-13-5950-7_52
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DOI: https://doi.org/10.1007/978-981-13-5950-7_52
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