Le systeme typique de verification de programmes accepte en entree un programme annote avec des assertions a la floyd-hoare et genere en sortie une liste de conditions de verification. Malheureusement, le systeme ne peut pas relier un... more
Le systeme typique de verification de programmes accepte en entree un programme annote avec des assertions a la floyd-hoare et genere en sortie une liste de conditions de verification. Malheureusement, le systeme ne peut pas relier un echec dans la preuve d'une condition a une position dans le programme ou dans les assertions. Nous apportons une reponse a ce probleme en proposant l'integration de plusieurs facilites dans un systeme de verification. Le tracage des origines a pour role d'annoter les conditions generees avec leurs origines dans le programme source. Il repose sur une instrumentation du generateur de conditions avec un calcul d'origines. L'instrumentation est systematique etant dirigee par la forme syntaxique des regles. Nous prouvons la correction du generateur instrumente et que sa complexite est un facteur constant de celle du generateur initial. Une implantation de cette technique a ete realisee dans le systeme centaur. Les coupes de programme peu...
The work presented in this paper addresses the challenge of fully verifying complextemporal properties on large RTL designs. Windowed induction has been proposedby Sheeran, Singh, and Stalmarck as a technique augmenting Bounded... more
The work presented in this paper addresses the challenge of fully verifying complextemporal properties on large RTL designs. Windowed induction has been proposedby Sheeran, Singh, and Stalmarck as a technique augmenting Bounded ModelChecking for unbounded verication of safety properties. While induction proved tobe quite eective for combinational properties, the case of temporal properties wasnot handled by previously known methods. We introduce explicit induction, a newinduction scheme targeted to temporal properties, ...
ABSTRACT Clock gating has become a standard practice for saving dynamic power in the clock network. Due to design reuse, it is common to find designs that have already some partial clock gating. We propose to exploit the existing clock... more
ABSTRACT Clock gating has become a standard practice for saving dynamic power in the clock network. Due to design reuse, it is common to find designs that have already some partial clock gating. We propose to exploit the existing clock gating in order to extract stronger gating ...
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Briefly, a system and a method of formal verification and failure analysis and rectification of models or designs, eg, VLSI designs, of processors, circuits and logical systems. Embodiments of the system may include a multi-value... more
Briefly, a system and a method of formal verification and failure analysis and rectification of models or designs, eg, VLSI designs, of processors, circuits and logical systems. Embodiments of the system may include a multi-value annotation scheme for annotating different types of values of signals, and a post-annotation scheme for further analysis based on the annotated values. Some embodiments of the invention may optionally include a generator of counter-examples of a given length.
RTL assertions play an increasing role in the validation process. The high capacity and usability of Bounded Model Checking (BMC) make it especially attractive for the verification of such assertions. However, BMC is usually used to check... more
RTL assertions play an increasing role in the validation process. The high capacity and usability of Bounded Model Checking (BMC) make it especially attractive for the verification of such assertions. However, BMC is usually used to check a single property for a given bound, while here we are dealing with hundreds of properties each one requiring a different bound. We
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ABSTRACT Clock gating has become a standard practice for saving dynamic power in the clock network. Due to design reuse, it is common to find designs that have already some partial clock gating. We propose to exploit the existing clock... more
ABSTRACT Clock gating has become a standard practice for saving dynamic power in the clock network. Due to design reuse, it is common to find designs that have already some partial clock gating. We propose to exploit the existing clock gating in order to extract stronger gating ...
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Our experience with semi-exhaustive verification shows a severe degradation in usability for the corner-case bugs, where the tuning effort becomes much higher and recovery from dead-ends is more and more difficult. Moreover, when there... more
Our experience with semi-exhaustive verification shows a severe degradation in usability for the corner-case bugs, where the tuning effort becomes much higher and recovery from dead-ends is more and more difficult. Moreover, when there are no bugs at all, shifting semi-exhaustive traversal to exhaustive traversal is very expensive, if not impossible. This makes the output of semi-exhaustive verification on non-buggy designs very ambiguous. Furthermore, since after the design fixes each falsification task needs to converge to full ...
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The work presented in this paper addresses the challenge of fully verifying complextemporal properties on large RTL designs. Windowed induction has been proposedby Sheeran, Singh, and Stalmarck as a technique augmenting Bounded... more
The work presented in this paper addresses the challenge of fully verifying complextemporal properties on large RTL designs. Windowed induction has been proposedby Sheeran, Singh, and Stalmarck as a technique augmenting Bounded ModelChecking for unbounded verication of safety properties. While induction proved tobe quite eective for combinational properties, the case of temporal properties wasnot handled by previously known methods. We introduce explicit induction, a newinduction scheme targeted to temporal properties, ...