2012 13th International Conference on Parallel and Distributed Computing, Applications and Technologies, 2012
ABSTRACT Most modern scientific research requires significant advanced modeling, simulation, and ... more ABSTRACT Most modern scientific research requires significant advanced modeling, simulation, and visualization. Due to the growing complexity of physical models, these research activities increasingly are requiring more and more High Performance Computing (HPC) resources and this trend is predicted to grow even stronger. Considering this growth in HPC applications, the traditional parallel computing model based solely on Central Processing Units (CPUs) is unable to meet the scientific needs of the researchers. HPC requirements are expected to reach exascale in this decade. There are several approaches to enhance and speed up HPC, some of the most promising involve hybrid solutions. In this paper, we describe existing state of hardware and accelerators for HPC. Such components include CPUs, Graphics Processing Units (GPU), and Field-Programmable Gate Arrays (FPGAs). Various hybrid implementations of these accelerators are presented and compared. Examples of the top supercomputers are included as well, together with their hardware configurations. Concluding this paper, we discuss our prediction of further HPC hardware trends in support of advanced modeling, simulation, and visualization.
2011 21st International Conference on Systems Engineering, 2011
ABSTRACT This paper is dedicated to two seemingly different problems. The first one concerns info... more ABSTRACT This paper is dedicated to two seemingly different problems. The first one concerns information theory and the second one is connected to logic synthesis methods. The reason why these issues are considered together is the important task of the efficient representation of data in information systems and as well as in logic systems. An efficient algorithm to solve the task of attributes/arguments reduction is presented. Keywords-machine learning, knowledge representation, dis- cernibility function, logic minimization, attribute reduction, complement
2008 19th International Conference on Systems Engineering, 2008
Recent technological developments have shown huge advances in semi-conductor based System on Chip... more Recent technological developments have shown huge advances in semi-conductor based System on Chip (SoC). However, limitations of such technology has quickly become an obstacle for the fast and highly demanding development of general or application specific SoCs. Since research in semi-conductor devices has reached its saturation, researchers look for alternative solutions. Optical technology is emerging as the leader due to its very high bandwidth capabilities (the main constraint of semi-conductor technology). In this paper, we analyze the most recent developments for optical Network on Chip (NoC) as a basic architecture for SoC. Packet switching remains most popular due to scalability and reliability issues, as well as due to variety of applications it is designed for. While optical switching technologies promise high speed interconnection, buffering technologies havenpsilat matured enough to support fully optical packet switching NoCs. What is the current state and what are the expectations from the optical/photonics technologies? The paper tries to study these issues and provide an answer.
Advances in Intelligent Systems and Computing, 2014
ABSTRACT Multiphysics systems are used to simulate various physics phenomena given by Partial Dif... more ABSTRACT Multiphysics systems are used to simulate various physics phenomena given by Partial Differential Equations (PDEs). The most popular method of solving PDEs is Finite Element method. The simulations require large amount of computational power, that is mostly caused by extensive processing of matrices. The high computational requirements have led recently to parallelization of algorithms and to utilization of Graphic Processing Units (GPUs). To take advantage of GPUs, one of GPU programming models has to be used. In this paper, CUDA model developed by nVidia is used to implement two parallel matrix multiplication algorithms. To evaluate the effectiveness of these algorithms, several experiments have been performed. Results have been compared with results obtained by classic Central Processing Unit (CPU) matrix multiplication algorithm. The comparison shows that matrix multiplication on GPU significantly outperforms classic CPU approach.
International Journal of Electronics and Telecommunications, 2012
ABSTRACT This paper concerns Directed Acyclic Graph task scheduling on parallel executors. The pr... more ABSTRACT This paper concerns Directed Acyclic Graph task scheduling on parallel executors. The problem is solved using two new implementations of Tabu Search and genetic algorithm presented in the paper. A new approach to solution coding is also introduced and implemented in both metaheuristics algorithms. Results given by the algorithms are compared to those generated by greedy LPT and SS-FF algorithms; and HAR algorithm. The analysis of the obtained results of multistage simulation experiments confirms the conclusion that the proposed and implemented algorithms are characterized by very good performance and characteristics.
Well-designed Processor Allocator (PA) is an important factor in modern Chip MultiProcessors (CMP... more Well-designed Processor Allocator (PA) is an important factor in modern Chip MultiProcessors (CMPs). It needs to be fast as well as area and energy efficient, because it is only a small component of the CMP. In this paper, we propose an architecture for such an efficient and fast PA. The PA structure is based on bit map approach and is
2012 13th International Conference on Parallel and Distributed Computing, Applications and Technologies, 2012
ABSTRACT Most modern scientific research requires significant advanced modeling, simulation, and ... more ABSTRACT Most modern scientific research requires significant advanced modeling, simulation, and visualization. Due to the growing complexity of physical models, these research activities increasingly are requiring more and more High Performance Computing (HPC) resources and this trend is predicted to grow even stronger. Considering this growth in HPC applications, the traditional parallel computing model based solely on Central Processing Units (CPUs) is unable to meet the scientific needs of the researchers. HPC requirements are expected to reach exascale in this decade. There are several approaches to enhance and speed up HPC, some of the most promising involve hybrid solutions. In this paper, we describe existing state of hardware and accelerators for HPC. Such components include CPUs, Graphics Processing Units (GPU), and Field-Programmable Gate Arrays (FPGAs). Various hybrid implementations of these accelerators are presented and compared. Examples of the top supercomputers are included as well, together with their hardware configurations. Concluding this paper, we discuss our prediction of further HPC hardware trends in support of advanced modeling, simulation, and visualization.
2011 21st International Conference on Systems Engineering, 2011
ABSTRACT This paper is dedicated to two seemingly different problems. The first one concerns info... more ABSTRACT This paper is dedicated to two seemingly different problems. The first one concerns information theory and the second one is connected to logic synthesis methods. The reason why these issues are considered together is the important task of the efficient representation of data in information systems and as well as in logic systems. An efficient algorithm to solve the task of attributes/arguments reduction is presented. Keywords-machine learning, knowledge representation, dis- cernibility function, logic minimization, attribute reduction, complement
2008 19th International Conference on Systems Engineering, 2008
Recent technological developments have shown huge advances in semi-conductor based System on Chip... more Recent technological developments have shown huge advances in semi-conductor based System on Chip (SoC). However, limitations of such technology has quickly become an obstacle for the fast and highly demanding development of general or application specific SoCs. Since research in semi-conductor devices has reached its saturation, researchers look for alternative solutions. Optical technology is emerging as the leader due to its very high bandwidth capabilities (the main constraint of semi-conductor technology). In this paper, we analyze the most recent developments for optical Network on Chip (NoC) as a basic architecture for SoC. Packet switching remains most popular due to scalability and reliability issues, as well as due to variety of applications it is designed for. While optical switching technologies promise high speed interconnection, buffering technologies havenpsilat matured enough to support fully optical packet switching NoCs. What is the current state and what are the expectations from the optical/photonics technologies? The paper tries to study these issues and provide an answer.
Advances in Intelligent Systems and Computing, 2014
ABSTRACT Multiphysics systems are used to simulate various physics phenomena given by Partial Dif... more ABSTRACT Multiphysics systems are used to simulate various physics phenomena given by Partial Differential Equations (PDEs). The most popular method of solving PDEs is Finite Element method. The simulations require large amount of computational power, that is mostly caused by extensive processing of matrices. The high computational requirements have led recently to parallelization of algorithms and to utilization of Graphic Processing Units (GPUs). To take advantage of GPUs, one of GPU programming models has to be used. In this paper, CUDA model developed by nVidia is used to implement two parallel matrix multiplication algorithms. To evaluate the effectiveness of these algorithms, several experiments have been performed. Results have been compared with results obtained by classic Central Processing Unit (CPU) matrix multiplication algorithm. The comparison shows that matrix multiplication on GPU significantly outperforms classic CPU approach.
International Journal of Electronics and Telecommunications, 2012
ABSTRACT This paper concerns Directed Acyclic Graph task scheduling on parallel executors. The pr... more ABSTRACT This paper concerns Directed Acyclic Graph task scheduling on parallel executors. The problem is solved using two new implementations of Tabu Search and genetic algorithm presented in the paper. A new approach to solution coding is also introduced and implemented in both metaheuristics algorithms. Results given by the algorithms are compared to those generated by greedy LPT and SS-FF algorithms; and HAR algorithm. The analysis of the obtained results of multistage simulation experiments confirms the conclusion that the proposed and implemented algorithms are characterized by very good performance and characteristics.
Well-designed Processor Allocator (PA) is an important factor in modern Chip MultiProcessors (CMP... more Well-designed Processor Allocator (PA) is an important factor in modern Chip MultiProcessors (CMPs). It needs to be fast as well as area and energy efficient, because it is only a small component of the CMP. In this paper, we propose an architecture for such an efficient and fast PA. The PA structure is based on bit map approach and is
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