The multiplier circuit is an important component in digital signal processing. The increasing cos... more The multiplier circuit is an important component in digital signal processing. The increasing cost of silicon technology has put a lot of pressure on developing dedicated SoC solutions for DSP systems and has typically cornered such solutions to high volume productions only. Recently, FPGAs have been used as an alternative platform for DSP systems as they have the ability to develop suitable circuit architecture in a way similar to SoC systems. Whilst the prefabricated aspects of FPGAs avoid many architectural problems, the ability to create an efficient implementation from a DSP system description, still remains a highly convoluted problem. This has prompted different FPGA vendors to improve the capacity and flexibility of the underlying fabric by including specialized primitive, macro and IP support. In this paper we carry out the implementation of fixed-point multiplier circuit by using these primitives and macro support. Our implementation results indicate reduction in resource ...
Modern day field programmable gate arrays (FPGAs) have very huge and versatile logic resources re... more Modern day field programmable gate arrays (FPGAs) have very huge and versatile logic resources resulting in the migration of their application domain from prototype designing to low and medium volume production designing. Unfortunately most of the work pertaining to FPGA implementations does not focus on the technology dependent optimizations that can implement a desired functionality with reduced cost. In this paper we consider the mapping of simple ripple carry fixed-point adders (RCA) on look-up table (LUT) based FPGAs. The objective is to transform the given RCA Boolean network into an optimized circuit netlist that can implement the desired functionality with minimum cost. We particularly focus on 6-input LUTs that are inherent in all the modern day FPGAs. Technology dependent optimizations are carried out to utilize this FPGA primitive efficiently and the result is compared against various adder designs. The implementation targets the XC5VLX30-3FF324 device from Xilinx Virtex-...
The multiplier circuit is an important component in digital signal processing. The increasing cos... more The multiplier circuit is an important component in digital signal processing. The increasing cost of silicon technology has put a lot of pressure on developing dedicated SoC solutions for DSP systems and has typically cornered such solutions to high volume productions only. Recently, FPGAs have been used as an alternative platform for DSP systems as they have the ability to develop suitable circuit architecture in a way similar to SoC systems. Whilst the prefabricated aspects of FPGAs avoid many architectural problems, the ability to create an efficient implementation from a DSP system description, still remains a highly convoluted problem. This has prompted different FPGA vendors to improve the capacity and flexibility of the underlying fabric by including specialized primitive, macro and IP support. In this paper we carry out the implementation of fixed-point multiplier circuit by using these primitives and macro support. Our implementation results indicate reduction in resource ...
Fixed-point multiplication is frequently used in many DSP algorithms. This paper considers the de... more Fixed-point multiplication is frequently used in many DSP algorithms. This paper considers the design of a constant word-length bit-parallel fixed-point multiplier based on CORDIC algorithm. Traditional bit-parallel multipliers are designed using ripple-carry or carry-save logic. A comparative analysis of our implementation results against three widely used constant word-length bit-parallel fixed-point multipliers viz. ripple carry array multiplier, carry-save array multiplier and Bough-Wooley multiplier is presented in this paper. The comparison is made with respect to resource utilization, timing and power dissipation. The implementation is carried out for varying input word-lengths ranging from 4 to 32-bit parallel operands. Further, the implementation targets three different FPGA families viz. Spartan-6, Virtex-4, and Virtex-5. Our implementation achieves a reduction in resource usage by at least 30 %; increase in speed by at least 5 % and reduction in dynamic power dissipation ...
In this paper we present an efficient FPGA implementation of common CORDIC architecture for circu... more In this paper we present an efficient FPGA implementation of common CORDIC architecture for circular coordinates. CORDIC is one of the most versatile algorithms available for developing high-performance computing hardware. It is a multiplier-less approach and involves only shift and add operations. Since fixed-point arithmetic is efficiently realizable on FPGAs, CORDIC algorithm is very apt for implementation on FPGAs. Unfortunately, majority of the published work related to FPGA implementation of CORDIC algorithm has focused only on technology independent (architectural) modification. However, in this paper we consider the technology dependent optimization of CORDIC architectures that can implement a desired functionality with reduced cost. We particularly focus on 4-input LUTs that are inherent basic logic elements in Virtex-4 FPGAs. Technology dependent optimizations are carried out to utilize this FPGA primitive efficiently. The cost of the circuit is expressed in terms of the r...
The multiplier circuit is an important component in digital signal processing. The increasing cos... more The multiplier circuit is an important component in digital signal processing. The increasing cost of silicon technology has put a lot of pressure on developing dedicated SoC solutions for DSP systems and has typically cornered such solutions to high volume productions only. Recently, FPGAs have been used as an alternative platform for DSP systems as they have the ability to develop suitable circuit architecture in a way similar to SoC systems. Whilst the prefabricated aspects of FPGAs avoid many architectural problems, the ability to create an efficient implementation from a DSP system description, still remains a highly convoluted problem. This has prompted different FPGA vendors to improve the capacity and flexibility of the underlying fabric by including specialized primitive, macro and IP support. In this paper we carry out the implementation of fixed-point multiplier circuit by using these primitives and macro support. Our implementation results indicate reduction in resource ...
Modern day field programmable gate arrays (FPGAs) have very huge and versatile logic resources re... more Modern day field programmable gate arrays (FPGAs) have very huge and versatile logic resources resulting in the migration of their application domain from prototype designing to low and medium volume production designing. Unfortunately most of the work pertaining to FPGA implementations does not focus on the technology dependent optimizations that can implement a desired functionality with reduced cost. In this paper we consider the mapping of simple ripple carry fixed-point adders (RCA) on look-up table (LUT) based FPGAs. The objective is to transform the given RCA Boolean network into an optimized circuit netlist that can implement the desired functionality with minimum cost. We particularly focus on 6-input LUTs that are inherent in all the modern day FPGAs. Technology dependent optimizations are carried out to utilize this FPGA primitive efficiently and the result is compared against various adder designs. The implementation targets the XC5VLX30-3FF324 device from Xilinx Virtex-...
The multiplier circuit is an important component in digital signal processing. The increasing cos... more The multiplier circuit is an important component in digital signal processing. The increasing cost of silicon technology has put a lot of pressure on developing dedicated SoC solutions for DSP systems and has typically cornered such solutions to high volume productions only. Recently, FPGAs have been used as an alternative platform for DSP systems as they have the ability to develop suitable circuit architecture in a way similar to SoC systems. Whilst the prefabricated aspects of FPGAs avoid many architectural problems, the ability to create an efficient implementation from a DSP system description, still remains a highly convoluted problem. This has prompted different FPGA vendors to improve the capacity and flexibility of the underlying fabric by including specialized primitive, macro and IP support. In this paper we carry out the implementation of fixed-point multiplier circuit by using these primitives and macro support. Our implementation results indicate reduction in resource ...
Fixed-point multiplication is frequently used in many DSP algorithms. This paper considers the de... more Fixed-point multiplication is frequently used in many DSP algorithms. This paper considers the design of a constant word-length bit-parallel fixed-point multiplier based on CORDIC algorithm. Traditional bit-parallel multipliers are designed using ripple-carry or carry-save logic. A comparative analysis of our implementation results against three widely used constant word-length bit-parallel fixed-point multipliers viz. ripple carry array multiplier, carry-save array multiplier and Bough-Wooley multiplier is presented in this paper. The comparison is made with respect to resource utilization, timing and power dissipation. The implementation is carried out for varying input word-lengths ranging from 4 to 32-bit parallel operands. Further, the implementation targets three different FPGA families viz. Spartan-6, Virtex-4, and Virtex-5. Our implementation achieves a reduction in resource usage by at least 30 %; increase in speed by at least 5 % and reduction in dynamic power dissipation ...
In this paper we present an efficient FPGA implementation of common CORDIC architecture for circu... more In this paper we present an efficient FPGA implementation of common CORDIC architecture for circular coordinates. CORDIC is one of the most versatile algorithms available for developing high-performance computing hardware. It is a multiplier-less approach and involves only shift and add operations. Since fixed-point arithmetic is efficiently realizable on FPGAs, CORDIC algorithm is very apt for implementation on FPGAs. Unfortunately, majority of the published work related to FPGA implementation of CORDIC algorithm has focused only on technology independent (architectural) modification. However, in this paper we consider the technology dependent optimization of CORDIC architectures that can implement a desired functionality with reduced cost. We particularly focus on 4-input LUTs that are inherent basic logic elements in Virtex-4 FPGAs. Technology dependent optimizations are carried out to utilize this FPGA primitive efficiently. The cost of the circuit is expressed in terms of the r...
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