"RTL Design and Verification Engineer"
I am an RTL design and Verification engineer with a strong background in Computer Architecture and Digital Logic Design.
- SystemVerilog, Verilog, CHISEL
- Universal Verification Methodology (UVM)
- RISC-V Assembly
- C / C++
- Python, Bash, tcl
- Functional coverage collection
- Random Instruction Sequence Generation
- Unit level Testing / VIP in UVM
- Reusing existing IPs / integration
- Xcelium, Questa Sim, Vivado (xsim), Verilator, iCarus Verilog, GTK wave
- Vivado (synthesis and implementation), AWS Cloud FPGA
- Genus, Yosys