A little tutorial on how to use UVVM (Universal VHDL Verification Methodology).
This tutorial was developed as part of the course "Practical FPGA Applications", in the masters program "Embedded Systems Design" at the University of Applied Sciences Upper Austria, Campus Hagenberg.
<-- FH OOE, Masters Program ESD
Please follow the main tutorial document.
There is also a presentation available, that shows some additional block diagrams to get an overview of the UVVM verification environment.
Michael Wurm <wurm.michael95@gmail.com>
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