8000 Adding Number of Logic levels and number of timing graph levels to ti… by behnam-rs · Pull Request #2383 · verilog-to-routing/vtr-verilog-to-routing · GitHub
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…ming setup and hold reports

Description

Adding Number of Logic levels and number of timing graph levels to timing setup and hold reports

Related Issue

Motivation and Context

How Has This Been Tested?

We have tested via some manual small design.

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool external_libs labels Aug 31, 2023
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