Pulse · verilator/verilator · GitHub

8000 Pulse · verilator/verilator · GitHub

July 25, 2025 – July 26, 2025

Overview

1 Active pull request 5AE6

4 Active issues
- 1 Merged pull request
- 0 Open pull requests
- 3 Closed issues
- 1 New issue

1 Pull request merged by 1 person

Support Verilog real ports as SystemC double ports (#6136)
#6158 merged Jul 25, 2025

3 Issues closed by 1 person

Improve --skip-identical to look for input files with identical hashes
#6109 closed Jul 26, 2025
Verilog real ports are converted to uint64_t sc_signals when verilating to SystemC
#6136 closed Jul 25, 2025
Incorrect handling of `x` in if blocks (`if (x) else` ) ?
#6199 closed Jul 25, 2025

1 Issue opened by 1 person

V3DfgDfgToAst.cpp:48: Incorrect width in AstNode created from DfgVertex REPLICATE: 1 vs 8
#6231 opened Jul 26, 2025

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