-
Notifications
You must be signed in to change notification settings - Fork 670
Incorrect Optimization Causes Mismatched Output in Verilator #6007
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Comments
It looks Line 1880 in 6b42d78
should be for (uint64_t bit = 0; bit < width(); ++bit) { |
@sdjasj mind attempting a second pull with @yTakatsukasa (thanks) suggestion please? |
No problem, I'm happy to help :) and thank you @yTakatsukasa for your fix suggestion. |
Line 1881 in 6b42d78
Ah I also think static_cast in this line is not necessary if bit is uint64_t .
I'm not sure whether an obvious shortcut of |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Uh oh!
There was an error while loading. Please reload this page.
The following is the problematic code
test.v
.You can reproduce the issue with the following commands:
Verilator output:
However, Icarus Verilog completes successfully with
*-* All Finished *-*
. Moreover, examining the expression shows that the result should also be 0.System details:
The text was updated successfully, but these errors were encountered: