Hardware and Software Co-design implementations

HLS SHA-3 Accelerator

Deep Learning Processing Unit (DPU IP) integration with Application Processing Unit (APU) using (Zynq-7000 PS) in Xilinx Vivado Design Suite

Driving 32BY16 RGB Panel using ZYNQ SoC

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Usese the zybo and nexys 4 ddr to play a game of breakout.

Vivado test IP for Hermes NoC Router

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

The ZyboZ7's Zynq-7000 processor polls data from an ADC through I2C. The captured data is then sent to a Sparkfun 7-Segment via SPI. Other information is sent to an LCD (with a custom IP LCD driver) that interfaces with the Zynq-7000.