pipelined-processors

Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-mapped L1 Data Cache, and a 4-way set-associative L2 Victim Cache with a fully-associative 8-entry Victim Buffer. Also has a tournament branch predictor (global and local predictors) and a set-associative BTB.

cache riscv32 victim-cache pipelined-processors set-associative-cache pipelined-risc

Updated Dec 23, 2022
Verilog

EmanOthman21 / MIPS-Pipelined-Processor

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This is a MIPS 5 stage 32-bit pipelined processor with Harvard architecture, which comes with an assembler to interpret instructions to supported OP codes.

mips vhdl assembler computer-architecture mips-architecture pipelined-processors

Updated Aug 12, 2021
VHDL

Sanskar777 / Dynamic-branch-predictor-in-pipelined-processors

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verilog-hdl branch-predictor pipelined-processors

Updated Nov 18, 2019
Verilog

fardinabbasi / RISC-V_Processor_Pipelined

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Design and implementation of RISC-V processor with a pipelined datapath, controller, and hazard unit.

verilog computer-architecture modelsim risc-v digital-systems computer-arithmetic pipelined-processors

Updated Aug 13, 2024
Verilog

abdullahalshawafi / RISC-Processor

Star

A simple 5-stage pipelined processor following Harvard's architecture. The processor has RISC-like ISA. There are eight 2-byte general-purpose registers, and another three special-purpose registers (Program Counter, Exception Program Counter, Stack Pointer). The memory address space is 1 MB of 16-bit width and is word addressable.

processor vhdl computer-architecture pipelined-processors

Updated Jan 10, 2022
VHDL

naderabdalghani / 32-bit-risc-pipelined-processor

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Implementation of a simple 5-stage 32-bit pipelined processor and its assembler using VHDL and Python

hardware 32-bit cpu-design assembler-implementation pipelined-processors

Updated Apr 26, 2021
VHDL

Elzawawy / mips-processor-simulator

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A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.

mips mips-architecture mips-simulator pipelined-processors single-cycle-processor multi-cycle-processor

Updated Aug 31, 2020
SystemVerilog

akankshac-073 / MIPS-5-stage-pipelined-control-and-datapath

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Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding cont…

verilog computer-architecture mips-architecture mips-processor mips32 pipelined-processors mips-pipline-processor-verilog

Updated Mar 22, 2022
Verilog

helcsnewsxd / famaf-computer_science-computer_architecture

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Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

processor-architecture optimization labs theory computer-architecture system-verilog armv8 quartus hardware-description-language pipelined-processors university-subjects famaf-unc

Updated Jul 24, 2024
SystemVerilog

abdulkhan94 / Computer-Design-and-Prototyping

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MIPS 32 bit processor - fully functional shared memory dual-core processor with MSI for cache coherency

multicore pipelined-processors cache-coherency

Updated Jun 1, 2017
SystemVerilog

AbdelrahmanHamdyy / RISC-Pipelined-Processor

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5 stages RISC pipelined processor with multiple instructions implemented in verilog including ALU Operations, Interrupts as a state machine, Jumps and branching instructions, Memory operations and more.. following Harvard architecture.

memory assembler verilog systemverilog computer-architecture interrupts hazards pipelined-processors alu-digital-circuit

Updated Jan 7, 2023
SystemVerilog

MaheenAnees / Single-Cycle-RISCV-Processor

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This repository is created to build a single cycle processor and converting it to a 5-stage pipelined processor capable of executing a bubble sort program.

verilog computer-architecture risc-v pipelined-processors single-cycle-processor