RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
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Updated
Nov 14, 2018 - SystemVerilog
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
GSoC Accepted Proposals for the year 2015 to 2020
This is Malayalam Speech Recognition model developed for CMUSphinx. This is now used for Google Summer Code 2016
Parallella RISC-V Prebuilt Images
Notes and Implementation Roadmap for ServiceWorkers GSoC'16 Project
Personal Repository for my GNOME Logs GSoC project.
Google Summer of Code - This is a showcase demonstrating how the istsos-java-core library can be used to build android applications.
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