A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

Verilog Implementation of an ARM LEGv8 CPU

Final Project of the Computer Architecture (ICOM4215) course, Spring 2023. The project documents the journey of three students learning the basics of the vast world of FPGAs and hardware design in general. Here We designed a SPARC-Based Processor in Verilog :D

ARM processor pipeline implementation. Featuring hazard unit, forwarding unit, SRAM & cache memory.

A 32-bit Arm Processor Using Verilog HDL With Hazard Detection, Forwarding Unit, SRAM Memory & A 2-Way Set-Associative Cache.

Verilog Implementation of an ARM LEGv8 CPU

The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.

ARM processor implementation, hazard unit, forwarding unit, SRAM & cache memory.