This project implements a "Dino Run" game on a Basys 3 FPGA Board using SystemVerilog, with a state machine controlling game logic and VGA display output. The design includes modules for random number generation, obstacle management, and a score counter, all integrated to create a functional side-scrolling game.

Tetris in low level programming. Made for Nios II processors.

2022 Fall Bilkent EEE102

Minimal SoC design for alarm clock

МИЭТ, курс "Архитектуры процессорных систем"

It contains 10 assignments based on simulation and testing of hardware codes on BASYS board.

Traffic Light Controller uses VHDL to control intersection traffic lights on an Altera MAX10 FPGA, simulating how to manage traffic signals and pedestrian requests.

SublimeText (highlighting) plugin for working with Xilinx Vivado files (tcl, xdc, etc)

Covers the DEEDS training material for electronic Design

Audio Signal Processing SoC Project Website

Graph Processing Framework that supports || OpenMP || CAPI

An SoC with multiple RISC-V IMA processors.

A collection of debugging busses developed and presented at zipcpu.com

Repository gathering basic modules for CDC purpose