8000 Clang xtensa target by gerekon · Pull Request #2 · tinygo-org/llvm-project · GitHub
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1a2cc2b
[ELF] Exclude sizeof(InputSection) to _WIN32
MaskRay Nov 24, 2024
ae01e3a
[nfc][sancov] Remove unnecessary default argument (#117463)
vitalybuka Nov 24, 2024
215f3dd
[nfc][sancov] Remove unnecessary default argument (#117464)
vitalybuka Nov 24, 2024
8d65073
[AMDGPU] Fix AMDGPUISD::TRAP description (#117453)
s-barannikov Nov 24, 2024
c85c77c
[AVR] Fix shift node descriptions (#117456)
s-barannikov Nov 24, 2024
68a48ec
[clang][analysis][NFC]place the comment to correct position (#117467)
HerrCai0907 Nov 24, 2024
eb4d2f2
[ELF] Simplify reportMissingFeature. NFC
MaskRay Nov 24, 2024
5fa0345
[tsan] Unwind for CHECK according to fast_unwind_on_fatal (#117470)
vitalybuka Nov 24, 2024
4d4a353
[TSan] Increase the number of simultaneously locked mutexes that a th…
gbMattN Nov 24, 2024
2af6ddb
[mlir][ods] Fix missing property elision for variadic segment propert…
Moxinilian Nov 24, 2024
bd7d6c8
[bazel] Port 776476c282bca71d5b856e80e0a88fbd6f3ccdd2
d0k Nov 24, 2024
c4d656a
[bazel] Add missing dependencies for a0ef12c64284abf59bc092b2535cce12…
d0k Nov 24, 2024
f942949
[LLD][COFF] Require explicit specification of ARM64EC target (#116281)
cjacek Nov 24, 2024
0c21ed4
[clang-tidy][NFC] fix release note order (#117484)
HerrCai0907 Nov 24, 2024
7498eaa
[mlir][LLVM] Add the `ConvertToLLVMAttrInterface` and `ConvertToLLVMO…
fabianmcg Nov 24, 2024
08bf901
Revert "[AIX] Fix AIX BuildBot failure as AIX linker doesn't support …
xingxue-ibm Nov 24, 2024
63d9ef5
[AST] Migrate away from PointerUnion::{is,get} (NFC) (#117469)
kazutakahirata Nov 24, 2024
aafe934
[hexagon] Require "asserts" build for widen-not-load test (#117414)
androm3da Nov 24, 2024
6cfaddf
[X86] Split rr/rm CVT schedules on SNB/HSW/BDW (#117494)
RKSimon Nov 24, 2024
0a6d797
[X86] Improve F16C CVT schedules on SNB/HSW/BDW
RKSimon Nov 24, 2024
ff97b28
[ELF] Simplif reportUndefinedSymbol. NFC
MaskRay Nov 24, 2024
c2ffb42
[lldb] Fix TestLoadUnload.py (#117416)
splhack Nov 24, 2024
0dbdc6d
[VPlan] Simplify code to re-use existing basic blocks (NFCI).
fhahn Nov 24, 2024
d8495ed
[ELF] Change getLocation to use ELFSyncStream. NFC
MaskRay Nov 24, 2024
360718f
[test] Improve symbol-location.s to check --defsym
MaskRay Nov 24, 2024
c790d6f
[ELF] isCompatile: avoid a toStr and 2 ErrAlways
MaskRay Nov 24, 2024
c4dc5ed
[ELF] Avoid some toStr and ErrAlways
MaskRay Nov 24, 2024
1cd6275
[ELF] Remove unneeded Twine in ELFSyncStream
MaskRay Nov 24, 2024
590f451
[VPlan] Allow setting IR name for VPDerivedIVRecipe (NFCI).
fhahn Nov 24, 2024
5ce4d4c
[mlir] fix memory effects in GPU barrier elimination (#117432)
ftynse Nov 24, 2024
e3aafe4
[clang-tidy] fix false positive use-internal-linkage for func decl wi…
HerrCai0907 Nov 24, 2024
ae20dbd
[clang][analysis] refactor the unevaluated api (#117474)
HerrCai0907 Nov 24, 2024
605b8da
[clang-tidy] Fix false positive in cppcoreguidelines-avoid-const-or-r…
HerrCai0907 Nov 24, 2024
3c344f9
[clang][tablegen][NFC]add static for internal linkage function (#117479)
HerrCai0907 Nov 24, 2024
cbdd14e
[clang][NFC]add static for internal linkage function (#117482)
HerrCai0907 Nov 24, 2024
2a5e3a6
[AST] Fix a warning
kazutakahirata Nov 25, 2024
095f489
[X86] Swap ports 10 and 11 in SapphireRapids Scheduling Model (#117468)
boomanaiden154 Nov 25, 2024
512dc5c
[X86] Swap ports 10 and 11 in Alder Lake Scheduling Model (#117466)
boomanaiden154 Nov 25, 2024
5ed09d5
[Support] Check zstd decompress result before msan unpoison (#117276)
yingcong-wu Nov 25, 2024
6aeffa1
[ELF] --reproduce: strip directories for --dependency-file=
MaskRay Nov 25, 2024
e70f9e2
[LoongArch] Remove the added in #116762
SixWeining Nov 25, 2024
02408d6
[VP] Refactoring some functions in ExpandVectorPredication.NFC (#115840)
LiqinWeng Nov 25, 2024
5f3eab9
[AVR] Remove extra ROL / ROR operands (#117510)
s-barannikov Nov 25, 2024
bb5bbe5
[RISCV][GISel] Support s32/s64 G_FSUB/FDIV/FNEG without F/D extensions.
topperc Nov 23, 2024
345ca6a
[mlir][Transforms] Dialect conversion: extra signature conversion che…
matthias-springer Nov 25, 2024
0bfc951
[lldb] Remove lldbutil.get_stack_frames (NFC) (#117505)
kastiglione Nov 25, 2024
e26af09
[llvm] Add `BasicTTIImpl::areInlineCompatible` for target feature sub…
heiher Nov 25, 2024
3fb0bea
[RISCV][GISel] Add register class to some isel output patterns so the…
topperc Nov 25, 2024
2523439
[LoongArch] Add a test case for inline compatibility checks (#117144)
heiher Nov 25, 2024
7317a6e
[RISCV][MachineVerifier] Use RegUnit for register liveness checking (…
BeMg Nov 25, 2024
87cc4b4
[NFC] Fix buildbot fail by add riscv64-registered-target
BeMg Nov 25, 2024
9e3215a
[memprof] Add an assert to InstrProfWriter::addMemProfData (#117426)
kazutakahirata Nov 25, 2024
ff7b42c
[memprof] Speed up llvm-profdata (#117446)
kazutakahirata Nov 25, 2024
73bebf9
[LangRef] Update the position of some parameters in the vp intrinsic …
LiqinWeng Nov 25, 2024
b9731a4
[clang-format][doc] Minor cleanup
owenca Nov 25, 2024
2568e52
[X86,SimplifyCFG] Support hoisting load/store with conditional faulti…
phoebewang Nov 25, 2024
b0bdbf4
[mlir][bazel] Port https://github.com/llvm/llvm-project/commit/7498ea…
chsigg Nov 25, 2024
2585b6e
[mlir][bazel] Fix layering check failure.
chsigg Nov 25, 2024
df335b0
[Clang] Preserve partially substituted pack indexing type/expressions…
zyn0217 Nov 25, 2024
404d0e9
[mlir] Adjust code flagged by ClangTidyPerformance (NFC).
akuegel Nov 25, 2024
0fe12a7
[clang-format][NFC] Remove a pointer in ContinuationIndenter
owenca Nov 25, 2024
815a1bb
[SystemZ] Use getSignedConstant() where necessary (#117181)
nikic Nov 25, 2024
3317c9c
[AMDGPU] Use getSignedConstant() where necessary (#117328)
nikic Nov 25, 2024
55f5d68
[win/asan] Recognize mov QWORD PTR [rip + X], reg (#117335)
zmodem Nov 25, 2024
6512e48
[LLD][ARM] Allow R_ARM_SBREL32 relocations in debug info (#116956)
ostannard Nov 25, 2024
1bc9895
[lldb/DWARF] Remove duplicate type filtering (#116989)
labath Nov 25, 2024
866755f
[LLVM] Update backend maintainer (#116622)
nikic Nov 25, 2024
d35098b
[mlir][LLVM][NFC] Move `LLVMStructType` to ODS (#117485)
zero9178 Nov 25, 2024
2b5e2d7
[AArch64][GlobalISel] Extend arm64-vshift.ll test coverage. NFC
davemgreen Nov 25, 2024
7d8d51e
Recommit "[TargetVersion] Only enable on RISC-V and AArch64" (#117110…
BeMg Nov 25, 2024
e5faeb6
[InstCombine] Support reassoc for foldLogicOfFCmps (#116065)
nikic Nov 25, 2024
22ec44f
[DAGCombiner] Add support for scalarising extracts of a vector setcc …
david-arm Nov 25, 2024
321fe74
[InstCombine] Add extra test for eq of parts fold (NFC)
nikic Nov 25, 2024
db14010
[RISCV][TTI] Implement cost of intrinsic abs with LMUL (#115813)
LiqinWeng Nov 25, 2024
84fec77
[lldb][docs] Clarify unit for SVE P register size
DavidSpickett Nov 25, 2024
c537c75
[AArch64][GlobalISel] Scalarize i128 vector sadd_sat/uadd_sat/etc.
davemgreen Nov 25, 2024
f81f47e
[InstCombine] Add fptrunc of max test (NFC)
nikic Nov 25, 2024
15fadeb
[RISCV] Add cost for @llvm.experimental.vp.splat (#117313)
lukel97 Nov 25, 2024
48ec59c
[llvm][AMDGPU] Fold `llvm.amdgcn.wavefrontsize` early (#114481)
AlexVlx Nov 25, 2024
612f8ec
seq_cst is allowed in Flush since OpenMP 5.1. (#114072)
ShashwathiNavada Nov 25, 2024
e477989
[InstCombine] Handle trunc i1 pattern in eq-of-parts fold (#112704)
nikic Nov 25, 2024
ceaf6e9
[clang][bytecode] Support ImplicitValueInitExpr for multi-dim arrays …
tbaederr Nov 25, 2024
5352478
[TableGen] Remove comments from generated validateOperandClass (#117352)
jayfoad Nov 25, 2024
8c5a3a9
[mlir][docs] Update MLIR's PatternRewriter documentation (#116183)
jle-quel Nov 25, 2024
b5a11d3
[SelectOpt] Refactor to prepare for support more select-like operatio…
igogo-x86 Nov 25, 2024
4b71b37
[BOLT] DataAggregator support for binaries with multiple text segment…
paschalis-mpeis Nov 25, 2024
957c2ac
[BOLT] Fix for bughunter.sh in offline mode (#116649)
paschalis-mpeis Nov 25, 2024
b4d49fb
[libc] Remove RPC server API and use the header directly (#117075)
jhuber6 Nov 25, 2024
0ccc389
[libc] Make RPC header work with GCC9
jhuber6 Nov 25, 2024
52755ac
[flang][OpenMP] Use new modifier infrastructure for MAP/FROM/TO claus…
kparzysz Nov 25, 2024
506ca19
[OpenMP] Remove use of '__AMDGCN_WAVEFRONT_SIZE' (#113156)
jhuber6 Nov 25, 2024
4715dec
[XTensa] Use getSignedConstant() for negative values
nikic Nov 25, 2024
3699931
[M68k] Use getSignedConstant() where necessary
nikic Nov 25, 2024
18abc7e
[PatternMatch] Introduce m_c_Select (#114328)
davemgreen Nov 25, 2024
9b76e7f
Revert "[DAGCombiner] Add support for scalarising extracts of a vecto…
david-arm Nov 25, 2024
6f16a8b
[clang][bytecode] Use bitcasts to cast from integer to vector (#117547)
tbaederr Nov 25, 2024
2d62daa
[flang] AArch64 support for BIND(C) derived return types (#114051)
DavidTruby Nov 25, 2024
809c5ac
[X86] Modify tests for constrained rounding functions (#116951)
spavloff Nov 25, 2024
06cb5c9
[LLVM] Update ARM maintainers (#117002)
nikic Nov 25, 2024
4a7a27c
Revert "[SelectOpt] Refactor to prepare for support more select-like …
igogo-x86 Nov 25, 2024
a5506a3
[mlir][spirv] Use assemblyFormat to define {InBound}PtrAccessChainOp …
cydonialis Nov 25, 2024
6de97e9
[libc] Allow NVPTX targets to build in debug mode
jhuber6 Nov 25, 2024
387be04
[libc][NFC] Add const to RPC header members
jhuber6 Nov 25, 2024
7800d59
[SanitizerCoverage] Add gated tracing callbacks support to trace-cmp …
thetruestblue Nov 25, 2024
f9dca5b
[ADT] Add convenience function `filter_to_vector` (#117460)
kuhar Nov 25, 2024
7e3187e
Adding mlir prefix for missing places in TilingInterface.td (#117495)
ddubov100 Nov 25, 2024
57bbdbd
[SLP]Relax assertion in mask combine for non-power-of-2 number of ele…
alexey-bataev Nov 25, 2024
1b18ce5
[X86] vector-interleaved-load-i16-stride-2.ll - regenerate with AVX51…
RKSimon Nov 25, 2024
4d8eb00
[InstCombine] Remove SPF guard for trunc transforms (#117535)
nikic Nov 25, 2024
3de2147
[clang][codegen] Mention the invariant that LLVM demangler should be …
VitaNuo Nov 25, 2024
f953b5e
[SLP]Relax assertion about subvectors mask size
alexey-bataev Nov 25, 2024
b872c4c
[flang][Driver] Fix incorrect condition in test
tarunprabhu Nov 25, 2024
c9e606b
[mlir] Improve doc in `OpFormatGen.cpp` (NFC) (#117564)
chelini Nov 25, 2024
99fd1c5
[libc++][NFC] Don't add legacy transitive includes in <__chrono/durat…
philnik777 Nov 25, 2024
20bd029
[RISCV] Promote fldexp with Zfh. (#117396)
topperc Nov 25, 2024
3db4f5b
AMDGPU: Refine gfx950 xdl-write-vgpr hazard cases (#117285)
arsenm Nov 25, 2024
c3fe5ad
AMDGPU: Handle vcmpx+permalane gfx950 hazard (#117286)
arsenm Nov 25, 2024
27a8afa
AMDGPU: Handle gfx950 valu write vdst + permlane read hazard (#117287)
arsenm Nov 25, 2024
8a2311c
[Offload] Introduce offload-tblgen and initial new API implementation…
callumfare Nov 25, 2024
9cc2502
[clang] hexagon: fix link order for libc/builtins (#117057)
androm3da Nov 25, 2024
d88ed93
[NFC][RISCV] Refactor allocation of the stack space (#116625)
rzinsly Nov 25, 2024
e97fb22
AMDGPU: Add support for load transpose instructions for gfx950 (#117378)
arsenm Nov 25, 2024
6f8e7c1
AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (#117379)
arsenm Nov 25, 2024
8ea7800
[RISCV] Add test case for RVV CSRs with cm.push.
topperc Nov 23, 2024
7ad1084
AMDGPU: MC support for v_cvt_scale_[f16|f32]_fp8 of gfx950. (#117380)
arsenm Nov 25, 2024
91af15b
AMDGPU: MC support for v_cvt_scale_[f16|f32]_bf8 of gfx950. (#117381)
arsenm Nov 25, 2024
8997bf8
AMDGPU: MC support for v_cvt_scalef32_pk_{fp8|bf8}_f32 of gfx950. (#1…
arsenm Nov 25, 2024
70fef78
AMDGPU: MC support for v_cvt_scalef32_pk_f32_[fp|bf]8 of gfx950. (#11…
arsenm Nov 25, 2024
362d8fb
AMDGPU: MC support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 of gfx950.…
arsenm Nov 25, 2024
0077048
[C23] Fixed the value of BOOL_WIDTH (#117364)
AaronBallman Nov 25, 2024
0a140c4
[AMDGPU] Adds pre-commit test for fmul-select combine (#111107)
vg0204 Nov 25, 2024
29828b2
[RISCV] Fix double counting scalar CSRs with Zcmp when emitting cfi_o…
topperc Nov 25, 2024
d7c20a6
[libc][NFC] Move RPC opcodes to the 'shared/' directory as well
jhuber6 Nov 25, 2024
1a86d44
AMDGPU: MC support for v_cvt_scale_fp4<->f32 of gfx950. (#117417)
arsenm Nov 25, 2024
3cb2852
Reapply "[runtimes] Allow building against an installed LLVM tree"
arichardson Nov 25, 2024
d047bee
Revert "[Offload] Introduce offload-tblgen and initial new API implem…
jhuber6 Nov 25, 2024
a5dd646
Add extendhfxf2 into compiler rt (#113897)
biabbas Nov 25, 2024
ed6749a
[RISCV] Promote frexp with Zfh.
topperc Nov 25, 2024
b0bc467
[X86] Fix bad instregex in VPMOVSX/ZX znver4 512-bit patterns.
RKSimon Nov 25, 2024
bb88fd1
[DirectX] Calculate resource binding offsets using the lower bound (#…
bogner Nov 25, 2024
fdf1f69
[CGData][GMF] Skip No Params (#116548)
kyulee-com Nov 25, 2024
b0ca543
[memprof] Remove dead code in MemProfReader (NFC) (#117607)
kazutakahirata Nov 25, 2024
fe3c23b
Revert "[CGData][GMF] Skip No Params (#116548)"
kyulee-com Nov 25, 2024
c94d715
[RISCV] Add coverage for immediate sinking in switch vs branch cases
preames Nov 25, 2024
d733fa1
[RISCV] Consolidate VLS codepaths in stack frame manipulation [nfc] (…
preames Nov 25, 2024
5001f16
AMDGPU: MC support for v_cvt_scalef32_pk_{f|bf}16_fp4 of gfx950. (#11…
arsenm Nov 25, 2024
8e510b8
[RISCV] Fix a warning
kazutakahirata Nov 25, 2024
deab4e9
[flang][cuda][NFC] Add missing default values (#117610)
clementval Nov 25, 2024
96547de
[DirectX] Infrastructure to collect shader flags for each function (#…
bharadwajy Nov 25, 2024
466ff3e
[VPlan] Mark VPIRInstruction::getInstruction) as const (NFCI).
fhahn Nov 25, 2024
30af6fb
[VPlan] Group together helpers for retrieving various VPBlocks (NFCI).
fhahn Nov 25, 2024
9de73b2
[DWARF] Fix DWARTTypePrinter unable to print qualified name for DW_TA…
ZequanWu Nov 25, 2024
fe69a20
Reland [CGData][GMF] Skip No Params (#116548)
kyulee-com Nov 25, 2024
1df34f1
[MCA][X86] Add avx512 test coverage for VPMOV truncation instructions
RKSimon Nov 25, 2024
0988bf8
[LLVM-Reduce] - Null pointer handling during distinct metadata reduct…
rbintel Nov 25, 2024
935da49
AMDGPU: Pass HwMode to AMDGPUGenRegisterInfo (#117449)
arsenm Nov 25, 2024
ece4e12
[mlir][Affine] Split off delinearize parts that depend on last compon…
krzysz00 Nov 25, 2024
76f0ff8
[SLP]Add an extra check to avoid infinite vectorization attempts
alexey-bataev Nov 25, 2024
ab4e066
[X86][MC] Add R_X86_64_CODE_6_GOTTPOFF (#117277)
fzou1 Nov 25, 2024
4c91662
[libc] Resolve multi-line comment error (#117636)
Caslyn Nov 25, 2024
1973270
[libc] suppress string warning in case intrinsics are defined as macr…
SchrodingerZhu Nov 25, 2024
32432a6
[libc] suppress math library warnings on windows (#117638)
SchrodingerZhu Nov 25, 2024
1ea7ced
[mlir][py] Enable disabling loading all registered (#117643)
jpienaar Nov 25, 2024
97fe5fa
[Driver] Pass `--cuda-path` to test (#117415)
bzEq Nov 26, 2024
cac9783
[HLSL] Add `Increment`/`DecrementCounter` methods to structured buffe…
hekota Nov 26, 2024
c2bb056
[SelectionDAG][RISCV][AArch64] Allow f16 STRICT_FLDEXP to be promoted…
topperc Nov 26, 2024
2ab84a6
[X86][FP16][BF16] Improve vectorization of fcmp (#116153)
phoebewang Nov 26, 2024
c1a3960
[X86] Add APX imulzu support. (#116806)
daniel-zabawa Nov 26, 2024
2ed8c5d
[flang][OpenMP] Fix handling of nested loop wrappers in LowerWorkshar…
ivanradanov Nov 26, 2024
ebcaa57
[GISel] #undef macros when they are no longer needed. NFC (#117652)
topperc Nov 26, 2024
bf07a56
[LangRef] Remove extra commas of llvm.vp.ctlz (#117542)
LiqinWeng Nov 26, 2024
dd7aabf
[TTI][RISCV] Deduplicate type-based VP costing of vpcmp/vpcast (#117520)
LiqinWeng Nov 26, 2024
6633916
[RISCV] Remove getPostRAMutations (#117527)
wangpc-pp Nov 26, 2024
6657d4b
[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)
preames Nov 26, 2024
5dd48c4
AMDGPU: MC support for v_cvt_scalef32_pk32_f32_[fp|bf]6 of gfx950 (#1…
arsenm Nov 26, 2024
658db91
AMDGPU: MC support for v_cvt_scalef32_pk32_{bf|f}16_{bf|fp}6 of gfx95…
arsenm Nov 26, 2024
22503a9
AMDGPU: Support v_cvt_scalef32_pk32_{bf|f}6_{bf|fp}16 for gfx950 (#11…
arsenm Nov 26, 2024
c767570
AMDGPU: MC support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 of gfx950.…
arsenm Nov 26, 2024
d727b6f
AMDGPU: MC support for v_cvt_scalef32_pk_fp4_{f|bf}16 on gfx950. (#11…
arsenm Nov 26, 2024
c3377af
[RISCV][CostModel] add cost for cttz/ctlz under the non-zvbb (#117515)
LiqinWeng Nov 26, 2024
a87d484
AMDGPU: Support v_cvt_scalef32_2xpk16_{bf|fp}6_f32 for gfx950. (#117595)
arsenm Nov 26, 2024
5d650a6
AMDGPU: Add support for v_ashr_pk_i8/u8_i32 instructions for gfx950 (…
arsenm Nov 26, 2024
aa7eb57
AMDGPU: Add support for v_dot2_f32_bf16 instruction for gfx950 (#117597)
arsenm Nov 26, 2024
716364e
AMDGPU: Add support for v_dot2c_f32_bf16 instruction for gfx950 (#117…
arsenm Nov 26, 2024
7fc71f7
AMDGPU: Support buffer_atomic_pk_add_bf16 for gfx950 (#117599)
arsenm Nov 26, 2024
a5174de
AMDGPU: Add encodings for minimum3/maximum3 f3 10000 2 for gfx950 (#117600)
arsenm Nov 26, 2024
ae719f0
AMDGPU: Add minimum3/maximum3 pkf16 for gfx950 encodings (#117601)
arsenm Nov 26, 2024
eb5cda4
[flang][cuda] cuf.allocate: Carry over stream to the runtime call (#1…
clementval Nov 26, 2024
ca184cf
[clangd] Support outgoing calls in call hierarchy (#77556)
HighCommander4 Nov 26, 2024
d77cab8
Revert "[clangd] Support outgoing calls in call hierarchy (#77556)" (…
HighCommander4 Nov 26, 2024
6e57186
[clang-format][NFC] Clean up RemoveBraces, RemoveSemi, etc.
owenca Nov 26, 2024
bc28260
[SelectionDAG] Require last operand of (STRICT_)FP_ROUND to be a Targ…
topperc Nov 26, 2024
90f5c8b
[LV][NFC] Auto-generate the test cases related to FindLastIV idioms. …
Mel-Chen Nov 26, 2024
5e3f615
[lldb/NativePDB] Don't create parentless blocks (#117581)
labath Nov 26, 2024
56eb559
[clang][FMV] Fix crash with cpu_specific attribute. (#115762)
labrinea Nov 26, 2024
1b2c8f1
[mlir][linalg] Extract `GeneralizePadOpPattern` into a standalone tra…
banach-space Nov 26, 2024
bb8bf85
[flang] add internal_assoc flag to mark variable captured in internal…
jeanPerier Nov 26, 2024
a96ec01
[AMDGPU] Optimize out s_barrier_signal/_wait (#116993)
piotrAMD Nov 26, 2024
9acd8e3
[clangd] Drop requirement for named template parameters (#117565)
ckandeler Nov 26, 2024
93caee1
[RISCV][SLEEF]: Support SLEEF vector library for RISC-V target. (#114…
mga-sc Nov 26, 2024
2906232
[RISCV] Implement tail call optimization in machine outliner (#115297)
mga-sc Nov 26, 2024
3e1b55c
[SDAG] Don't allow implicit trunc in getConstant() (#117558)
nikic Nov 26, 2024
231e63d
[StructurizeCFG] Refactor insertConditions. NFC. (#115476)
jayfoad Nov 26, 2024
79f59af
[mlir][linalg][nfc] Update "pack-dynamic-inner-tile.mlir" (#117533)
banach-space Nov 26, 2024
36b1811
[win/asan] Add a test skeleton for function GetInstructionSize. (#116…
bernhardu Nov 26, 2024
3414993
[AMDGPU][SplitModule] Fix potential divide by zero (#117602)
frasercrmck Nov 26, 2024
cf602b9
[flang] handle fir.call in AliasAnalysis::getModRef (#117164)
jeanPerier Nov 26, 2024
ad7bb65
[flang] Implement non-standard LNBLNK intrinsic (#117589)
tblah Nov 26, 2024
c0192a0
[flang] implement function form of SYSTEM intrinsic (#117585)
tblah Nov 26, 2024
b9e3a76
[flang][mlir][llvm][OpenMP] Add lowering and translation support for …
NimishMishra Nov 26, 2024
d471c85
[mlir][int-range] Update int range inference for `arith.xori` (#117272)
Hardcode84 Nov 26, 2024
45fdb77
[MCA][X86] Cleanup znver4 instregex patterns for (V)PMOV extension/tr…
RKSimon Nov 26, 2024
4a7b56e
[MLIR][Arith] Add denormal attribute to binary/unary operations (#112…
chelini Nov 26, 2024
4866447
[Clang] Fix name lookup for dependent bases (#114978)
vbe-sc Nov 26, 2024
ec4c47d
Add code completion for C++20 keywords. (#107982)
16bit-ykiko Nov 26, 2024
90df664
[MCA][X86] Fix throughput of (V)PMOV extension/truncation 512-bit ins…
RKSimon Nov 26, 2024
827ebf8
[clang] constexpr built-in elementwise popcount function. (#117473)
c8ef Nov 26, 2024
f94bd3c
Revert "[RISCV] Implement tail call optimization in machine outliner"…
joker-eph Nov 26, 2024
6f5e5b6
[mlir][unittest][nfc] Simplify `getInversePermutation` (#117698)
banach-space Nov 26, 2024
5322415
[PowerPC] Use getSignedConstant() in SelectOptimalAddrMode()
nikic Nov 26, 2024
eb5d69c
[Clang] use begin member expr location for call expr with deducing th…
a-tarasyuk Nov 26, 2024
65c3617
[clang][analysis][NFC]add static for internal linkage function (#117481)
HerrCai0907 Nov 26, 2024
46fcdbb
[InstCombine] Add alias.scope & noalias metadata to test.
fhahn Nov 26, 2024
f4379db
[LoongArch] Support LA V1.1 feature that div.w[u] and mod.w[u] instru…
tangaac Nov 26, 2024
537343d
Revert "[BOLT] DataAggregator support for binaries with multiple text…
zmodem Nov 26, 2024
ead3a2f
[SLP][REVEC] getScalarizationOverhead should not be used when ScalarT…
HanKuanChen Nov 26, 2024
59b3630
[MLIR][SPIR-V] Drop commas from split barrier operations ASM format (…
victor-eds Nov 26, 2024
619e4b7
[MLIR][Arith] SelectOp fix invalid folding (#117555)
7FM Nov 26, 2024
f4d7586
[mlir] Use `llvm::filter_to_vector`. NFC. (#117655)
kuhar Nov 26, 2024
4028bb1
Local: Handle noalias_addrspace in combineMetadata (#103938)
arsenm Nov 26, 2024
ab6677e
[LICM] Only set AA metadata on hoisted load if it executes. (#117204)
fhahn Nov 26, 2024
9efdebc
[Clang] Only ignore special methods for unused private fields in Buil…
Maetveis Nov 26, 2024
624e52b
[DebugInfo] Handle trailing empty blocks when seeking prologue_end sp…
jmorse Nov 26, 2024
db6f627
[clang][SME] Ignore flatten/clang::always_inline statements for calle…
MacDue Nov 26, 2024
b214ca8
[mlir][vector] Rename vector type TD definitions (nfc) (#117150)
banach-space Nov 26, 2024
7577284
[OpenACC][NFC] Update varlist-ast test to check serialization
erichkeane Nov 26, 2024
80df56e
Reapply "[RISCV] Implement tail call optimization in machine outliner…
mga-sc Nov 26, 2024
f7dc1d0
Revert "[Clang] Fix name lookup for dependent bases (#114978)" (#117727)
asi-sc Nov 26, 2024
86f7f08
Fix return value of 'PluginManager::RegisterPlugin()'. (#114120)
Nov 26, 2024
88cff86
[InstCombine] Add tests for #113301 (NFC)
nikic Nov 26, 2024
ced2fc7
[mlir][bufferization] Fix OneShotBufferize when `defaultMemorySpaceFn…
christopherbate Nov 26, 2024
2a0162c
[AArch64][SVE] Change the immediate argument in svextq (#115340)
SpencerAbson Nov 26, 2024
bf440f7
[Clang][NFC] Remove trailing whitespace from Attr{,Docs}.td
philnik777 Nov 26, 2024
b1a34b8
[NFC][Test] Fix PowerPC test gcov_ctr_ref_init.ll (#117577)
syzaara Nov 26, 2024
c55a080
[RISCV] Add shuffle coverage for compress, decompress, and repeat idioms
preames Nov 26, 2024
5a3299a
AMDGPU: Remove some -verify-machineinstrs from tests (#117736)
arsenm Nov 26, 2024
4ab298b
[LLDB][ThreadELFCore] Set all the properties of ELFLinuxSigInfo to a …
Jlalond Nov 26, 2024
5fd4f32
[HLSL] Implement SV_GroupID semantic (#115911)
lizhengxing Nov 26, 2024
78c7024
[OpenACC] Implement 'present' for combined constructs.
erichkeane Nov 26, 2024
bf04885
[Clang][Xtensa] Add Xtensa target.
andreisfr May 31, 2023
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[X86] Improve F16C CVT schedules on SNB/HSW/BDW
Add complete IvyBridge schedule (which is included in the SandyBridge model, IvyBridge was the first to support F16C) - split rr/rm schedules as they usually have very different port usage.

Haswell/Broadwell use Port1 not Port0.

Confirmed with a mixture of Agner + uops.info comparisons.
  • Loading branch information
RKSimon committed Nov 24, 2024
commit 0a6d797c20f6ab53bc09fb66129f603ed6e4b524
8 changes: 4 additions & 4 deletions llvm/lib/Target/X86/X86SchedBroadwell.td
Original file line number Diff line number Diff line change
Expand Up @@ -393,11 +393,11 @@ defm : BWWriteResPair<WriteCvtPD2PS, [BWPort1,BWPort5], 4, [1,1], 2, 5>;
defm : BWWriteResPair<WriteCvtPD2PSY, [BWPort1,BWPort5], 6, [1,1], 2, 6>;
defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;

defm : X86WriteRes<WriteCvtPH2PS, [BWPort0,BWPort5], 2, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSY, [BWPort0,BWPort5], 2, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PS, [BWPort1,BWPort5], 2, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSY, [BWPort1,BWPort5], 2, [1,1], 2>;
defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
defm : X86WriteRes<WriteCvtPH2PSLd, [BWPort0,BWPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSYLd, [BWPort0,BWPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSLd, [BWPort1,BWPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSYLd, [BWPort1,BWPort23], 6, [1,1], 2>;
defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;

defm : X86WriteRes<WriteCvtPS2PH, [BWPort1,BWPort5], 4, [1,1], 2>;
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/X86/X86SchedHaswell.td
Original file line number Diff line number Diff line change
Expand Up @@ -393,12 +393,12 @@ defm : HWWriteResPair<WriteCvtPD2PS, [HWPort1,HWPort5], 4, [1,1], 2, 6>;
defm : HWWriteResPair<WriteCvtPD2PSY, [HWPort1,HWPort5], 6, [1,1], 2, 6>;
defm : HWWriteResPair<WriteCvtPD2PSZ, [HWPort1,HWPort5], 4, [1,1], 2, 6>; // Unsupported = 1

defm : X86WriteRes<WriteCvtPH2PS, [HWPort0,HWPort5], 2, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSY, [HWPort0,HWPort5], 2, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSZ, [HWPort0,HWPort5], 2, [1,1], 2>; // Unsupported = 1
defm : X86WriteRes<WriteCvtPH2PSLd, [HWPort0,HWPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSYLd, [HWPort0,HWPort23], 7, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSZLd, [HWPort0,HWPort23], 7, [1,1], 2>; // Unsupported = 1
defm : X86WriteRes<WriteCvtPH2PS, [HWPort1,HWPort5], 2, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSY, [HWPort1,HWPort5], 2, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSZ, [HWPort1,HWPort5], 2, [1,1], 2>; // Unsupported = 1
defm : X86WriteRes<WriteCvtPH2PSLd, [HWPort1,HWPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSYLd, [HWPort1,HWPort23], 7, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSZLd, [HWPort1,HWPort23], 7, [1,1], 2>; // Unsupported = 1

defm : X86WriteRes<WriteCvtPS2PH, [HWPort1,HWPort5], 4, [1,1], 2>;
defm : X86WriteRes<WriteCvtPS2PHY, [HWPort1,HWPort5], 6, [1,1], 2>;
Expand Down
24 changes: 14 additions & 10 deletions llvm/lib/Target/X86/X86SchedSandyBridge.td
Original file line number Diff line number Diff line change
Expand Up @@ -361,16 +361,20 @@ defm : SBWriteResPair<WriteCvtPD2PS, [SBPort1,SBPort5], 4, [1,1], 2, 6>;
defm : SBWriteResPair<WriteCvtPD2PSY, [SBPort1,SBPort5], 4, [1,1], 2, 7>;
defm : SBWriteResPair<WriteCvtPD2PSZ, [SBPort1,SBPort5], 4, [1,1], 2, 7>; // Unsupported = 1

defm : SBWriteResPair<WriteCvtPH2PS, [SBPort1], 3>;
defm : SBWriteResPair<WriteCvtPH2PSY, [SBPort1], 3>;
defm : SBWriteResPair<WriteCvtPH2PSZ, [SBPort1], 3>; // Unsupported = 1

defm : X86WriteRes<WriteCvtPS2PH, [SBPort1], 3, [1], 1>;
defm : X86WriteRes<WriteCvtPS2PHY, [SBPort1], 3, [1], 1>;
defm : X86WriteRes<WriteCvtPS2PHZ, [SBPort1], 3, [1], 1>; // Unsupported = 1
defm : X86WriteRes<WriteCvtPS2PHSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>;
defm : X86WriteRes<WriteCvtPS2PHYSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>;
defm : X86WriteRes<WriteCvtPS2PHZSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; // Unsupported = 1
// F16C Instructions (IvyBridge+)
defm : X86WriteRes<WriteCvtPH2PS, [SBPort0,SBPort5], 3, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSY, [SBPort0,SBPort5], 3, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSZ, [SBPort0,SBPort5], 3, [1,1], 2>; // Unsupported = 1
defm : X86WriteRes<WriteCvtPH2PSLd, [SBPort0,SBPort23], 8, [1,1], 2>;
defm : X86WriteRes<WriteCvtPH2PSYLd, [SBPort0,SBPort5,SBPort23], 8, [1,1,1], 3>;
defm : X86WriteRes<WriteCvtPH2PSZLd, [SBPort0,SBPort5,SBPort23], 8, [1,1,1], 3>; // Unsupported = 1

defm : X86WriteRes<WriteCvtPS2PH, [SBPort0,SBPort1,SBPort5], 10, [1,1,1], 3>;
defm : X86WriteRes<WriteCvtPS2PHY, [SBPort0,SBPort1,SBPort5], 10, [1,1,1], 3>;
defm : X86WriteRes<WriteCvtPS2PHZ, [SBPort0,SBPort1,SBPort5], 10, [1,1,1], 3>; // Unsupported = 1
defm : X86WriteRes<WriteCvtPS2PHSt, [SBPort0,SBPort1,SBPort23,SBPort4], 13, [1,1,1,1], 4>;
defm : X86WriteRes<WriteCvtPS2PHYSt, [SBPort0,SBPort1,SBPort23,SBPort4], 13, [1,1,1,1], 4>;
defm : X86WriteRes<WriteCvtPS2PHZSt, [SBPort0,SBPort1,SBPort23,SBPort4], 13, [1,1,1,1], 4>; // Unsupported = 1

// Vector integer operations.
defm : X86WriteRes<WriteVecLoad, [SBPort23], 5, [1], 1>;
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/tools/llvm-mca/X86/Broadwell/resources-f16c.s
Original file line number Diff line number Diff line change
Expand Up @@ -45,14 +45,14 @@ vcvtps2ph $0, %ymm0, (%rax)

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
# CHECK-NEXT: - - 4.00 4.00 1.67 1.67 2.00 4.00 - 0.67
# CHECK-NEXT: - - - 8.00 1.67 1.67 2.00 4.00 - 0.67

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: - - 1.00 - - - - 1.00 - - vcvtph2ps %xmm0, %xmm2
# CHECK-NEXT: - - 1.00 - 0.50 0.50 - - - - vcvtph2ps (%rax), %xmm2
# CHECK-NEXT: - - 1.00 - - - - 1.00 - - vcvtph2ps %xmm0, %ymm2
# CHECK-NEXT: - - 1.00 - 0.50 0.50 - - - - vcvtph2ps (%rax), %ymm2
# CHECK-NEXT: - - - 1.00 - - - 1.00 - - vcvtph2ps %xmm0, %xmm2
# CHECK-NEXT: - - - 1.00 0.50 0.50 - - - - vcvtph2ps (%rax), %xmm2
# CHECK-NEXT: - - - 1.00 - - - 1.00 - - vcvtph2ps %xmm0, %ymm2
# CHECK-NEXT: - - - 1.00 0.50 0.50 - - - - vcvtph2ps (%rax), %ymm2
# CHECK-NEXT: - - - 1.00 - - - 1.00 - - vcvtps2ph $0, %xmm0, %xmm2
# CHECK-NEXT: - - - 1.00 0.33 0.33 1.00 - - 0.33 vcvtps2ph $0, %xmm0, (%rax)
# CHECK-NEXT: - - - 1.00 - - - 1.00 - - vcvtps2ph $0, %ymm0, %xmm2
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/tools/llvm-mca/X86/Generic/resources-f16c.s
Original file line number Diff line number Diff line change
Expand Up @@ -22,14 +22,14 @@ vcvtps2ph $0, %ymm0, (%rax)
# CHECK-NEXT: [6]: HasSideEffects (U)

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 vcvtph2ps %xmm0, %xmm2
# CHECK-NEXT: 2 3 1.00 vcvtph2ps %xmm0, %xmm2
# CHECK-NEXT: 2 8 1.00 * vcvtph2ps (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 vcvtph2ps %xmm0, %ymm2
# CHECK-NEXT: 2 8 1.00 * vcvtph2ps (%rax), %ymm2
# CHECK-NEXT: 1 3 1.00 vcvtps2ph $0, %xmm0, %xmm2
# CHECK-NEXT: 1 4 1.00 * vcvtps2ph $0, %xmm0, (%rax)
# CHECK-NEXT: 1 3 1.00 vcvtps2ph $0, %ymm0, %xmm2
# CHECK-NEXT: 1 4 1.00 * vcvtps2ph $0, %ymm0, (%rax)
# CHECK-NEXT: 2 3 1.00 vcvtph2ps %xmm0, %ymm2
# CHECK-NEXT: 3 8 1.00 * vcvtph2ps (%rax), %ymm2
# CHECK-NEXT: 3 10 1.00 vcvtps2ph $0, %xmm0, %xmm2
# CHECK-NEXT: 4 13 1.00 * vcvtps2ph $0, %xmm0, (%rax)
# CHECK-NEXT: 3 10 1.00 vcvtps2ph $0, %ymm0, %xmm2
# CHECK-NEXT: 4 13 1.00 * vcvtps2ph $0, %ymm0, (%rax)

# CHECK: Resources:
# CHECK-NEXT: [0] - SBDivider
Expand All @@ -43,15 +43,15 @@ vcvtps2ph $0, %ymm0, (%rax)

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
# CHECK-NEXT: - - - 8.00 2.00 - 2.00 2.00
# CHECK-NEXT: - - 8.00 4.00 2.00 5.00 2.00 2.00

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
# CHECK-NEXT: - - - 1.00 - - - - vcvtph2ps %xmm0, %xmm2
# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcvtph2ps (%rax), %xmm2
# CHECK-NEXT: - - - 1.00 - - - - vcvtph2ps %xmm0, %ymm2
# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcvtph2ps (%rax), %ymm2
# CHECK-NEXT: - - - 1.00 - - - - vcvtps2ph $0, %xmm0, %xmm2
# CHECK-NEXT: - - - 1.00 1.00 - 0.50 0.50 vcvtps2ph $0, %xmm0, (%rax)
# CHECK-NEXT: - - - 1.00 - - - - vcvtps2ph $0, %ymm0, %xmm2
# CHECK-NEXT: - - - 1.00 1.00 - 0.50 0.50 vcvtps2ph $0, %ymm0, (%rax)
# CHECK-NEXT: - - 1.00 - - 1.00 - - vcvtph2ps %xmm0, %xmm2
# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vcvtph2ps (%rax), %xmm2
# CHECK-NEXT: - - 1.00 - - 1.00 - - vcvtph2ps %xmm0, %ymm2
# CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 vcvtph2ps (%rax), %ymm2
# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - vcvtps2ph $0, %xmm0, %xmm2
# CHECK-NEXT: - - 1.00 1.00 1.00 - 0.50 0.50 vcvtps2ph $0, %xmm0, (%rax)
# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - vcvtps2ph $0, %ymm0, %xmm2
# CHECK-NEXT: - - 1.00 1.00 1.00 - 0.50 0.50 vcvtps2ph $0, %ymm0, (%rax)
10 changes: 5 additions & 5 deletions llvm/test/tools/llvm-mca/X86/Haswell/resources-f16c.s
Original file line number Diff line number Diff line change
Expand Up @@ -45,14 +45,14 @@ vcvtps2ph $0, %ymm0, (%rax)

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
# CHECK-NEXT: - - 4.00 4.00 1.67 1.67 2.00 6.00 - 0.67
# CHECK-NEXT: - - - 8.00 1.67 1.67 2.00 6.00 - 0.67

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: - - 1.00 - - - - 1.00 - - vcvtph2ps %xmm0, %xmm2
# CHECK-NEXT: - - 1.00 - 0.50 0.50 - - - - vcvtph2ps (%rax), %xmm2
# CHECK-NEXT: - - 1.00 - - - - 1.00 - - vcvtph2ps %xmm0, %ymm2
# CHECK-NEXT: - - 1.00 - 0.50 0.50 - - - - vcvtph2ps (%rax), %ymm2
# CHECK-NEXT: - - - 1.00 - - - 1.00 - - vcvtph2ps %xmm0, %xmm2
# CHECK-NEXT: - - - 1.00 0.50 0.50 - - - - vcvtph2ps (%rax), %xmm2
# CHECK-NEXT: - - - 1.00 - - - 1.00 - - vcvtph2ps %xmm0, %ymm2
# CHECK-NEXT: - - - 1.00 0.50 0.50 - - - - vcvtph2ps (%rax), %ymm2
# CHECK-NEXT: - - - 1.00 - - - 1.00 - - vcvtps2ph $0, %xmm0, %xmm2
# CHECK-NEXT: - - - 1.00 0.33 0.33 1.00 1.00 - 0.33 vcvtps2ph $0, %xmm0, (%rax)
# CHECK-NEXT: - - - 1.00 - - - 1.00 - - vcvtps2ph $0, %ymm0, %xmm2
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/tools/llvm-mca/X86/SandyBridge/resources-f16c.s
Original file line number Diff line number Diff line change
Expand Up @@ -22,14 +22,14 @@ vcvtps2ph $0, %ymm0, (%rax)
# CHECK-NEXT: [6]: HasSideEffects (U)

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 vcvtph2ps %xmm0, %xmm2
# CHECK-NEXT: 2 3 1.00 vcvtph2ps %xmm0, %xmm2
# CHECK-NEXT: 2 8 1.00 * vcvtph2ps (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 vcvtph2ps %xmm0, %ymm2
# CHECK-NEXT: 2 8 1.00 * vcvtph2ps (%rax), %ymm2
# CHECK-NEXT: 1 3 1.00 vcvtps2ph $0, %xmm0, %xmm2
# CHECK-NEXT: 1 4 1.00 * vcvtps2ph $0, %xmm0, (%rax)
# CHECK-NEXT: 1 3 1.00 vcvtps2ph $0, %ymm0, %xmm2
# CHECK-NEXT: 1 4 1.00 * vcvtps2ph $0, %ymm0, (%rax)
# CHECK-NEXT: 2 3 1.00 vcvtph2ps %xmm0, %ymm2
# CHECK-NEXT: 3 8 1.00 * vcvtph2ps (%rax), %ymm2
# CHECK-NEXT: 3 10 1.00 vcvtps2ph $0, %xmm0, %xmm2
# CHECK-NEXT: 4 13 1.00 * vcvtps2ph $0, %xmm0, (%rax)
# CHECK-NEXT: 3 10 1.00 vcvtps2ph $0, %ymm0, %xmm2
# CHECK-NEXT: 4 13 1.00 * vcvtps2ph $0, %ymm0, (%rax)

# CHECK: Resources:
# CHECK-NEXT: [0] - SBDivider
Expand All @@ -43,15 +43,15 @@ vcvtps2ph $0, %ymm0, (%rax)

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
# CHECK-NEXT: - - - 8.00 2.00 - 2.00 2.00
# CHECK-NEXT: - - 8.00 4.00 2.00 5.00 2.00 2.00

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
# CHECK-NEXT: - - - 1.00 - - - - vcvtph2ps %xmm0, %xmm2
# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcvtph2ps (%rax), %xmm2
# CHECK-NEXT: - - - 1.00 - - - - vcvtph2ps %xmm0, %ymm2
# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcvtph2ps (%rax), %ymm2
# CHECK-NEXT: - - - 1.00 - - - - vcvtps2ph $0, %xmm0, %xmm2
# CHECK-NEXT: - - - 1.00 1.00 - 0.50 0.50 vcvtps2ph $0, %xmm0, (%rax)
# CHECK-NEXT: - - - 1.00 - - - - vcvtps2ph $0, %ymm0, %xmm2
# CHECK-NEXT: - - - 1.00 1.00 - 0.50 0.50 vcvtps2ph $0, %ymm0, (%rax)
# CHECK-NEXT: - - 1.00 - - 1.00 - - vcvtph2ps %xmm0, %xmm2
# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vcvtph2ps (%rax), %xmm2
# CHECK-NEXT: - - 1.00 - - 1.00 - - vcvtph2ps %xmm0, %ymm2
# CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 vcvtph2ps (%rax), %ymm2
# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - vcvtps2ph $0, %xmm0, %xmm2
# CHECK-NEXT: - - 1.00 1.00 1.00 - 0.50 0.50 vcvtps2ph $0, %xmm0, (%rax)
# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - vcvtps2ph $0, %ymm0, %xmm2
# CHECK-NEXT: - - 1.00 1.00 1.00 - 0.50 0.50 vcvtps2ph $0, %ymm0, (%rax)
0