8000 Support partial vector extension instructions by vestata · Pull Request #545 · sysprog21/rv32emu · GitHub
[go: up one dir, main page]
Skip to content

Support partial vector extension instructions #545

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 4 commits into
base: master
Choose a base branch
from
Open

Support partial vector extension instructions #545

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
fbcfad1
Add decode for RISC-V "V" Vector extension
vestata Dec 17, 2024
c4725d5
Implement vector configuration intructions
vestata Jan 9, 2025
7edf398
Implement basic unit-stride vector load/store
vestata Jan 12, 2025
c3374ea
Modularize single-width vector instruction
vestata Jan 17, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Prev Previous commit
Modularize single-width vector instruction 
To emulate vector registers of length VLEN using an array of uint32_t,
we first handle different SEW values (8, 16, 32) using sew_*b_handler.
Inside the handler, the V*_LOOP macro expands to process different VL
values and operand types, along with its corresponding V*_LOOP_LEFT.

The goal is to maximize code reuse by defining individual operations
next to their respective vector instructions, which can be easily
applied using the OPT() macro.

V*_LOOP execution steps:
1. Copy the operand op1 (op2).
2. Align op1 to the right.
3. Perform the specified operation between op1 and op2.
4. Mask the result according to the corresponding SEW.
5. Shift the result left to align with the corresponding position.
6. Accumulate the result.

In vector register groups, registers should follow the pattern v2*n,
v2*n+1 when lmul = 2, etc. The current implementation allows using any
vector registers except those exceeding v31.

For vector masking, if the corresponding mask bit is 0, the value of the
destination vector register is preserved. The process is as follows:
1. Copy the destination register.
2. Clear the bits corresponding to VL.
3. Store the computed result in ans.
4. Update the destination register with ans.

If ir->vm == 0, vector masking is activated.
  • Loading branch information
@vestata
vestata committed Feb 18, 2025
commit c3374eaa45548cd84ec8a0903b9e99019c063640
1 change: 0 additions & 1 deletion src/rv32_constopt.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1827,5 +1827,4 @@ CONSTOPT(vfwmsac_vv, {})
CONSTOPT(vfwmsac_vf, {})
CONSTOPT(vfwnmsac_vv, {})
CONSTOPT(vfwnmsac_vf, {})

#endif
Loading
Loading
0