- Aachen
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17:17
(UTC +02:00) - https://suoglu.github.io
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Simple-SPI Public
Set of simple modules to communicate using SPI protocol.
Tcl Other UpdatedNov 9, 2023 -
xorshiftPlus Public
Pseudorandom number generator
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Verilog-Utilty-Modules Public
Collection of utility modules written in Verilog
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Simple-UART Public
Set of simple modules to communicate via UART
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Queue-Management-System Public
Simple queue management system
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Pmod Public
Collection of simple interfaces for Digilent Pmods
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MCP4725 Public
Interface module for MCP4725 DAC
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IR-Transreceiver Public
Encoder and decoder modules for infrared receivers, transmitters and remotes
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Simple-I2C Public
Set of simple modules to communicate via I²C Bus.
Verilog Other UpdatedAug 3, 2023 -
HC-SR04 Public
Verilog interface for HC-SR04 Ultrasonic Ranging Module
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16-bit Adder Multiplier hardware on Digilent Basys 3
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Divider Public
Hardware integer divider module
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Digital_Clock Public
Verilog code for a digital clock
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Sequential-CRC-Generator Public
Pair of modules to calculate crc values sequentially
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AXI-lite-slave Public
Slaves for AXI-lite interface
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AXIS-Buffer Public
AXIS buffer to keep data until next stage accepts it. Does not add any latency.
Tcl Other UpdatedAug 3, 2023 -
AXI-GPIO Public
Custom AXI GPIO core with up to 32 input and 32 output ports
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Image-to-Binary Public
Simple script to convert images to BMP files or raw RGB binary file.
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FPAM Public
Combinational adder and multiplier modules for IEEE 754 single-precision and double-precision floating point format.
Verilog Other UpdatedJan 12, 2023 -
VSC-Snippets Public
Some snippets for Verilog HDL to be used in VS Code
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UART-Tool Public
Serial communication tool written in Python 3
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Carry-Save-Multiplier Public
Parameterized and 4-bit carry save multiplier design