Intro

This is a simple batch tensor addition example with Xilinx SDAccel and CMake.
The targeted SDx version is 2019.1 but it also should work fine with 2018.3 without any modifications.

Steps to...

The path to SDAccel platform file(*.xpfm) should be set to the environment variable AWS_PLATFORM.
For configuring CMake and building the host program, run:

mkdir build
cmake ..
make

then,

For Software Emulation:

make compile_swemu
make link_swemu
sh launch_swemu.sh

or

sh autobuild_swemu.sh
sh launch_swemu.sh

For Hardware Emulation:

make compile_hwemu
make link_hwemu
sh launch_hwemu.sh

or

sh autobuild_hwemu.sh
sh launch_hwemu.sh

For Hardware Execution(Real FPGA):

Just make sure that if you are using AWS-F1, the fpga_image.xclbin is converted to fpga_image.awsxclbin and it is available in the build directory.

make compile_hw
make link_hw
sudo sh
source $XILINX_XRT/setup.sh
./MyHostExecutable fpga_image.awsxclbin

or

sh autobuild_hw.sh
sudo sh
source $XILINX_XRT/setup.sh
./MyHostExecutable fpga_image.awsxclbin

PasteBin Agent

In order to automate the building modes, the PasteBin agent is developed to automatically upload log files generated by XOCC during compilation and linking processes to PasteBin. Just make sure that it is enabled in the main CMakeLists.txt and username, password, and API key of your PasteBin account are set.

Data Vectorization

To increase the global memory access bandwidth, bus width of m_axi instances should be maximized. According to the documents, the maximum bus width for m_axi is 512-bits, which is equal to 16 float words. A separate helper header file is used to convert flattened 1-D indices into vectorized indices.
The determined m_axi bus width after implementation is logged in the *_csynth.rpt file, which could be generated through cmake synthesis target, by issuing the following command:

make synthesis

Useful Links

Link1
Link2
SDAccel Development Environment Help for 2019.1
SDx Command and Utility Reference Guide for 2019.1

Libraries

HLS Lib