8000 Backport fix for znver1 miscompilation by mati865 · Pull Request #28 · rust-lang/llvm-project · GitHub
[go: up one dir, main page]

Skip to content

Backport fix for znver1 miscompilation #28

New issue

Have a question 8000 about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Nov 29, 2019
Merged
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Teach the regmask clobber check to check if any subregister is preser…
…ved before considering the super register clobbered

X86 has some calling conventions where bits 127:0 of a vector register are callee saved, but the upper bits aren't. Previously we could detect that the full ymm register was clobbered when the xmm portion was really preserved. This patch checks the subregisters to make sure they aren't preserved.

Fixes PR44140

Differential Revision: https://reviews.llvm.org/D70699
  • Loading branch information
topperc authored and mati865 committed Nov 29, 2019
commit 5d902855b136536d62c847d2b3ff73a6cd7ce603
16 changes: 13 additions & 3 deletions llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -261,15 +261,25 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) {
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);

if (MO.isRegMask())
for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
if (MO.clobbersPhysReg(i)) {
if (MO.isRegMask()) {
auto ClobbersPhysRegAndSubRegs = [&](unsigned PhysReg) {
for (MCSubRegIterator SRI(PhysReg, TRI, true); SRI.isValid(); ++SRI)
if (!MO.clobbersPhysReg(*SRI))
return false;

return true;
};

for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
if (ClobbersPhysRegAndSubRegs(i)) {
DefIndices[i] = Count;
KillIndices[i] = ~0u;
KeepRegs.reset(i);
Classes[i] = nullptr;
RegRefs.erase(i);
}
}
}

if (!MO.isReg()) continue;
unsigned Reg = MO.getReg();
Expand Down
0