[Intel GPU][pt2e]: Collapse 3D input to 2D for matmul in qlinear_pointwise_binary fusion #148423
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/148423
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| def __init__(self): | ||
| super(Model, self).__init__() | ||
| self.linear = torch.nn.Linear(10, 10) | ||
| self.relu = torch.nn.ReLU() |
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| self.relu = torch.nn.ReLU() |
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Thanks for suggestions, since the UT is removed, we may resolve this issue.
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@ZhiweiYan-96 , why do we need to add a dedicated test file? I suppose it should reuse other test files. Right?
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Appreciation for suggestion, this file is not necessary.. I have removed the file and add 3D cases in test_mkldnn_pattern_matcher.py
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@pytorchbot merge |
Merge failedReason: Approvers from one of the following sets are needed:
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Hi @jansel @desertfire, |
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@pytorchbot merge |
Merge startedYour change will be merged once all checks pass (ETA 0-4 Hours). Learn more about merging in the wiki. Questions? Feedback? Please reach out to the PyTorch DevX Team |
# Motivation&Details This PR fix a bug that blocked quantized group convolution before. The bug is 8000 caused by that, grouped convolution requires setting weight scale mask on both group dimension and output channel dimension. This PR fixs the wrong mask in integration and add grouped conv in UT. # UT ` python test/inductor/test_mkldnn_pattern_matcher.py -k test_qconv2d_xpu` # Runtime exemplification ```onednn_verbose,v1,primitive,exec,gpu:0,convolution,jit:ir,forward_training,src:s8::blocked:acdb::f0 wei:s8::blocked:abcde::f0 bia:f32::blocked:a::f0 dst:f32::blocked:acdb::f0,attr-scratchpad:user attr-scales:src0:0:f32+dst:0:f32+wei:3:f32 attr-zero-points:src0:0:s32,alg:convolution_direct,g4mb1_ic128oc128_ih4oh2kh3sh1dh0ph0_iw4ow2kw3sw1dw0pw0,0.0529785`` The verbose shows that we successfully run into quantized convolution, where weight is `abcde` format(group conv). Pull Request resolved: #148522 Approved by: https://github.com/EikanWang, https://github.com/liangan1, https://github.com/jansel ghstack dependencies: #148423
Motivation
During the
qlinear_pointwise_binarylowering pass, dim collapsing only occurs when post-ops isadd. It is the responsibility of C++ kernels to handle dimension for post-opssumDetails
This PR explicitly reshape input from 3D to 2D in op
qlinear_pointwise_binary. Besides, we refractor implementationqlinear_pointwise_binary.tensorto callqlinear_pointwise_binaryfor removing duplicated codes.UT testing
python test/inductor/test_mkldnn_pattern_matcher.py -k test_qlienar_add_xpuStack from ghstack (oldest at bottom):
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