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A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one

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Fast Sail emulation using PyPy/RPython's JIT compiler

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This repository contains Pydrofoil, an experimental emulator for various instruction set architectures. The best tested one is a RISC-V emulator based on the Sail RISC-V ISA model. It achieves fast performance by doing dynamic binary translation (aka just-in-time compilation) from RISC-V guest instructions into host machine instructions. It's built on top of the RPython meta-jit compiler and reuses all its optimizations, backends, etc. The emulator is complete enough to boot (an old version of) Linux up to the login prompt.

It also contains an even more experimental emulator for Aarch64 version 9.4, based on the Sail ARM ISA model, which is itself automatically generated from the ASL code that ARM provides. Booting Linux on that emulator is possible, at least up to the point where the init process starts.

The most recent ISA that is experimentally supported is CHERIoT, a variant of the 32-bit CHERI-RISC-V ISA aimed at supporting secure IoT devices.

See https://docs.pydrofoil.org for the complete documentation. To read a more thorough description of how the project works, please refer to our preprint.

If you want to cite this work, please use the following bibtex snippet:

@article{Bolz-Tereick2025-au,
  title         = "Pydrofoil: accelerating Sail-based instruction set
                   simulators",
  author        = "Bolz-Tereick, CF and Panayi, Luke and McKeogh,
                   Ferdia and Spink, Tom and Berger, Martin",
  abstract      = "We present Pydrofoil, a multi-stage compiler that generates
                   instruction set simulators (ISSs) from processor instruction
                   set architectures (ISAs) expressed in the high-level,
                   verification-oriented ISA specification language Sail.
                   Pydrofoil shows a > 230x speedup over the C-based ISS
                   generated by Sail on our benchmarks, and is based on the
                   following insights. (i) An ISS is effectively an interpreter
                   loop, and tracing just-in-time (JIT) compilers have proven
                   effective at accelerating those, albeit mostly for
                   dynamically typed languages. (ii) ISS workloads are highly
                   atypical, dominated by intensive bit manipulation
                   operations. Conventional compiler optimisations for
                   general-purpose programming languages have limited impact
                   for speeding up such workloads. We develop suitable
                   domain-specific optimisations. (iii) Neither tracing JIT
                   compilers, nor ahead-of-time (AOT) compilation alone, even
                   with domain-specific optimisations, suffice for the
                   generation of performant ISSs. Pydrofoil therefore
                   implements a hybrid approach, pairing an AOT compiler with a
                   tracing JIT built on the meta-tracing PyPy framework. AOT
                   and JIT use domain-specific optimisations. Our benchmarks
                   demonstrate that combining AOT and JIT compilers provides
                   significantly greater performance gains than using either
                   compiler alone.",
  month         =  mar,
  year          =  2025,
  archivePrefix = "arXiv",
  primaryClass  = "cs.PL",
  eprint        = "2503.04389"
}
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