pycom · Xykon · Feb 28, 2020 · Oct 8, 2019 · Oct 8, 2019 · Oct 7, 2019
diff --git a/.gitignore b/.gitignore
@@ -36,6 +36,7 @@ user.props
 .pydevproject
 .settings
 .launch
+.vscode
 
 # Key files (for Flash Encryption and Secure Boot)
 secure_boot_signing_key.pem

diff --git a/Jenkinsfile b/Jenkinsfile
@@ -85,7 +85,8 @@ def flashBuild(short_name, version, variant) {
       unstash 'esp32Tools'
       unstash 'tests'
       unstash 'tools'
-      sh 'python esp32/tools/fw_updater/updater.py --port ' + device_name +' flash -t esp32/build-' + variant + '/' + board_name + '-' + version + '.tar.gz'
+      sh 'python esp32/tools/fw_updater/updater.py --noexit --port ' + device_name +' flash -t esp32/build-' + variant + '/' + board_name + '-' + version + '.tar.gz'
+      sh 'python esp32/tools/fw_updater/updater.py --port ' + device_name +' pybytes --auto_start False'
     }
   }
 }

diff --git a/docs/library/ussl.rst b/docs/library/ussl.rst
@@ -114,6 +114,21 @@ network sockets, both client-side and server-side.
 
        SSL sockets inherit all methods and from the standard sockets, see the :mod:`usocket` module.
 
+    .. function:: ssl.save_session(sock)
+
+       Takes an instance sock of ssl.SSLSocket, and returns an instance of ssl.SSLSession representing saved session data from the socket, which can be used to resume a SSL session later. Example::
+
+          import socket
+          import ssl
+          addr = socket.getaddrinfo('www.google.com', 443)[0][-1]
+          sock_one = ssl.wrap_socket(socket.socket())
+          sock_one.connect(addr) # performs a full ssl handshake
+          session = ssl.save_session(sock_one)
+          sock_one.close()
+          sock_one = None
+          sock_two = ssl.wrap_socket(socket.socket(), saved_session=session)
+          sock_two.connect(addr) # resumes using saved session, resulting in a faster handshake
+
     Exceptions
     ----------
 

diff --git a/esp32/PyJTAG/Readme.md b/esp32/PyJTAG/Readme.md
@@ -1,30 +1,34 @@
 # Short readme for how to use the PyJTAG
 
+## Setup
+Generally follow these rules to setup JTAG debugging on your OS: https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/jtag-debugging/index.html
+
+Download link for OpenOCD for ESP32 from Espressif: https://github.com/espressif/openocd-esp32/releases
+
+
+## Build the firmware
 Create the firmware with `BTYPE=debug` flag.
-Do not use the default pins assigned to UART, SPI, CAN because they are used by the JTAG. Pins not to be used: P4, P9, P10, P23
 
-Detailed information are here: https://pycomiot.atlassian.net/wiki/spaces/FIR/pages/966295564/Usage+of+PyJTAG
+Note: Do not use the default pins assigned to UART, SPI, CAN because they are used by the JTAG. Pins not to be used: P4, P9, P10, P23.
+
+## Setup the PyJTAG board
 
-Setup the PyJTAG board's switches:
+PyJTAG's switches:
  * ESP32 JTAG: all turned ON
  * ESP32 B.LOADER: all turned ON except SAFE_BOOT_SW which is OFF
  * TO LTE UART 1/2: does not matter
  * CURRENT SHUNTS: connected
 
-Place the Pycom board with the reset button towards the Current Shunts.
-
-Generally follow these rules to setup JTAG debugging on your OS: https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/jtag-debugging/index.html
-
-(Download link of OpenOCD for ESP32 from Espressif: https://github.com/espressif/openocd-esp32/releases)
-
-Connect the PyJTAG via usb. You see four new USB devices:
+Place the Pycom board with the reset button towards the Current Shunts. Now connect the PyJTAG via usb. You will see four new USB devices. On Linux this will look like this:
 ```
 $ lsusb -d 0403:
 Bus 001 Device 010: ID 0403
E979
:6011 Future Technology Devices International, Ltd FT4232H Quad HS USB-UART/FIFO IC
 $ ls /dev/ttyUSB?
 /dev/ttyUSB0  /dev/ttyUSB1  /dev/ttyUSB2  /dev/ttyUSB3
 ```
 
+## Start OCD
+
 Go to `esp32` folder in Firmware-Development repository and run:
 ```
 PATH_TO_OPENOCD/bin/openocd -s PATH_TO_OPENOCD/share/openocd/scripts -s PyJTAG -f PyJTAG/interface/ftdi/esp32-pycom.cfg -f PyJTAG/board/esp32-pycom.cfg
@@ -49,9 +53,33 @@ Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica)
 Info : Listening on port 3333 for gdb connections
 ```
 
+## Start GDB
+
 When OpenOCD is running, start GDB from `esp32` folder. Assuming you have a FIPY:
 ```
 xtensa-esp32-elf-gdb -x PyJTAG/gdbinit build/FIPY/debug/application.elf
 ```
 
-In `PyJTAG/gdbinit` a breakpoint is configured at `TASK_Micropython`, so execution should stop there first.
+In `PyJTAG/gdbinit` a breakpoint is configured at `TASK_Micropython`, so execution should stop there first:
+
+```
+Thread 1 hit Temporary breakpoint 1, TASK_Micropython (pvParameters=0x0) at mptask.c:136
+```
+
+
+## REPL
+
+Connect to `/dev/ttyUSB2` to reach the REPL terminal over usb serial. E.g. using pymakr in Atom. 
+
+## Troubleshooting
+If openocd says "Error: Connect failed", try to close gdb and openocd and start over.
+
+If `/dev/ttyUSB0` doesn't show up or disappears, disconnect the PyJTAG board, reconnect and start over.
+
+It can be advisable to use the `gdb` from the latest xtensa toolchain, even if an earlier version is used to build the firmware.
+
+If `gdb` does not reach the `Thread 1 hit Temporary breakpoint ...` line, close and reopen `gdb`.
+
+## Extra
+A few more details are here: https://pycomiot.atlassian.net/wiki/spaces/FIR/pages/966295564/Usage+of+PyJTAG
+
diff --git a/esp32/application.mk b/esp32/application.mk
@@ -369,7 +369,7 @@ SRC_QSTR_AUTO_DEPS +=
 BOOT_LDFLAGS = $(LDFLAGS) -T esp32.bootloader.ld -T esp32.rom.ld -T esp32.peripherals.ld -T esp32.bootloader.rom.ld -T esp32.rom.spiram_incompatible_fns.ld
 
 # add the application linker script(s)
-APP_LDFLAGS += $(LDFLAGS) -T esp32_out.ld -T esp32.project.ld -T esp32.rom.ld -T esp32.peripherals.ld
+APP_LDFLAGS += $(LDFLAGS) -T esp32_out.ld -T esp32.project.ld -T esp32.rom.ld -T esp32.peripherals.ld -T esp32.rom.libgcc.ld
 
 # add the application specific CFLAGS
 CFLAGS += $(APP_INC) -DMICROPY_NLR_SETJMP=1 -DMBEDTLS_CONFIG_FILE='"mbedtls/esp_config.h"' -DHAVE_CONFIG_H -DESP_PLATFORM -DFFCONF_H=\"lib/oofatfs/ffconf.h\" -DWITH_POSIX

diff --git a/esp32/bootloader/lib/libbootloader_support.a b/esp32/bootloader/lib/libbootloader_support.a
diff --git a/esp32/bootloader/lib/libefuse.a b/esp32/bootloader/lib/libefuse.a
diff --git a/esp32/bootloader/lib/liblog.a b/esp32/bootloader/lib/liblog.a
diff --git a/esp32/bootloader/lib/libmicro-ecc.a b/esp32/bootloader/lib/libmicro-ecc.a
diff --git a/esp32/bootloader/lib/libsoc.a b/esp32/bootloader/lib/libsoc.a
diff --git a/esp32/bootloader/lib/libspi_flash.a b/esp32/bootloader/lib/libspi_flash.a