8000 Merge pull request #42 from howjmay/readme · plctlab/numpy@e00b431 · GitHub
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Merge pull request numpy#42 from howjmay/readme
doc: Add description of impl restriction
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‎README.md

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@@ -23,7 +23,7 @@ neon2rvv is a translator of Arm/Aarch64 NEON intrinsics to RISC-V Vector (RVV) E
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### Targets and Limitations
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The preliminary stage development goal of neon2rvv is targeting RV64 architecture with 128 bits vector register size, which means the implementation is compiled with `-march=rv64gcv_zba` flag.
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The preliminary stage development goal of neon2rvv is targeting RV64 architecture with `128 bits vector register size (vlen == 128)`, which means the implementation is compiled with `-march=rv64gcv_zba` flag.
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We are using [RISC-V GNU Compiler Toolchain](https://github.com/riscv-collab/riscv-gnu-toolchain) for development.
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